CN112068098B - Individual radar high-integration signal processing system and signal processing method - Google Patents
Individual radar high-integration signal processing system and signal processing method Download PDFInfo
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- CN112068098B CN112068098B CN202010685298.XA CN202010685298A CN112068098B CN 112068098 B CN112068098 B CN 112068098B CN 202010685298 A CN202010685298 A CN 202010685298A CN 112068098 B CN112068098 B CN 112068098B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
- G01S7/415—Identification of targets based on measurements of movement associated with the target
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
- G01S13/50—Systems of measurement based on relative movement of target
- G01S13/58—Velocity or trajectory determination systems; Sense-of-movement determination systems
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02A—TECHNOLOGIES FOR ADAPTATION TO CLIMATE CHANGE
- Y02A90/00—Technologies having an indirect contribution to adaptation to climate change
- Y02A90/10—Information and communication technologies [ICT] supporting adaptation to climate change, e.g. for weather forecasting or climate simulation
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Abstract
The invention belongs to the technical field of radar signal processing, and discloses a signal processing system and a signal processing method for high integration level of an individual radar, wherein the system comprises the following components: DSP, ADC, DAC and a network port module which are respectively connected with the FPGA, and an upper computer display control terminal module which is communicated with the network port module; the antenna module is connected with the FPGA, the signal output end of the clock generation module in the antenna module is connected with the clock chip, and the clock chip is respectively connected with the ADC and the DAC; I/Q signals of radar echoes in the antenna module are respectively connected with the signal input end of the ADC; the system adopts an FPGA+DSP architecture, the FPGA finishes the functions of radar echo acquisition and signal preprocessing, the DSP processes radar echo data in real time, the acquired data is generated into a trace, the detection of a moving target and the association of a flight path are realized, the processing capacity of the radar echo signal is stronger, the storage capacity is stronger, and the integration level is high.
Description
Technical Field
The invention relates to the technical field of radar signal processing, in particular to a signal processing system and a signal processing method for high integration level of an individual radar.
Background
The individual soldier radar can detect and identify moving targets at night and in severe weather, and can be used for monitoring border and sensitive areas and alarming enemy conditions at ordinary times. The optimization of the volume of the individual soldier radar is convenient for the individual soldier to carry easily during investigation, and is always the important point to be considered during design. The individual radar signal processor is an important component of a radar system, the individual radar signal processor is used for detecting radar echo signals and extracting and processing information, huge data volume needs to be processed and transmitted in real time, and along with the development of the radar system, the system integration level is higher and higher.
The individual radar signal processor is used for collecting, storing and processing radar echoes, and along with the development of radar systems, the system integration level is higher and higher, and signal processing design based on Field programmable gate arrays (Field-Programmable Gate Array, FPGA) has become a trend. The huge data volume of the radar needs to meet the requirements of real-time processing and transmission, and the digital signal processor (Digital Signal Processor, DSP) can meet the requirements of modern digital signal processing such as complex algorithm control structure, high operation speed, flexible addressing mode, strong communication performance and the like, and can be widely applied to the field of signal processing through programming. The signal processing function of the individual radar signal processor can be realized on the DSP, and the moving target detection of radar echo data is completed. Based on the above analysis, the use of either a DSP or FPGA alone as the control core of the data acquisition system is not the best option. If the DSP is combined with the FPGA, the high-speed data processing capacity of the DSP is combined with the high-speed complex combination logic and sequential logic control capacity of the FPGA, the defects between the DSP and the FPGA can be complemented, and the FPGA is more suitable for radar signal processing application.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention aims to provide a signal processing system with high integration level for an individual radar and a signal processing method, the system adopts an FPGA+DSP architecture, combines the advantages of strong logic control capability of the FPGA and high-speed signal processing capability of the DSP, completes the acquisition and signal preprocessing functions of radar echo in the FPGA, and the DSP processes radar echo data in real time, generates point tracks for the acquired data, realizes track association, and completes the moving target detection and movement track association of the radar echo data; the processing capability of the radar echo signal is stronger, the storage capability is stronger, and the integration level is high.
In order to achieve the above purpose, the present invention is realized by the following technical scheme.
An individual radar high-integration signal processing system comprises: the system comprises an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module; the individual radar signal processor comprises an FPGA, a digital signal processor, an analog-digital converter, a digital-analog converter and a network port module;
the antenna module comprises a clock generation module and an antenna switch emission control module;
the FPGA is connected with the digital signal processor through a rapidIO interface, the configuration part and the data transmission of the analog-digital converter are respectively connected with the FPGA through an SPI interface and an LVDS interface, and the configuration part and the data transmission of the digital-analog converter are respectively connected with the FPGA through the SPI interface and the LVDS interface; the FPGA is connected with the network port module through an RGMII interface; the network port module is connected with the upper computer display control terminal module through an Ethernet interface;
the servo module is connected with the FPGA through a two-standard data transceiver RS422 interface;
the antenna switch emission control module is connected with the FPGA through an asynchronous serial RS-232 interface;
the signal output end of the clock generation module is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector, the transformer and the clock chip in the individual radar signal processor; the clock chip is connected with the analog-digital converter and the digital-analog converter through LVDS interfaces respectively;
the I/Q two paths of signals of the radar echo are respectively connected with the signal input end of the analog-digital converter; the signal output end of the digital-to-analog converter is connected with the SMP connector of the antenna module.
Further, DDR3 and EMMC are connected to the outside of the FPGA; and DDR3 is connected to the outside of the digital signal processor.
Further, the analog-to-digital converter comprises an SMP connector, a transformer and an AD chip; the I-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the Q-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the clock chip is connected with the AD chip through an LVDS interface, and the configuration part and the data transmission of the AD chip are respectively connected with the FPGA through an SPI interface and an LVDS interface.
Further, the digital-to-analog converter comprises an SMP connector, a transformer and a DA chip; the signal output end of the DA chip is sequentially connected with the transformer of the digital-to-analog converter and the SMP connector and is connected with the SMP connector of the antenna module; the clock chip is connected with the DA chip through an LVDS interface, and the configuration part and the data transmission of the DA chip are connected with the FPGA through an SPI interface and an LVDS interface respectively.
Furthermore, the EMMC is mainly used for storing a large amount of radar echo data and exporting the radar echo data through the internet access module so as to facilitate data analysis; DDR3 hung on the FPGA is used for caching radar echo data, FPGA programs and data needing preprocessing by the FPGA; DDR3, which is externally hung on the DSP, is used for caching the data processed by the DSP and the DSP program.
Further, the antenna module is used for acquiring radar echo signals; the analog-digital converter is used for sampling radar echo signals and converting the radar echo signals into radar digital signals; the FPGA is used for performing fast Fourier transform on the radar digital signals in the azimuth direction and the distance direction; the DSP is used for realizing the detection of a moving target and the association of tracks through an MTI algorithm and a track association algorithm on the radar signals preprocessed by the FPGA.
(II) an individual radar signal processing method, which comprises the following steps:
step 1, powering on an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module, powering on the servo module for self-checking, and transmitting a normal working signal of the servo module to the upper computer display control terminal module; the upper computer display control terminal module configures working parameters of the antenna module and the servo module, binds the working parameters, and transmits the bound working parameters to a PS end of the FPGA through the network port module;
step 2, the PS end is transmitted to the PL end through an AXI bus, and the control of the antenna module and the servo module is finished through an RS232 interface and an RS422 interface respectively; the antenna module acquires radar echo signals, and the radar echo signals are converted into radar digital signals after ADC sampling;
step 3, preprocessing the radar digital signal through an FPGA to obtain a radar preprocessed signal;
step 4, a radar pretreatment signal is sent to a digital signal processor through a rapidIO interface, and the digital signal processor detects a moving target and correlates a track through an MIT algorithm and a track correlation algorithm on the radar pretreatment signal;
and step 5, transmitting the track association result of the target to the upper computer display control terminal module for display through the network interface module.
Further, in step 3, the preprocessing is to perform fast fourier transform in the azimuth direction and the distance direction, respectively.
Compared with the prior art, the invention has the beneficial effects that:
(1) The high-integration signal processing system of the individual radar adopts an FPGA+DSP architecture, combines the advantages of strong logic control capability of the FPGA and high-speed signal processing capability of the DSP, completes the functions of collecting radar echo and preprocessing signals in the FPGA, completes the related processing of radar echo data by the DSP, carries out real-time processing on the radar echo data, generates a trace point by the collected data, realizes track association, and completes the moving target detection and the movement trace association of the radar echo data. Compared with the traditional individual radar signal processor, the signal processing capacity is stronger, and the storage capacity is stronger.
(2) According to the invention, chips such as FPGA, DSP, ADC, DAC, EMMC and a network port module are integrated on one board, so that the signal processing function of the individual radar is realized on one board, and the integration level is greatly improved.
Drawings
The invention will now be described in further detail with reference to the drawings and to specific examples.
FIG. 1 is a block diagram of an individual radar high-integration signal processing system;
FIG. 2 is a PCB diagram of an individual radar high-integration signal processing system;
fig. 3 is a diagram of a display control terminal module of the upper computer.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only for illustrating the present invention and should not be construed as limiting the scope of the present invention.
Referring to fig. 1, an individual radar high-integration signal processing system includes: the system comprises an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module; the individual radar signal processor comprises an FPGA, a Digital Signal Processor (DSP), a network port module, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC); the ADC comprises an SMP connector, a transformer and an AD chip; the DAC includes an SMP connector, a transformer, and a DA chip. The antenna module comprises a clock generation module and an antenna switch emission control module.
Specifically, the individual radar signal processor integrates an FPGA, a DSP, a network port module, an ADC, a DAC and the like on a board with 140mm x 99.5 mm.
The data line and the address line of the EMMC are connected to the common Bank of the FPGA; the DDR3 interface is directly connected to the Bank502 of the FPGA; the network port module is directly connected to the fixed Bank501 of the FPGA and performs data communication with the MAC layer of the Zynq7000PS system through the RGMII interface. The network port module is connected with the upper computer display control terminal module through an RJ45 Ethernet interface.
The EMMC is operated in parallel by four MTFC64GAKAEEY-4M chips, 32 bit data lines and 256GB are used for storing a large amount of radar echo data, the radar echo data are exported through a network port module, data analysis is convenient, a self-defined file system is realized on ARM, and a user can directly realize the read-write deletion operation of files through an upper computer interface. The ARM end can access DDR3 through a high-performance interface. DDR3 hung on the FPGA is used for caching echo data and data which are needed to be preprocessed by the FPGA. DDR3, which is externally hung on the DSP, is used for caching the data processed by the DSP and the DSP program. The FPGA loading module is used for programming the FPGA program, and the DSP loading module is used for programming the DSP program.
The network port module moves data from the EMMC to the DDR3 through the DMA based on the TCP protocol, and then radar echo data is derived from the DDR3 through the network port module for analysis. Based on UDP protocol, carrying out track association on information such as track distance, angle, speed and the like processed by DSP, sending track association result of the target back to FPGA through RapidIO interface, and transmitting to upper computer display terminal control module for display through network interface module; and the network port module transmits the data of the upper computer display terminal control module to the ARM of the FPGA for unpacking according to a specified communication protocol. The invention selects 88E1116R, the chip supports 10/100/1000Mbps network transmission rate, and the data communication is carried out with the MAC layer of the Zynq7000PS system through the RGMII interface, thereby supporting various speed self-adaption.
The output end of the clock generation module is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector, the transformer and the clock chip in the individual radar signal processor. The clock chip selects LMX2572 with phase synchronization function, one path provides 3500MHz clock for the DA chip, and the LMX2572 provides sampling clock for the AD chip through 3500Mz frequency division. The LMX2572 input is provided with an operating clock by the antenna through the SMP and the connector, so that the synchronization of the radar and the processor clock is ensured.
The ADC consists of an SMP connector, a transformer and an AD chip. The AD chip is connected with the clock chip through an LVDS interface, and the input clock of the AD chip is provided by a differential signal output by the clock chip. The configuration part and the data transmission of the AD chip are respectively connected with the FPGA through an SPI interface and an LVDS interface. The I-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the Q-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip. The ADC is mainly used for sampling and converting echo signals output by the individual radar receiver into digital signals.
From the performance indexes of ADC conversion, such as speed, precision, channel number and the like, the sampling frequency, resolution and precision are gradually improved, the sampling channel is developed from a single channel to a double channel and multiple channels, and the signal acquisition module usually needs to process the multiple channels in parallel so as to meet the requirement of real-time property. Ltc2185 is selected, which is a two-channel simultaneous sampling 16-bit A/D converter, the sampling rate can reach 125Msps, and the acquired radar echo is transmitted to the FPGA through a CMOS output mode. The invention controls the sampling point number of the AD chip and the initial sampling time and the termination sampling time under the repetition frequency period through the ARM end.
The DAC is composed of an SMP connector, a transformer and a DA chip. The DA chip is connected with the clock chip through an LVDS interface, and the input clock of the DA chip is provided by a differential signal output by the clock chip. The DA chip configuration part and the data transmission are respectively connected with the FPGA through an SPI interface and an LVDS interface. The signal output end of the DA chip is sequentially connected with the transformer of the digital-analog converter and the SMP connector and is connected with the SMP connector of the antenna module, the linear frequency modulation signal of the DA chip is output to the transmitting antenna in the antenna module, and the antenna receives echo data and then acquires and transmits the echo data to the FPGA through the ADC.
The function of the DAC is to generate the chirp signal required for the transmit antenna, which is sent to the antenna of the antenna module via the transformer and SMP connector. Through PS and PL end configuration, the central frequency, the starting and stopping frequency and the like of the DA chip sweep frequency are flexibly controlled at the ARM end. AD9914 is selected, the AD9914 is a direct digital frequency synthesizer (DDS), a 12-bit digital-to-analog converter is arranged in the direct digital frequency synthesizer, and the target working rate is up to 3.5GSPS.
The antenna switch emission control module is communicated with the FPGA through an asynchronous serial RS-232 interface, the baud rate is 115200Bps, and the main function is to control the emission of the radar switch by the FPGA.
The servo module and the FPGA are communicated through a two-standard data transceiver RS422 interface, the baud rate is 115200Bps, one path mainly realizes the control of servo self-checking, scanning angle, scanning speed and the like, and the other path is used for readback of servo rotation angle.
The FPGA selects XC7Z045FFG900-2 of Zynq-7000 series, is provided with a dual-core ARM Cortex-A9 processor, and the CPU clock can reach 667Mhz. Control of the plurality of peripheral devices such as ADC, DAC, EMMC, DMA at PL (Programmable Logic) is accomplished at PS (process system), thus eliminating the need to modify the PL for repeated compilation during debugging. Based on UDP protocol, the ARM and the upper computer display control terminal module send and unpack according to the protocol, namely, the packet header and tail information sent to the DAP data packet is generated, and the control instruction of the antenna transmitting switch of the individual radar is obtained through analysis. At the PL end, radar echo data is subjected to FFT (fast Fourier transform) in the azimuth direction and the distance direction, and is moved to the DDR3 hung on the FPGA through DMA to obtain a radar echo processing result, and then the radar echo processing result is transmitted to the DSP through a RapidIO interface. The FPGA mainly completes the collection, storage and preprocessing (FFT is carried out on azimuth and distance directions) of radar data.
TMS320C6678 is selected by the DSP, is an 8-core DSP processor with TI based on KeyStone architecture, and has a working main frequency of up to 1.25GHz for each core, so that powerful fixed point and floating point operation capability is provided. The DSP performs constant false alarm detection on radar echo data preprocessed by the FPGA through the rapidIO interface communication, sorts the radar echo data according to the energy of the targets, outputs the targets with high energy according to the number of limited targets, calculates the distance, speed and angle information of the targets, generates a track, realizes track association, and realizes detection of moving targets and track association of the radar echo data preprocessed by the FPGA through an MTI algorithm and a track association algorithm.
The FPGA performs FFT on the radar echo data sampled by the AD chip in the azimuth direction and the distance direction to obtain preprocessed radar echo data; the preprocessed radar echo data are transmitted to the DSP through the rapidIO interface, and the DSP generates a target track according to the preprocessed radar echo data and outputs the target track to the upper computer display control terminal module; because the noise level exceeds the threshold level and is mistakenly regarded as the event of the signal, namely the false alarm, the constant false alarm detection is carried out on the DSP, the targets with high energy are output according to the sorting of the target energy and the limiting number of the targets; calculating to obtain the distance, speed and angle information of the target through an MTI algorithm, and generating a point trace; and the correlation of target track is realized, and finally, the track correlation result of the target is displayed on the upper computer display control terminal module.
The target to be detected by the radar is typically a moving object, such as an aircraft in the air, a missile, a ship at sea, a vehicle on the ground, etc. But there are many different backgrounds around the target, such as various ground features, trees, etc., that are stationary or have very little speed of movement. Because the speeds of the real target and the clutter background object are different, the speeds of different targets are different, so that echoes of different targets and clutter background can be distinguished. The detection of the moving object can be realized by utilizing the MTI displayed by the moving object.
Track association is the association of recognition of objects and motion trajectories of the objects in a multi-object context. The first step is to select three scanning points meeting the conditions from four scanning values according to a 3/4 logic method as an initial track, pre-judge the target movement position according to the initial track, select the nearest point for association, and associate each new scanning value according to the same method by taking the last associated point as a reference.
Referring to fig. 2, when the single-soldier radar signal processor is used for designing a PCB, DDR3 is as close to a corresponding FPGA or DSP as possible, so as to shorten signal wiring; the high-power-consumption chips are placed in the corresponding areas of the heat dissipation plates with the relative center positions of the boards being 95mm or 50mm, so that heat dissipation is facilitated; the interface with the antenna and the servo peripheral communication interface are arranged on the board side, so that the connection with the peripheral equipment is facilitated.
The signal processing method of the individual soldier radar comprises the following steps:
step 1, the whole system (comprising an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module) is electrified, the servo module is electrified for self-checking, a servo normal working signal is returned to the upper computer display control terminal module, the upper computer display control terminal module starts to configure working parameters of the antenna module and the servo module (refer to fig. 3), and after the configuration is completed, the upper computer display control terminal module carries out parameter binding, and at the moment, the parameters are transmitted to a PS end of an FPGA through a network port module.
And 2, the PS end is transmitted to the PL end through an AXI bus, and then the control of the antenna module and the servo module is completed through an RS232 or RS422 interface. After ADC sampling, the radar echo signal obtained by the antenna receiving end is converted into a radar digital signal to XC7Z045FFG900-2.
Step 3, packaging radar digital signals after FFT, moving the packed frame head and frame tail into the DDR3 hung on the FPGA through DMA by ARM, and then caching through double-port RAM; and sending the packaged radar pretreatment data to the DSP through the rapidIO interface.
And 4, performing constant false alarm detection on the radar pretreatment data by the DSP, outputting targets with high energy according to the number of limited targets after sorting according to the energy, calculating position, speed and angle information of the corresponding output targets, generating a track, further realizing track association, and displaying a target track association result on an upper computer display control terminal module.
While the invention has been described in detail in this specification with reference to the general description and the specific embodiments thereof, it will be apparent to one skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (8)
1. An individual radar high-integration signal processing system, comprising: the system comprises an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module; the individual radar signal processor comprises an FPGA, a digital signal processor, an analog-digital converter, a digital-analog converter and a network port module;
the antenna module comprises a clock generation module and an antenna switch emission control module;
the FPGA is connected with the digital signal processor through a rapidIO interface, the configuration part and the data transmission of the analog-digital converter are respectively connected with the FPGA through an SPI interface and an LVDS interface, and the configuration part and the data transmission of the digital-analog converter are respectively connected with the FPGA through the SPI interface and the LVDS interface; the FPGA is connected with the network port module through an RGMII interface; the network port module is connected with the upper computer display control terminal module through an Ethernet interface;
the servo module is connected with the FPGA through a two-standard data transceiver RS422 interface;
the antenna switch emission control module is connected with the FPGA through an asynchronous serial RS-232 interface;
the signal output end of the clock generation module is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector, the transformer and the clock chip in the individual radar signal processor; the clock chip is connected with the analog-digital converter and the digital-analog converter through LVDS interfaces respectively;
the I/Q two paths of signals of the radar echo are respectively connected with the signal input end of the analog-digital converter; the signal output end of the digital-to-analog converter is connected with the SMP connector of the antenna module.
2. The single-soldier radar high integration signal processing system according to claim 1, wherein DDR3 and EMMC are connected outside the FPGA; and DDR3 is connected to the outside of the digital signal processor.
3. The single-soldier radar high integration signal processing system according to claim 1, wherein the analog-to-digital converter comprises an SMP connector, a transformer and an AD chip; the I-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the Q-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the clock chip is connected with the AD chip through an LVDS interface, and the configuration part and the data transmission of the AD chip are respectively connected with the FPGA through an SPI interface and an LVDS interface.
4. The single-soldier radar high integration signal processing system according to claim 1, wherein the digital-to-analog converter comprises an SMP connector, a transformer and a DA chip; the signal output end of the DA chip is sequentially connected with the transformer of the digital-to-analog converter and the SMP connector and is connected with the SMP connector of the antenna module; the clock chip is connected with the DA chip through an LVDS interface, and the configuration part and the data transmission of the DA chip are connected with the FPGA through an SPI interface and an LVDS interface respectively.
5. The single-soldier radar high integration signal processing system according to claim 2, wherein the EMMC is mainly used for storing a large amount of radar echo data and deriving the radar echo data through a portal module for facilitating data analysis; DDR3 hung on the FPGA is used for caching radar echo data, FPGA programs and data needing preprocessing by the FPGA; DDR3, which is externally hung on the DSP, is used for caching the data processed by the DSP and the DSP program.
6. The individual radar high-integration signal processing system according to claim 5, wherein the antenna module is configured to acquire radar echo signals; the analog-digital converter is used for sampling radar echo signals and converting the radar echo signals into radar digital signals; the FPGA is used for performing fast Fourier transform on the radar digital signals in the azimuth direction and the distance direction; the DSP is used for realizing the detection of a moving target and the association of tracks through an MTI algorithm and a track association algorithm on the radar signals preprocessed by the FPGA.
7. The signal processing method for the individual soldier radar is characterized by comprising the following steps of:
step 1, powering on an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module, powering on the servo module for self-checking, and transmitting a normal working signal of the servo module to the upper computer display control terminal module; the upper computer display control terminal module configures working parameters of the antenna module and the servo module, binds the working parameters, and transmits the bound working parameters to a PS end of the FPGA through the network port module;
step 2, the PS end is transmitted to the PL end through an AXI bus, and the control of the antenna module and the servo module is finished through an RS232 interface and an RS422 interface respectively; the antenna module acquires radar echo signals, and the radar echo signals are converted into radar digital signals after ADC sampling;
step 3, preprocessing the radar digital signal through an FPGA to obtain a radar preprocessed signal;
step 4, a radar pretreatment signal is sent to a digital signal processor through a rapidIO interface, and the digital signal processor detects a moving target and correlates a track through an MIT algorithm and a track correlation algorithm on the radar pretreatment signal;
and step 5, transmitting the track association result of the target to the upper computer display control terminal module for display through the network interface module.
8. The individual radar signal processing method according to claim 7, wherein in step 3, the preprocessing is fast fourier transform in azimuth and distance directions, respectively.
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