CN112068098A - High-integration signal processing system and signal processing method for individual radar - Google Patents

Abstract

The invention belongs to the technical field of radar signal processing, and discloses a high-integration signal processing system and a high-integration signal processing method for an individual radar, wherein the system comprises the following components: the system comprises a DSP, an ADC, a DAC and a network port module which are respectively connected with the FPGA, and an upper computer display control terminal module communicated with the network port module; the antenna module is connected with the FPGA, the signal output end of a clock generation module in the antenna module is connected with a clock chip, and the clock chip is respectively connected with the ADC and the DAC; I/Q signals of radar echoes in the antenna module are respectively connected with a signal input end of the ADC; the system adopts an FPGA + DSP framework, the FPGA completes the functions of radar echo acquisition and signal preprocessing, the DSP performs real-time processing on radar echo data, the acquired data is generated into trace points, the detection of moving targets and the association of the trace are realized, the processing capacity of radar echo signals is stronger, the storage capacity is stronger, and the integration level is high.

Description

High-integration signal processing system and signal processing method for individual radar

Technical Field

The invention relates to the technical field of radar signal processing, in particular to a high-integration signal processing system and a high-integration signal processing method for an individual-soldier radar.

Background

The individual radar can detect and identify moving targets at night and in severe weather environments, and can be used for monitoring and enemy alarming in borders and sensitive areas at ordinary times. The optimized size of the individual radar is always the key point which must be considered in design because the individual radar is convenient to carry during the investigation of infantry. The individual radar signal processor is an important component of a radar system, the individual radar signal processor is used for detecting and extracting and processing radar echo signals, huge data volume needs to be processed and transmitted in real time, and along with the development of the radar system, the system integration level is higher and higher.

The individual radar signal processor collects, stores and processes radar echoes, the system integration level is higher and higher along with the development of a radar system, and the signal processing design based on a Field-Programmable Gate Array (FPGA) becomes a trend. The radar has huge data volume which needs to meet the requirements of real-time processing and transmission, a Digital Signal Processor (DSP) can meet the requirements of modern Digital Signal processing such as complex algorithm control structure, high operation speed, flexible addressing mode, strong communication performance and the like, and the radar can be widely applied to the field of Signal processing through programming. The individual radar signal processor can realize the signal processing function on the DSP and complete the moving target detection of radar echo data. Based on the above analysis, it is not the best choice to adopt DSP or FPGA alone as the control core part of the data acquisition system. If the DSP and the FPGA are combined, the high-speed data processing capability of the DSP is combined with the high-speed complex combinational logic and sequential logic control capability of the FPGA, the defects between the DSP and the FPGA can be complemented, and the method is more suitable for the application of radar signal processing.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide a high-integration signal processing system and a signal processing method for an individual soldier radar, the system adopts an FPGA + DSP framework, combines the advantages of strong logic control capability of the FPGA and high-speed signal processing capability of the DSP, finishes the functions of radar echo acquisition and signal preprocessing on the FPGA, and the DSP processes radar echo data in real time to generate trace points of the acquired data, thereby realizing track association and finishing moving target detection and moving track association of the radar echo data; the radar echo signal processing method has the advantages of stronger processing capability, stronger storage capability and high integration level.

In order to achieve the purpose, the invention is realized by adopting the following technical scheme.

An individual radar high-integration signal processing system comprises: the system comprises an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module; the individual radar signal processor comprises an FPGA, a digital signal processor, an analog-digital converter, a digital-analog converter and a network interface module;

the antenna module comprises a clock generation module and an antenna switch transmission control module;

the FPGA is connected with the digital signal processor through a RapidIO interface, the configuration part and the data transmission of the analog-digital converter are respectively connected with the FPGA through an SPI interface and an LVDS interface, and the configuration part and the data transmission of the digital-analog converter are respectively connected with the FPGA through an SPI interface and an LVDS interface; the FPGA is connected with the network port module through an RGMII interface; the network port module is connected with the upper computer display control terminal module through an Ethernet interface;

the servo module is connected with the FPGA through two paths of standard receiving and transmitting RS422 interfaces;

the antenna switch emission control module is connected with the FPGA through an asynchronous serial RS-232 interface;

the signal output end of the clock generation module is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector, the transformer and the clock chip in the individual radar signal processor; the clock chip is respectively connected with the analog-digital converter and the digital-analog converter through LVDS interfaces;

two paths of signals I/Q of the radar echo are respectively connected with the signal input end of the analog-digital converter; and the signal output end of the digital-analog converter is connected with the SMP connector of the antenna module.

Furthermore, DDR3 and EMMC are externally connected with the FPGA; the digital signal processor is externally connected with DDR 3.

Further, the analog-digital converter comprises an SMP connector, a transformer and an AD chip; the I-path signal of the radar echo is connected with an SMP connector of the antenna module and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the Q-path signal of the radar echo is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the clock chip is connected with the AD chip through an LVDS interface, and the configuration part and the data transmission of the AD chip are respectively connected with the FPGA through an SPI interface and an LVDS interface.

Further, the digital-to-analog converter comprises an SMP connector, a transformer and a DA chip; the signal output end of the DA chip is sequentially connected with a transformer and an SMP connector of the digital-to-analog converter and is connected with the SMP connector of the antenna module; the clock chip is connected with the DA chip through an LVDS interface, and the configuration part and the data transmission of the DA chip are respectively connected with the FPGA through an SPI interface and an LVDS interface.

Furthermore, the EMMC is mainly used for storing a large amount of radar echo data and exporting the radar echo data through the network port module so as to facilitate data analysis; the DDR3 externally hung on the FPGA is used for caching radar echo data, an FPGA program and data needing preprocessing by the FPGA; the DSP-attached DDR3 is used to cache DSP-processed data and DSP programs.

Further, the antenna module is used for acquiring a radar echo signal; the analog-digital converter is used for sampling the radar echo signal and converting the radar echo signal into a radar digital signal; the FPGA is used for performing fast Fourier transform on the radar digital signal in the azimuth direction and the distance direction; the DSP is used for detecting the radar signal preprocessed by the FPGA and realizing the detection of the moving target and the association of the flight path through an MTI algorithm and a flight path association algorithm.

(II) an individual soldier radar signal processing method, comprising the following steps:

step 1, powering on an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module, carrying out power-on self-detection on the servo module, and transmitting a normal working signal of the servo module to the upper computer display control terminal module; the upper computer display control terminal module is configured with the working parameters of the antenna module and the servo module and binds the working parameters, and the bound working parameters are transmitted to the PS end of the FPGA through the network port module;

step 2, the PS end is transmitted to the PL end through an AXI bus, and the control of the antenna module and the servo module is finished through RS232 and RS422 interfaces respectively; the antenna module acquires radar echo signals, and the radar echo signals are converted into radar digital signals after being sampled by the ADC;

step 3, preprocessing the radar digital signal through an FPGA to obtain a radar preprocessing signal;

step 4, sending the radar preprocessing signal to a digital signal processor through a RapidIO interface, and realizing the detection of the moving target and the association of the track by the digital signal processor through an MIT algorithm and a track association algorithm on the radar preprocessing signal;

and 5, transmitting the track correlation result of the target to an upper computer display control terminal module through a network interface module for displaying.

Further, in step 3, the preprocessing is to perform fast fourier transform in the azimuth direction and the distance direction, respectively.

Compared with the prior art, the invention has the beneficial effects that:

(1) the high-integration signal processing system of the individual soldier radar adopts an FPGA + DSP framework, combines the advantages of strong logic control capability of the FPGA and high-speed signal processing capability of the DSP, finishes the functions of radar echo acquisition and signal preprocessing on the FPGA, finishes related processing on radar echo data by the DSP, processes the radar echo data in real time by the DSP, generates point tracks on the acquired data, realizes track association, and finishes moving target detection and moving track association of the radar echo data. Compared with the traditional individual radar signal processor, the invention has stronger signal processing capability and stronger storage capability.

(2) The invention integrates the chips such as the FPGA, the DSP, the ADC, the DAC, the EMMC, the network port module and the like on one board card, realizes the signal processing function of the individual soldier radar on one board card, and greatly improves the integration level.

Drawings

The invention is described in further detail below with reference to the figures and specific embodiments.

FIG. 1 is a diagram of a high-integration signal processing system of an individual soldier radar;

FIG. 2 is a PCB diagram of an individual soldier radar high-integration signal processing system;

fig. 3 is a structure diagram of a display control terminal module of an upper computer.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention.

Referring to fig. 1, an individual radar high-integration signal processing system includes: the system comprises an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module; the individual radar signal processor comprises an FPGA, a Digital Signal Processor (DSP), a network port module, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC); the ADC comprises an SMP connector, a transformer and an AD chip; the DAC comprises an SMP connector, a transformer and a DA chip. The antenna module comprises a clock generation module and an antenna switch transmission control module.

Specifically, the individual soldier radar signal processor integrates an FPGA, a DSP, a network port module, an ADC, a DAC and the like on a board card of 140mm by 99.5 mm.

The data line and the address line of the EMMC are connected to a common Bank of the FPGA; the DDR3 interface is directly connected to the Bank502 of the FPGA; the network port module is directly connected with a fixed Bank501 of the FPGA and carries out data communication with the MAC layer of the Zynq7000PS system through an RGMII interface. The network port module is connected with the upper computer display control terminal module through an RJ45 Ethernet interface.

The EMMC uses four MTFC64GAKAEEY-4M chips for parallel operation, totally has 32 bit data lines and 256GB, is mainly used for storing a large amount of radar echo data and exporting the radar echo data through a network port module so as to be convenient for data analysis, realizes a self-defined file system on the ARM, and enables a user to directly realize read-write deletion operation of files through an upper computer interface. The ARM side may access the DDR3 through a high performance interface. The DDR3 external to the FPGA is used to buffer the echo data and the FPGA program and the data that the FPGA needs to preprocess. The DSP-attached DDR3 is used to cache DSP-processed data and DSP programs. The FPGA loading module is used for programming an FPGA program, and the DSP loading module is used for programming a DSP program.

The network port module transfers data from the EMMC to the DDR3 through the DMA based on the TCP protocol, and then the radar echo data are led out from the DDR3 through the network port module for analysis. Based on a UDP protocol, carrying out track association on information such as the trace point distance, the angle, the speed and the like processed by the DSP, sending a track association result of a target back to the FPGA through a RapidIO interface, and transmitting the track association result to a display terminal control module of an upper computer for display through a network interface module; and the network port module transmits the data of the upper computer display terminal control module to an ARM of the FPGA for unpacking according to a specified communication protocol. The invention selects 88E1116R, the chip supports 10/100/1000Mbps network transmission rate, and the chip carries out data communication with the MAC layer of the Zynq7000PS system through the RGMII interface, thereby supporting various speed self-adaptation.

The output end of the clock generation module is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector, the transformer and the clock chip in the individual radar signal processor. The clock chip selects LMX2572 with phase synchronization function, one path provides 3500MHz clock for DA chip, LMX2572 provides sampling clock for AD chip by frequency division of 3500 Mz. The LMX2572 input is clocked by the antenna through the SMP and connector, ensuring synchronization of the radar and processor clocks.

The ADC is composed of an SMP connector, a transformer and an AD chip. The AD chip is connected with the clock chip through an LVDS interface, and an input clock of the AD chip is provided by a differential signal output by the clock chip. The configuration part and the data transmission of the AD chip are respectively connected with the FPGA through an SPI interface and an LVDS interface. The I-path signal of the radar echo is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; and the Q-path signal of the radar echo is connected with the SMP connector of the antenna module, and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip. The ADC is mainly used for sampling and converting echo signals output by the soldier radar receiver into digital signals.

From performance indexes such as ADC conversion speed, precision, channel number and the like, sampling frequency, resolution and precision are gradually improved, a sampling channel is developed into a double channel and a multi-channel from a single channel, and a signal acquisition module generally needs to perform parallel processing on the multi-channel so as to meet the requirement of real-time performance. Selecting Ltc2185 which is a 16-bit A/D converter with two channels sampling simultaneously, wherein the sampling rate can reach 125Msps, and collecting radar echoes to be transmitted to FPGA through a CMOS output mode. The invention controls the number of sampling points of the AD chip and the initial sampling time and the final sampling time under the repetition frequency period through the ARM end.

The DAC consists of an SMP connector, a transformer and a DA chip. The DA chip is connected with the clock chip through an LVDS interface, and an input clock of the DA chip is provided by a differential signal output by the clock chip. The DA chip configuration part and the data transmission are respectively connected with the FPGA through an SPI interface and an LVDS interface. The signal output end of the DA chip is sequentially connected with a transformer and an SMP connector of the digital-to-analog converter and is connected with the SMP connector of the antenna module, the linear frequency modulation signal of the DA chip is output to a transmitting antenna in the antenna module, and the antenna receives echo data and then transmits the echo data to the FPGA through the ADC.

The function of the DAC is to generate the chirp signal required by the transmitting antenna to be sent to the antenna of the antenna module through the transformer and SMP connector. And the central frequency, the starting frequency, the terminating frequency and the like of the DA chip frequency sweep are flexibly controlled at the ARM end through the configuration of the PS end and the PL end. The AD9914 is selected, the AD9914 is a direct digital frequency synthesizer (DDS), a 12-bit digital-to-analog converter is arranged in the DDS, and the highest target working speed can reach 3.5 GSPS.

The antenna switch emission control module is communicated with the FPGA through an asynchronous serial RS-232 interface, the baud rate is 115200Bps, and the main function is to complete the control of the FPGA on the radar switch emission.

The servo module and the FPGA communicate through two standard receiving and transmitting RS422 interfaces, the baud rate is 115200Bps, one path is mainly used for controlling servo self-checking, scanning angles, scanning speeds and the like, and the other path is used for readback of servo rotation angles.

The FPGA selects Zynq-7000 series XC7Z045FFG900-2, is provided with a dual-core ARM Cortex-A9 processor, and the CPU clock can reach 667 Mhz. The control of a plurality of peripheral devices such as ADC, DAC, EMMC and DMA at the PL (programmable logic) end is finished at the PS (process system) end, so that the PL end does not need to be modified for repeated compiling in the debugging process. Based on a UDP protocol, the ARM and the upper computer display control terminal module are packaged and unpacked according to the protocol, namely, the package head and package tail information sent to a DAP data package is generated, and the control instruction of the antenna emission switch of the individual soldier radar is obtained through analysis. And at the PL end, FFT (fast Fourier transform) is carried out on radar echo data in the azimuth direction and the distance direction, the radar echo data are moved to the DDR3 externally hung on the FPGA through DMA (direct memory access), a radar echo processing result is obtained, and the radar echo processing result is transmitted to the DSP through a RapidIO interface. The FPGA mainly completes the acquisition, storage and preprocessing of radar data (FFT is carried out in the direction of azimuth and the direction of distance).

The DSP selects TMS320C6678, is an 8-core DSP processor with TI based on KeyStone architecture, the work dominant frequency of each core can reach 1.25GHz at most, and powerful fixed-point and floating-point operation capabilities are provided. The DSP and the FPGA communicate through a RapidIO interface, the DSP performs constant false alarm detection on radar echo data preprocessed by the FPGA, sorts according to the energy of targets, outputs the targets with high energy according to the limited number of the targets, calculates the distance, the speed and the angle information of the targets, generates a trace point, and realizes track association, and the DSP performs MTI algorithm and track association algorithm on the radar echo data preprocessed by the FPGA to realize the detection of moving targets and the track association.

The FPGA conducts FFT on radar echo data sampled by the AD chip in the azimuth direction and the distance direction to obtain preprocessed radar echo data; the preprocessed radar echo data are transmitted to the DSP through the RapidIO interface, and the DSP generates a target track according to the preprocessed radar echo data and outputs the target track to the upper computer display control terminal module; because an event that the noise level exceeds the threshold level and is mistaken for a signal, namely a false alarm occurs, constant false alarm detection is carried out on the DSP, the targets are sorted according to the target energy, and the targets with high energy are output according to the limited number of the targets; calculating the distance, speed and angle information of the target through an MTI algorithm to generate a trace point; and finally, displaying the track association result of the target on the upper computer display control terminal module.

The target to be detected by the radar is typically a moving object, such as an airborne aircraft, a missile, a marine vessel, a ground vehicle, etc. But there are many kinds of backgrounds around the target, such as various ground features, trees, etc., which are static or have a small moving speed. Because the speed of the real target is different from that of the clutter background object, and the speed of different targets is different, the echoes of different targets and clutter backgrounds can be distinguished. The MTI can be displayed by utilizing the moving target, so that the detection of the moving target can be realized.

The track association is the association of the identification of the target and the motion track of the target under the background of multiple targets. The first step is to select the three times of scanning points meeting the conditions from the four times of scanning values as the starting track according to the logic method 3/4, the moving position of the target is pre-judged according to the starting track, the nearest point is selected for association, and each new scanning value is associated by using the last time of associated point track as the reference according to the same method.

Referring to fig. 2, when the individual soldier radar signal processor used in the present invention designs a PCB, the DDR3 is as close as possible to the corresponding FPGA or DSP, shortening the signal routing; the high-power-consumption chips are placed in the corresponding area of the heat dissipation plate with the position of 95mm x 50mm relative to the central position of the board card, so that heat dissipation is facilitated; and the peripheral communication interfaces with the antenna and the servo are arranged on the edge of the board, so that the peripheral equipment can be conveniently connected.

(II) the individual soldier radar signal processing method comprises the following steps:

step 1, electrifying the whole system (comprising an individual radar signal processor, an antenna module, a servo module and an upper computer display and control terminal module), electrifying the servo module for self-checking, returning a servo normal working signal to the upper computer display and control terminal module, configuring working parameters (refer to fig. 3) of the antenna module and the servo module by the upper computer display and control terminal module, binding the parameters by the upper computer display and control terminal module after the configuration is completed, and transmitting the parameters to a PS (packet switched) end of an FPGA (field programmable gate array) through a network port module.

And 2, the PS end is transmitted to the PL end through the AXI bus, and then the control of the antenna module and the servo module is finished through the RS232 or RS422 interface. And radar echo signals acquired by an antenna receiving end are converted into radar digital signals to XC7Z045FFG900-2 after being sampled by an ADC (analog to digital converter).

Step 3, packing the radar digital signals after FFT, moving the packed frame head and frame tail to the DDR3 externally hung on the FPGA through DMA by an ARM, and caching through a double-port RAM; and sending the packed radar preprocessing data to the DSP through a RapidIO interface.

And 4, carrying out constant false alarm detection on the radar preprocessed data by the DSP, outputting targets with high energy according to the limited number of targets after sorting according to the energy, calculating position, speed and angle information of the corresponding output targets, generating a trace point, further realizing track association, and displaying a target track association result on an upper computer display control terminal module.

Although the present invention has been described in detail in this specification with reference to specific embodiments and illustrative embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto based on the present invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (8)

1. An individual-soldier radar high-integration signal processing system is characterized by comprising: the system comprises an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module; the individual radar signal processor comprises an FPGA, a digital signal processor, an analog-digital converter, a digital-analog converter and a network interface module;

the antenna module comprises a clock generation module and an antenna switch transmission control module;

the FPGA is connected with the digital signal processor through a RapidIO interface, the configuration part and the data transmission of the analog-digital converter are respectively connected with the FPGA through an SPI interface and an LVDS interface, and the configuration part and the data transmission of the digital-analog converter are respectively connected with the FPGA through an SPI interface and an LVDS interface; the FPGA is connected with the network port module through an RGMII interface; the network port module is connected with the upper computer display control terminal module through an Ethernet interface;

the servo module is connected with the FPGA through two paths of standard receiving and transmitting RS422 interfaces;

the antenna switch emission control module is connected with the FPGA through an asynchronous serial RS-232 interface;

the signal output end of the clock generation module is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector, the transformer and the clock chip in the individual radar signal processor; the clock chip is respectively connected with the analog-digital converter and the digital-analog converter through LVDS interfaces;

two paths of signals I/Q of the radar echo are respectively connected with the signal input end of the analog-digital converter; and the signal output end of the digital-analog converter is connected with the SMP connector of the antenna module.

2. The individual soldier radar high integration signal processing system of claim 1, wherein DDR3, EMMC are externally connected to the FPGA; the digital signal processor is externally connected with DDR 3.

3. The individual soldier radar high integration signal processing system of claim 1, wherein, the analog-to-digital converter comprises an SMP connector, a transformer and an AD chip; the I-path signal of the radar echo is connected with an SMP connector of the antenna module and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the Q-path signal of the radar echo is connected with the SMP connector of the antenna module and is sequentially connected with the SMP connector of the analog-digital converter, the transformer and the AD chip; the clock chip is connected with the AD chip through an LVDS interface, and the configuration part and the data transmission of the AD chip are respectively connected with the FPGA through an SPI interface and an LVDS interface.

4. The individual soldier radar high integration signal processing system of claim 1, in which the digital to analog converter comprises an SMP connector, a transformer and a DA chip; the signal output end of the DA chip is sequentially connected with a transformer and an SMP connector of the digital-to-analog converter and is connected with the SMP connector of the antenna module; the clock chip is connected with the DA chip through an LVDS interface, and the configuration part and the data transmission of the DA chip are respectively connected with the FPGA through an SPI interface and an LVDS interface.

5. The individual soldier radar high integration signal processing system of claim 2, wherein the EMMC is mainly used for storing a large amount of radar echo data and exporting the radar echo data through the network port module to facilitate data analysis; the DDR3 externally hung on the FPGA is used for caching radar echo data, an FPGA program and data needing preprocessing by the FPGA; the DSP-attached DDR3 is used to cache DSP-processed data and DSP programs.

6. The individual soldier radar high integration signal processing system of claim 1, wherein the antenna module is used for acquiring radar return signals; the analog-digital converter is used for sampling the radar echo signal and converting the radar echo signal into a radar digital signal; the FPGA is used for performing fast Fourier transform on the radar digital signal in the azimuth direction and the distance direction; the DSP is used for detecting the radar signal preprocessed by the FPGA and realizing the detection of the moving target and the association of the flight path through an MTI algorithm and a flight path association algorithm.

7. An individual soldier radar signal processing method is characterized by comprising the following steps:

step 1, powering on an individual radar signal processor, an antenna module, a servo module and an upper computer display control terminal module, carrying out power-on self-detection on the servo module, and transmitting a normal working signal of the servo module to the upper computer display control terminal module; the upper computer display control terminal module is configured with the working parameters of the antenna module and the servo module and binds the working parameters, and the bound working parameters are transmitted to the PS end of the FPGA through the network port module;

step 2, the PS end is transmitted to the PL end through an AXI bus, and the control of the antenna module and the servo module is finished through RS232 and RS422 interfaces respectively; the antenna module acquires radar echo signals, and the radar echo signals are converted into radar digital signals after being sampled by the ADC;

step 3, preprocessing the radar digital signal through an FPGA to obtain a radar preprocessing signal;

step 4, sending the radar preprocessing signal to a digital signal processor through a RapidIO interface, and realizing the detection of the moving target and the association of the track by the digital signal processor through an MIT algorithm and a track association algorithm on the radar preprocessing signal;

and 5, transmitting the track correlation result of the target to an upper computer display control terminal module through a network interface module for displaying.

8. The individual soldier radar signal processing method of claim 7, wherein in step 3, the preprocessing is fast Fourier transform in azimuth direction and distance direction, respectively.

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