CN112051690A - 有源矩阵基板及带触摸传感器的液晶显示装置 - Google Patents
有源矩阵基板及带触摸传感器的液晶显示装置 Download PDFInfo
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- CN112051690A CN112051690A CN202010493248.1A CN202010493248A CN112051690A CN 112051690 A CN112051690 A CN 112051690A CN 202010493248 A CN202010493248 A CN 202010493248A CN 112051690 A CN112051690 A CN 112051690A
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Abstract
一种有源矩阵基板及带触摸传感器的液晶显示装置,有源矩阵基板具备:源极金属层,其包含源极总线;下部绝缘层,其覆盖源极金属层;顶栅型的氧化物半导体TFT,其包含设置在下部绝缘层上的氧化物半导体层;层间绝缘层,其覆盖氧化物半导体TFT;像素电极,其设置在层间绝缘层上;共用电极,其包含能作为触摸传感器用的电极发挥功能的多个子共用电极;栅极金属层,其包含栅极总线和栅极电极;漏极金属层,其包含漏极电极;以及多个触摸传感器用配线,其分别电连接到多个子共用电极中的任意一个子共用电极,并且包含于漏极金属层。
Description
技术领域
本发明涉及有源矩阵基板。另外,本发明还涉及具备有源矩阵基板的带触摸传感器的液晶显示装置。
背景技术
近年来,具备触摸传感器的显示装置(以下,称为“触摸面板”)已广泛用于智能手机、平板电脑型便携终端等。对于触摸传感器,已知电阻膜式、静电电容式、光学式等各种方式的触摸传感器。在静电电容式的触摸传感器中,对由物体(例如手指)的接触或接近引起的静电电容的变化进行电检测,从而判别是否为触摸状态。
静电电容式的触摸传感器有如下方式:对触摸传感器用的电极与物体(例如手指)之间所产生的静电电容的变化进行探测的自电容方式;以及使用触摸传感器用的一对电极(发射器电极和接收器电极)产生电场并对电极间的电场变化进行检测的互电容方式。
另外,触摸面板有外置型(在配置于观察者侧的偏振板的进一步观察者侧配置有触摸传感器)和内置型。内置型触摸面板有外嵌型(on-cell)触摸面板和内嵌(in-cell)型触摸面板。在此,单元指显示单元(以下,称为“显示面板”。),例如,液晶显示面板包含以中间隔着液晶层而彼此相对的方式配置的有源矩阵基板(TFT基板)和相对基板,不包含偏振板。“内嵌型”是指在显示面板内具有担负触摸面板功能的层的类型。另一方面,“外嵌型”是指担负触摸面板功能的层配置在显示面板与偏振板之间(例如相对基板与偏振板之间)的类型。另外,还有将担负触摸面板功能的层分别配置在显示面板内、以及显示面板与偏振板之间的“混合型”。内置型触摸面板与外置型触摸面板相比,有利于薄型化、轻量化等,具有能提高光的透射率的优点。
专利文献1公开了在使用作为一种横电场模式的FFS(Fringe Field Switching;边缘场开关)模式的液晶显示面板的内置型触摸面板中,将设置于有源矩阵基板的共用电极用作触摸传感器用的电极。
现有技术文献
专利文献
专利文献1:国际公开第2017/213173号
发明内容
发明要解决的问题
在带触摸传感器的横电场模式的液晶显示面板中,在有源矩阵基板的显示区域除了设置有配置于各像素的TFT及像素电极、以及兼作触摸传感器用的电极(以下,称为“传感器电极”)的共用电极之外,还设置有触摸传感器的驱动用和/或检测用的配线(以下,统称为“触摸传感器用配线”)。因此,与现有的横电场模式的液晶显示面板相比,需要额外地形成触摸传感器用配线及覆盖它的绝缘层。因此,导致制造液晶显示面板所需的光掩模的数量增多。
例如,在FFS模式的液晶显示面板中,一般为在覆盖TFT的层间绝缘层上依次层叠共用电极、电介质层以及像素电极的构成。在该构成中,在层间绝缘层与共用电极之间设置触摸传感器用配线的情况下,在层间绝缘层上会依次层叠触摸传感器用配线、绝缘层、共用电极、电介质层以及像素电极,因此,需要追加用于将成为触摸传感器用配线的导电膜图案化的光掩模、以及用于将覆盖触摸传感器用配线的绝缘层图案化的光掩模。也就是说,制造所需的光掩模会增加2个。
本发明的实施方式是鉴于上述问题而完成的,其目的在于,提供具备触摸传感器用配线并且抑制了制造所需的光掩模的数量的增加的有源矩阵基板、以及具备这样的有源矩阵基板的带触摸传感器的液晶显示装置。
用于解决问题的方案
本说明书公开了以下的项目所述的有源矩阵基板及带触摸传感器的液晶显示装置。
[项目1]
一种有源矩阵基板,具有多个像素区域,上述有源矩阵基板具备:
基板;
源极金属层,其设置在上述基板上,包含多个源极总线;
下部绝缘层,其覆盖上述源极金属层;
氧化物半导体TFT,其配置于上述多个像素区域中的每一个像素区域,并且具有设置在上述下部绝缘层上的氧化物半导体层、设置在上述氧化物半导体层上的栅极绝缘层、以隔着上述栅极绝缘层与上述氧化物半导体层相对的方式设置的栅极电极、以及电连接到上述氧化物半导体层的源极电极及漏极电极;
层间绝缘层,其覆盖上述氧化物半导体TFT;
像素电极,其设置在上述层间绝缘层上,电连接到上述漏极电极;
共用电极,其隔着电介质层与上述像素电极相对,并且包含分别能作为触摸传感器用的电极发挥功能的多个子共用电极;
栅极金属层,其包含多个栅极总线和上述栅极电极;
漏极金属层,其包含上述漏极电极;以及
多个触摸传感器用配线,其分别电连接到上述多个子共用电极中的任意一个子共用电极,并且包含于上述漏极金属层。
[项目2]
根据项目1所述的有源矩阵基板,
上述电介质层设置在上述像素电极上,
上述共用电极设置在上述电介质层上。
[项目3]
根据项目2所述的有源矩阵基板,
上述多个触摸传感器用配线分别在形成于上述电介质层和上述层间绝缘层的接触孔中连接到上述多个子共用电极中的对应的子共用电极。
[项目4]
根据项目1至3中的任意一项所述的有源矩阵基板,
还具备覆盖上述氧化物半导体层和上述栅极金属层的上部绝缘层,
上述多个触摸传感器用配线设置在上述上部绝缘层上。
[项目5]
根据项目1至4中的任意一项所述的有源矩阵基板,
在从上述基板的法线方向观看时,上述多个触摸传感器用配线分别与上述多个源极总线中的任意一个源极总线重叠。
[项目6]
根据项目1至5中的任意一项所述的有源矩阵基板,
上述氧化物半导体TFT的上述源极电极与上述多个源极总线中的任意一个源极总线形成为一体。
[项目7]
根据项目1至6中的任意一项所述的有源矩阵基板,
上述源极金属层包含在从上述基板的法线方向观看时与上述氧化物半导体层的沟道区域重叠的遮光层。
[项目8]
根据项目1至7中的任意一项所述的有源矩阵基板,
上述氧化物半导体层包含In-Ga-Zn-O系半导体。
[项目9]
根据项目8所述的有源矩阵基板,
上述In-Ga-Zn-O系半导体包含结晶质部分。
[项目10]
一种带触摸传感器的液晶显示装置,其特征在于,具备:
项目1至9中的任意一项所述的有源矩阵基板;
相对基板,其以与上述有源矩阵基板相对的方式配置;以及
液晶层,其设置在上述有源矩阵基板与上述相对基板之间。
发明效果
根据本发明的实施方式,能够提供具备触摸传感器用配线并且抑制了制造所需的光掩模的数量的增加的有源矩阵基板、以及具备这样的有源矩阵基板的带触摸传感器的液晶显示装置。
附图说明
图1是示意性地示出本发明的实施方式的带触摸传感器的液晶显示装置(触摸面板)100的截面图。
图2是示出触摸面板100所具备的有源矩阵基板(TFT基板)1中的共用电极CE的配置的例子的图。
图3是示意性地示出TFT基板1的俯视图,示出了TFT基板1的多个像素区域Pix之中的3个像素区域Pix。
图4是示意性地示出TFT基板1的截面图,示出了沿着图3中的4A-4A’线的截面。
图5是示出具有上部源极结构的比较例的TFT基板1’的截面图。
图6是示出在比较例的TFT基板1’中在层间绝缘层23上设置有触摸配线TL的构成的图。
图7A是用于说明TFT基板1的制造方法的工序截面图。
图7B是用于说明TFT基板1的制造方法的工序截面图。
图7C是用于说明TFT基板1的制造方法的工序截面图。
图7D是用于说明TFT基板1的制造方法的工序截面图。
图7E是用于说明TFT基板1的制造方法的工序截面图。
图7F是用于说明TFT基板1的制造方法的工序截面图。
图7G是用于说明TFT基板1的制造方法的工序截面图。
图7H是用于说明TFT基板1的制造方法的工序截面图。
图7I是用于说明TFT基板1的制造方法的工序截面图。
图7J是用于说明TFT基板1的制造方法的工序截面图。
图7K是用于说明TFT基板1的制造方法的工序截面图。
具体实施方式
以下,参照附图来说明本发明的实施方式。在以下参照的附图中,由共同的附图标记表示实质上具有相同功能的构成要素,并且有时省略其说明。另外,为了使说明容易理解,在以下参照的附图中,简化或示意性地示出了构成,或者省略了一部分构成要素。各图所示的构成要素间的尺寸比不一定表示实际的尺寸比。
参照图1来说明本发明的实施方式的带触摸传感器的液晶显示装置(以下,称为“触摸面板”)100。图1是示意性地示出触摸面板100的截面图。
如图1所示,触摸面板100具备:有源矩阵基板(以下,称为“TFT基板”)1;配置为与TFT基板1相对的相对基板(有时也被称为“彩色滤光片基板”)2;设置在TFT基板1与相对基板2之间的液晶层3。虽然在此未图示,但典型来说,相对基板2包含彩色滤光片。另外,虽然在此未图示,但触摸面板100在TFT基板1的背面侧具备背光源(照明元件)。
触摸面板100具有显示图像的功能。另外,触摸面板100具有对使用者在所显示的图像上触摸的位置(触摸位置)进行检测的功能。触摸面板100为所谓的内嵌型的触摸面板。
触摸面板100以横电场模式(更具体地说为FFS模式)进行显示。TFT基板1具有用于对液晶层3施加横向电场(边缘电场)的像素电极及共用电极(相对电极)。
图2是示出TFT基板1中的共用电极CE的配置的例子的图。如图2所示,共用电极CE包含分别能作为触摸传感器用的电极发挥功能的多个子共用电极CEs。多个子共用电极CEs排列为矩阵状。在图示出的例子中,各子共用电极CEs为大致矩形。虽然未在图2中示出,但TFT基板1具有排列为矩阵状的多个像素区域。各子共用电极CEs对应于2个以上的像素区域。
包含多个子共用电极CEs的共用电极CE电连接到共用电压配线CL。在对图像进行显示时,共用电极CE从共用电压配线CL被供应共用电压。
TFT基板1还具有多个触摸传感器用配线(以下称为“触摸配线”)TL和控制器4。
控制器4对图像显示进行控制。另外,控制器4还对触摸位置检测进行控制。
各触摸配线TL电连接到控制器4。另外,各触摸配线TL电连接到多个子共用电极CEs中的任意一个子共用电极CEs(对应的子共用电极CEs)。图2中的黑圆点表示触摸配线TL与子共用电极CEs的连接部位。
在任意的某子共用电极CEs与其它子共用电极CEs等之间形成有寄生电容。当人的手指等触碰触摸面板100的显示画面时,会在其与人的手指等之间形成电容,因此,悬垂于触摸位置的子共用电极CEs的静电电容增加。
在检测触摸位置时,控制器4经由触摸配线TL将用于检测触摸位置的触摸驱动信号供应到子共用电极CEs,另外,经由触摸配线TL接收触摸检测信号。由此,检测各子共用电极CEs的静电电容的变化来检测触摸位置。也就是说,触摸配线TL作为用于发送和接收触摸驱动信号及触摸检测信号的配线发挥功能。
在图2中例示了各触摸配线TL包含2条分支配线TLa及TLb的构成。2条分支配线TLa及TLb分别电连接到对应的子共用电极CEs。通过这种冗余结构,能够防止由于触摸配线TL的断线而导致的检测不良。此外,各触摸配线TL不必一定具有这种冗余结构。
参照图3及图4来说明TFT基板1的具体的构成。图3和图4是示意性地示出TFT基板1的俯视图和截面图。图3示出了TFT基板1的多个像素区域Pix之中的3个像素区域Pix,图4示出了沿着图3中的4A-4A’线的截面。
如图3所示,TFT基板1具有排列为包含多个行及多个列的矩阵状的多个像素区域Pix。TFT基板1的各像素区域Pix为与触摸面板100的各像素对应的区域,有时也简称为“像素”。
如图3和图4所示,TFT基板1具备:基板1a;以及设置在基板1a上的多个栅极总线GL及多个源极总线SL。基板1a是透明的且具有绝缘性。基板1a例如为玻璃基板或者塑料基板。多个栅极总线GL在行方向上延伸。多个源极总线SL在列方向上延伸。
栅极总线GL是通过将栅极用导电膜(栅极金属膜)图案化而形成的。将通过使栅极金属膜图案化而形成的配线和/或电极统称为栅极金属层GM。源极总线SL是通过将源极用导电膜(源极金属膜)图案化而形成的。将通过使源极金属膜图案化而形成的配线和/或电极统称为源极金属层SM。源极金属层SM位于比栅极金属层GM靠下方(也就是说基板1a侧)的位置。以覆盖源极金属层SM的方式设置有下部绝缘层21。
TFT基板1还具备:配置于多个像素区域Pix中的每一个像素区域Pix的氧化物半导体TFT(以下也简称为“TFT”)10及像素电极PE;以及隔着电介质层26与像素电极PE相对的共用电极CE。共用电极CE按每个像素区域至少具有1个狭缝s(在图4中未图示)。此外,狭缝s的数量及形状不限于图示的例子。
TFT10为顶栅型。TFT10具有氧化物半导体层11、栅极绝缘层12、栅极电极13、源极电极14以及漏极电极15。
氧化物半导体层11设置在下部绝缘层21上。栅极绝缘层12设置在氧化物半导体层11上,更具体地说设置在氧化物半导体层11的一部分上。栅极电极13以隔着栅极绝缘层12与氧化物半导体层11相对的方式设置。源极电极14和漏极电极15电连接到氧化物半导体层11。
氧化物半导体层11包含:在从基板1a的法线方向观看时与栅极电极13重叠的沟道区域11c;以及分别配置在沟道区域11c的两侧的第1区域11s及第2区域11d。第1区域11s和第2区域11d可以是电阻率比沟道区域11c小的低电阻区域。
源极电极14电连接到源极总线SL。在图示的例子中,源极电极14与源极总线SL形成为一体,更具体地说,源极总线SL的一部分作为源极电极14发挥功能。也就是说,源极电极14包含于源极金属层SM。此外,源极电极14也可以是以在与源极总线SL的延伸方向不同的方向上延伸的方式,从源极总线SL延伸设置。
在下部绝缘层21形成有使源极电极14露出的开口部21a,在该开口部21a中,氧化物半导体层11的第1区域11s连接到源极电极14。
栅极电极13电连接到栅极总线GL。在图示的例子中,栅极电极13与栅极总线GL形成为一体,更具体地说,栅极总线GL的一部分作为栅极电极13发挥功能。也就是说,栅极电极13包含于栅极金属层GM。此外,栅极电极13也可以是以在与栅极总线GL的延伸方向不同的方向上延伸的方式,从栅极总线GL延伸设置。
以覆盖氧化物半导体层11及栅极电极13(栅极金属层GM)的方式设置有上部绝缘层22。在上部绝缘层22形成有使氧化物半导体层11的第2区域11d的一部分露出的开口部22a。
漏极电极15设置在上部绝缘层22上,在上部绝缘层22的开口部22a中连接到氧化物半导体层11的第2区域11d。漏极电极15是通过将漏极用导电膜(漏极金属膜)图案化而形成的。将通过使漏极金属膜图案化从而形成的配线和/或电极统称为漏极金属层DM。
以覆盖TFT10的方式设置有层间绝缘层23。在图示的例子中,层间绝缘层23具有包含无机绝缘层(钝化膜)24、以及配置在无机绝缘层24上的有机绝缘层(平坦化膜)25的层叠结构。此外,层间绝缘层23也可以不必具有层叠结构。在层间绝缘层23形成有使漏极电极15的至少一部分露出的接触孔(以下称为“像素接触孔”)CHp。
像素电极PE设置在层间绝缘层23上。像素电极PE电连接到漏极电极15。像素电极PE在层间绝缘层23的像素接触孔CHp中连接到漏极电极15。
在像素电极PE上设置有电介质层26。在电介质层26上设置有包含多个子共用电极CEs的共用电极CE。也就是说,共用电极CE位于像素电极PE的上方。
在氧化物半导体层11的基板1a侧(也就是说下方)设置有遮光层27。遮光层27在从基板1a的法线方向观看时与氧化物半导体层11的沟道区域11c重叠。遮光层27由源极金属膜形成。也就是说,遮光层27包含于源极金属层SM。通过遮光层27,能够抑制由于来自背光源的光照射到氧化物半导体层11的沟道区域11c而导致的TFT10的特性劣化。遮光层27可以是电浮置(floating)状态,也可以是被提供一定的电位(固定电位)。
如已经说明的那样,TFT基板1具有多个触摸配线TL。如图4所示,触摸配线TL设置在上部绝缘层22上,由漏极金属膜形成。也就是说,触摸配线TL包含于漏极金属层DM。
多个触摸配线TL中的每一个触摸配线TL在形成于电介质层26和层间绝缘层23的接触孔(以下称为“触摸配线接触孔”)CHt中连接到对应的子共用电极CEs。虽然各触摸配线TL只要在至少1个部位与对应的子共用电极CEs连接即可,但通过在多个部位进行连接,能得到冗余性。
各触摸配线TL在从基板1a的法线方向观看时与多个源极总线SL中的任意一个源极总线SL重叠。也就是说,多个触摸配线TL在与多个源极总线SL大致相同的方向上延伸。
在此,说明“上部源极结构”及“下部源极结构”。
以往,在顶栅型的氧化物半导体TFT中,一般是如下构成:在氧化物半导体层的一部分上隔着栅极绝缘层配置有栅极电极,在覆盖栅极电极的绝缘层上配置有源极电极、漏极电极以及源极总线。也就是说,包含源极总线等的源极金属层位于比包含栅极电极的栅极金属层靠上方的位置。以下,将这种构成称为“上部源极结构”。
相对于此,在TFT基板1中,源极金属层SM位于比栅极金属层GM靠下方(也就是说基板1a侧)的位置。以下,将这种构成称为“下部源极结构”。
图5示出具有上部源极结构的比较例的TFT基板1’。比较例的TFT基板1’与TFT基板1同样地,具有顶栅型的TFT10’。不过,在比较例的TFT基板1’中,源极总线SL及TFT10’的源极电极14是与漏极电极15一起设置在上部绝缘层22上。也就是说,形成在上部绝缘层22上的源极金属层SM包含源极总线SL、源极电极14以及漏极电极15。源极电极14在形成于上部绝缘层22的开口部22b中连接到氧化物半导体层11的第1区域11s。另外,在比较例的TFT基板1’中,像素电极PE位于比共用电极CE靠上方的位置。
图6示出在比较例的TFT基板1’中在层间绝缘层23上设置有触摸配线TL的构成。在图6所示的构成中,在层间绝缘层23上依次层叠有触摸配线TL、覆盖触摸配线TL的绝缘层28、共用电极CE、电介质层26以及像素电极PE。触摸配线TL在形成于绝缘层28的开口部28a中连接到共用电极CE。在图6所示的构成中,在制造TFT基板1’时,需要追加用于将触摸配线用导电膜图案化的光掩模、以及用于将覆盖触摸配线TL的绝缘层28图案化的光掩模。也就是说,制造所需的光掩模会增加2个。
相对于此,在本发明的实施方式的触摸面板100的TFT基板1中,如上所述,触摸配线TL包含于漏极金属层DM。也就是说,触摸配线TL与漏极电极15由相同的导电膜(漏极金属膜)形成。因此,无需增加制造所需的光掩模的数量,就能设置触摸配线TL。
另外,虽然TFT基板1具有下部源极结构,但在设置遮光层27的构成中,如果使源极总线SL与遮光层27由相同的导电膜形成(换言之,如果由源极金属膜形成遮光层27),则也不会产生由于采用下部源极结构(也就是说将源极金属层SM设置在比栅极金属层GM靠下方)而导致的光掩模数量的增加。
此外,虽然也可以考虑由与遮光层27相同的导电膜来形成触摸配线TL,但在该情况下,会使开口率下降,或者使制造工艺的构筑变得困难。这是因为,用于将形成于与遮光层27相同的层(也就是说最下层)的触摸配线TL与位于最上层的共用电极CE连接的接触孔的尺寸必然会变大。如果为了减小接触孔的尺寸而将接触孔的侧面的锥形角设计得小(也就是说使接触孔的侧面变得陡峭),则担心会产生断开、接触电阻的上升等。
另外,在TFT基板1中,触摸配线TL位于层间绝缘层23下,因此,与图6所示那样的、触摸配线TL位于层间绝缘层23上的构成相比,能够减小任意的某子共用电极CEs和重叠于该某子共用电极CEs且未与其电连接的(也就是说不对应的)触摸配线TL之间形成的寄生电容。例如,在图6所示的构成中,触摸配线TL与子共用电极CEs之间仅隔着电介质层26,但在TFT基板1中,不仅是电介质层26,层间绝缘层23也介于触摸配线TL与子共用电极CEs之间。因此,触摸传感器的感测性能(灵敏度)提高,能够容易地实现通过手指及触摸笔均能很好地进行操作的触摸传感器。
从提高开口率的观点出发,优选如所例示的那样,在从基板1a的法线方向观看时,多个触摸配线TL分别与多个源极总线SL中的任意一个源极总线SL重叠。由此,能够将触摸配线TL引出到周边电路,且不会使像素开口率下降。
此外,在此,虽然例示了共用电极CE位于像素电极PE的上方的构成,但也可以与此相反,采用像素电极PE位于共用电极CE的上方的构成。不过,从提高触摸传感器的灵敏度的观点出发,优选共用电极CE位于像素电极PE的上方。
[TFT基板1的制造方法]
参照图7A~图7K来说明TFT基板1的制造方法。图7A~图7K是用于说明TFT基板1的制造方法的工序截面图。
首先,如图7A所示,在基板1a上形成包含源极电极14、源极总线SL以及遮光层27的源极金属层SM。具体地说,首先,在基板1a上形成源极用导电膜(源极金属膜),使用光刻工艺将源极金属膜图案化,从而能够形成源极金属层SM。
作为基板1a,例如能够使用玻璃基板、硅基板、具有耐热性的塑料基板(树脂基板)等。
源极金属膜没有特别限定,能够使用例如包含从铝(Al)、铬(Cr)、铜(Cu)、钽(Ta)、钛(Ti)、钼(Mo)或者钨(W)中选择的元素的金属膜或以这些元素为成分的合金膜等。另外,也可以使用包含它们之中的多个膜的层叠膜。例如,能够使用具有钛膜-铝膜-钛膜的3层结构或者钼膜-铝膜-钼膜的3层结构的层叠膜。此外,源极金属膜不限于3层结构,也可以具有单层或双层结构或4层以上的层叠结构。在此,作为源极金属膜,使用将Ti膜(厚度:15~70nm)作为下层且将Cu膜(厚度:200~500nm)作为上层的层叠膜。
接着,如图7B所示,形成覆盖源极金属层SM的下部绝缘层21。作为下部绝缘层21,能够适当使用氧化硅(SiO2)层、氮化硅(SiNx)层、氧氮化硅(SiOxNy;x>y)层、氮氧化硅(SiNxOy;x>y)层、氧化铝层或者氧化钽层等。下部绝缘层21也可以具有层叠结构。在此,作为下部绝缘层21,例如使用CVD法形成将氮化硅层(厚度:50~600nm)作为下层并且将氧化硅层(厚度:50~600nm)作为上层的层叠膜。如果使用氧化硅膜等氧化物膜作为下部绝缘层21(在下部绝缘层21具有层叠结构的情况下,作为其最上层),则能够通过氧化物膜降低之后形成的氧化物半导体层11的沟道区域11c所产生的氧化缺损,因此,能够抑制沟道区域11c的低电阻化。在形成下部绝缘层21之后,通过光刻工艺,对下部绝缘层21进行图案化(例如干式蚀刻)。由此,形成使源极电极14露出的开口部21a。
接下来,如图7C所示,在下部绝缘层21上形成氧化物半导体层11。具体地说,首先,例如使用溅射法形成氧化物半导体膜,之后,使用光刻工艺对氧化物半导体膜进行图案化,从而能够形成氧化物半导体层11。氧化物半导体膜没有特别限定,例如是具有15nm以上且200nm以下的厚度的In-Ga-Zn-O系半导体膜。
之后,如图7D所示,形成包含栅极绝缘层12、栅极电极13以及栅极总线GL的栅极金属层GM。具体地说,首先,以覆盖氧化物半导体层11的方式,依次形成绝缘膜和栅极用导电膜(栅极金属膜)。绝缘膜例如能通过CVD法形成。栅极金属膜例如能通过溅射法形成。
作为绝缘膜,能够使用与下部绝缘层21同样的绝缘膜(作为下部绝缘层21例示出的绝缘膜)。如果使用氧化硅膜等氧化物膜作为绝缘膜,则能够通过氧化物膜降低氧化物半导体层11的沟道区域11c所产生的氧化缺损,因此,能够抑制沟道区域11c的低电阻化。在此,使用氧化硅膜(厚度:80nm以上且250nm以下)作为绝缘膜。
作为栅极金属膜,能够使用例如包含从铝(Al)、铬(Cr)、铜(Cu)、钽(Ta)、钛(Ti)、钼(Mo)或者钨(W)中选择的元素的金属膜或以这些元素为成分的合金膜等。另外,也可以使用包含它们之中的多个膜的层叠膜。例如,能够使用具有钛膜-铝膜-钛膜的3层结构或者钼膜-铝膜-钼膜的3层结构的层叠膜。此外,栅极金属膜不限于3层结构,也可以具有单层或双层结构或4层以上的层叠结构。在此,作为栅极金属膜,使用将Ti膜(厚度:15~70nm)作为下层且将Cu膜(厚度:200~500nm)作为上层的层叠膜。
接着,使用抗蚀剂掩模对栅极金属膜进行图案化,形成栅极电极13及栅极总线GL。栅极金属膜的图案化能够通过湿式蚀刻或干式蚀刻来进行。之后,使用相同抗蚀剂掩模,对绝缘膜进行图案化。或者,也可以在除去抗蚀剂掩模之后,将栅极电极13作为掩模对绝缘膜进行图案化。由此,得到栅极绝缘层12。绝缘膜的图案化例如能够通过干式蚀刻来进行。
在本工序中,由于使用同一掩模对绝缘膜和栅极金属膜进行图案化,因此,栅极绝缘层12的侧面与栅极电极13的侧面在厚度方向上对齐。也就是说,在从基板1a的法线方向观看时,栅极绝缘层12的周缘与栅极电极13的周缘对齐。此外,也可以是形成绝缘膜并进行图案化来形成栅极绝缘层12,接下来,形成栅极金属膜并进行图案化来形成栅极电极13。
接下来,对氧化物半导体层11进行低电阻化处理。低电阻化处理例如是等离子体处理。由此,在从基板1a的法线方向观看时,氧化物半导体层11中的与栅极电极13及栅极绝缘层12不重叠的第1区域11s及第2区域11d成为电阻率比与栅极电极13及栅极绝缘层12重叠的沟道区域11c低的低电阻区域。第1区域11s及第2区域11d也可以是导电体区域(例如片电阻:200Ω/□以下)。
在低电阻化处理(等离子体处理)中,也可以将氧化物半导体层11中的未被栅极电极13覆盖的部分暴露于还原性等离子体或者包含掺杂元素的等离子体(例如氩等离子体)中。由此,在氧化物半导体层11中的露出的部分11s、11d的表面附近,电阻下降,成为低电阻区域。氧化物半导体层11中的由栅极电极13掩盖的部分11c保留为半导体区域。此外,低电阻化处理的方法及条件等例如记载于特开2008-40343号公报中。为了参考,将特开2008-40343号公报的全部公开内容援引至本说明书。
接着,如图7E所示,形成覆盖氧化物半导体层11及栅极金属层GM的上部绝缘层22。作为上部绝缘层22,能够将氧化硅膜、氮化硅膜、氧氮化硅膜、氮氧化硅膜等无机绝缘层以单层来使用或层叠来使用。无机绝缘层的厚度例如为100nm以上500nm以下。如果使用氮化硅膜等使氧化物半导体还原的绝缘膜来形成上部绝缘层22,则能够使氧化物半导体层11中的与上部绝缘层22接触的区域(在此为第1区域11s及第2区域11d)的电阻率维持得低,因此是优选的。在此,通过CVD法形成SiNx层(厚度:300nm)作为上部绝缘层22。在形成上部绝缘层22之后,例如通过干式蚀刻,在上部绝缘层22形成使氧化物半导体层11的第2区域11d的一部分露出的开口部22a。
接下来,如图7F所示,在上部绝缘层22上形成包含漏极电极15及触摸配线TL的漏极金属层DM。具体地说,首先,在上部绝缘层11上形成漏极用导电膜(漏极金属膜),之后,使用光刻工艺对漏极金属膜进行图案化,从而得到漏极金属层DM。图案化能够通过干式蚀刻或湿式蚀刻来进行。这样,完成TFT10。
作为漏极金属膜,能够使用例如从铝(Al)、铬(Cr)、铜(Cu)、钽(Ta)、钛(Ti)、钼(Mo)或者钨(W)中选择的元素或以这些元素为成分的合金等。例如,可以具有钛膜-铝膜-钛膜的3层结构或者钼膜-铝膜-钼膜等的3层结构的层叠膜。此外,漏极金属膜不限于3层结构,也可以具有单层或双层结构或4层以上的层叠结构。在此,使用将Ti膜(厚度:15~70nm)作为下层且将Cu膜(厚度:200~500nm)作为上层的层叠膜。
之后,如图7G所示,形成覆盖TFT10的层间绝缘层23。层间绝缘层23包含作为钝化膜发挥功能的无机绝缘层24、以及作为平坦化膜发挥功能的有机绝缘层25。无机绝缘层24的材料可以与作为上部绝缘层22的材料例示出的材料相同。在此,通过CVD法形成SiNx层(厚度:例如200nm)作为无机绝缘层24。有机绝缘层25例如可以由感光性树脂材料形成。有机绝缘层25的厚度例如为1~3μm,优选为2~3μm。
接着,如图7H所示,对有机绝缘层25进行图案化,形成与漏极电极15重叠的第1开口部25a、以及与触摸配线TL重叠的第2开口部25b。接下来,如图7I所示,将形成有第1开口部25a及第2开口部25b的有机绝缘层25用作掩模,在无机绝缘层24形成使漏极电极15露出的第1开口部24a、以及使触摸配线TL露出的第2开口部24b。有机绝缘层25的第1开口部25a和无机绝缘层24的第1开口部24a构成像素接触孔CHp。此外,也可以在对有机绝缘层25进行了图案化之后,另外设置蚀刻掩模,利用该蚀刻掩模对无机绝缘层24进行图案化,形成第1开口部24a及第2开口部24b。
之后,如图7J所示,在层间绝缘层23上形成像素电极PE。具体地说,首先,在层间绝缘层23上,例如通过溅射法形成第1透明导电膜。作为第1透明导电膜的材料,能够使用铟-锡氧化物(ITO)、铟-锌氧化物、ZnO等金属氧化物。在此,形成具有20~300nm的厚度的铟-锌氧化物膜作为第1透明导电膜。之后,使用光刻工艺对第1透明导电膜进行图案化(例如湿式蚀刻),从而能够形成像素电极PE。
接着,如图7K所示,形成覆盖像素电极PE的电介质层26。电介质层26的材料可以与作为无机绝缘层24的材料例示出的材料相同。在此,通过CVD法形成具有50~500nm的厚度的SiN膜作为电介质层26。之后,对电介质层26进行蚀刻,形成与触摸配线TL重叠的开口部26a。电介质层26的开口部26a、有机绝缘层25的第2开口部25b以及无机绝缘层24的第2开口部24b构成触摸配线接触孔CHt。
之后,在电介质层26上形成共用电极CE,从而得到图4所示的TFT基板1。关于共用电极CE的形成,具体地说,首先,在电介质层26上例如通过溅射法形成第2透明导电膜。作为第2透明导电膜的材料,能够使用与作为第1透明导电膜的材料例示出的材料相同的材料。在此,形成具有20~300nm的厚度的铟-锌氧化物膜作为第2透明导电膜。之后,使用光刻工艺对第2透明导电膜进行图案化(例如湿式蚀刻),从而能够形成共用电极CE。
[关于氧化物半导体]
氧化物半导体层11中包含的氧化物半导体可以是非晶质氧化物半导体,也可以是具有结晶质部分的结晶质氧化物半导体。作为结晶质氧化物半导体,可列举多晶氧化物半导体、微晶氧化物半导体、c轴大体垂直于层面取向的结晶质氧化物半导体等。
氧化物半导体层11也可以具有2层以上的层叠结构。在氧化物半导体层11具有层叠结构的情况下,氧化物半导体层11可以包含非晶质氧化物半导体层和结晶质氧化物半导体层。或者,也可以包含结晶结构不同的多个结晶质氧化物半导体层。另外,也可以包含多个非晶质氧化物半导体层。在氧化物半导体层11具有包含上层和下层的2层结构的情况下,优选上层所包含的氧化物半导体的能隙大于下层所包含的氧化物半导体的能隙。不过,在这些层的能隙的差比较小的情况下,下层的氧化物半导体的能隙也可以大于上层的氧化物半导体的能隙。
非晶质氧化物半导体及上述的各结晶质氧化物半导体的材料、结构、成膜方法以及具有层叠结构的氧化物半导体层的构成等例如记载于特开2014-007399号公报中。为了参考,将特开2014-007399号公报的全部公开内容援引至本说明书。
氧化物半导体层11例如可以包含In、Ga以及Zn中的至少1种金属元素。在本实施方式中,氧化物半导体层11例如包含In-Ga-Zn-O系的半导体(例如铟镓锌氧化物)。在此,In-Ga-Zn-O系的半导体是In(铟)、Ga(镓)、Zn(锌)的三元系氧化物,In、Ga以及Zn的比例(组成比)没有特别限定,例如包含In:Ga:Zn=2:2:1、In:Ga:Zn=1:1:1、In:Ga:Zn=1:1:2等。这种氧化物半导体层7能由包含In-Ga-Zn-O系的半导体的氧化物半导体膜形成。
In-Ga-Zn-O系的半导体可以是非晶体质的,也可以是结晶质的。作为结晶质In-Ga-Zn-O系的半导体,优选c轴大体垂直于层面取向的结晶质In-Ga-Zn-O系的半导体。
此外,结晶质In-Ga-Zn-O系的半导体的结晶结构例如公开于上述的特开2014-007399号公报、特开2012-134475号公报以及特开2014-209727号公报等。为了参考,将特开2012-134475号公报及特开2014-209727号公报的全部公开内容援引至本说明书。具有In-Ga-Zn-O系半导体层的TFT具有高迁移率(与a-SiTFT相比超过20倍)和低漏电流(与a-SiTFT相比不到百分之一),因此,适合用作驱动TFT(例如,在包含多个像素的显示区域的周边设置在与显示区域相同的基板上的驱动电路所包含的TFT)和像素TFT(设置于像素的TFT)。
氧化物半导体层7也可以包含其它氧化物半导体来代替In-Ga-Zn-O系半导体。例如可以包含In-Sn-Zn-O系半导体(例如In2O3-SnO2-ZnO;InSnZnO)。In-Sn-Zn-O系半导体为In(铟)、Sn(锡)以及Zn(锌)的三元系氧化物。或者,氧化物半导体层7也可以包含In-Al-Zn-O系半导体、In-Al-Sn-Zn-O系半导体、Zn-O系半导体、In-Zn-O系半导体、Zn-Ti-O系半导体、Cd-Ge-O系半导体、Cd-Pb-O系半导体、CdO(氧化镉)、Mg-Zn-O系半导体、In-Ga-Sn-O系半导体、In-Ga-O系半导体、Zr-In-Zn-O系半导体、Hf-In-Zn-O系半导体、Al-Ga-Zn-O系半导体、Ga-Zn-O系半导体以及In-Ga-Zn-Sn-O系半导体等。
根据本发明的实施方式,能够提供具备触摸传感器用配线并且抑制了制造所需的光掩模的数量的增加的有源矩阵基板、以及具备这样的有源矩阵基板的带触摸传感器的液晶显示装置。本发明的实施方式能够适用于具备氧化物半导体TFT的有源矩阵基板。
Claims (10)
1.一种有源矩阵基板,具有多个像素区域,其特征在于,具备:
基板;
源极金属层,其设置在上述基板上,包含多个源极总线;
下部绝缘层,其覆盖上述源极金属层;
氧化物半导体TFT,其配置于上述多个像素区域中的每一个像素区域,并且具有设置在上述下部绝缘层上的氧化物半导体层、设置在上述氧化物半导体层上的栅极绝缘层、以隔着上述栅极绝缘层与上述氧化物半导体层相对的方式设置的栅极电极、以及电连接到上述氧化物半导体层的源极电极及漏极电极;
层间绝缘层,其覆盖上述氧化物半导体TFT;
像素电极,其设置在上述层间绝缘层上,电连接到上述漏极电极;
共用电极,其隔着电介质层与上述像素电极相对,并且包含分别能作为触摸传感器用的电极发挥功能的多个子共用电极;
栅极金属层,其包含多个栅极总线和上述栅极电极;
漏极金属层,其包含上述漏极电极;以及
多个触摸传感器用配线,其分别电连接到上述多个子共用电极中的任意一个子共用电极,并且包含于上述漏极金属层。
2.根据权利要求1所述的有源矩阵基板,
上述电介质层设置在上述像素电极上,
上述共用电极设置在上述电介质层上。
3.根据权利要求2所述的有源矩阵基板,
上述多个触摸传感器用配线分别在形成于上述电介质层和上述层间绝缘层的接触孔中连接到上述多个子共用电极中的对应的子共用电极。
4.根据权利要求1至3中的任意一项所述的有源矩阵基板,
还具备覆盖上述氧化物半导体层和上述栅极金属层的上部绝缘层,
上述多个触摸传感器用配线设置在上述上部绝缘层上。
5.根据权利要求1至3中的任意一项所述的有源矩阵基板,
在从上述基板的法线方向观看时,上述多个触摸传感器用配线分别与上述多个源极总线中的任意一个源极总线重叠。
6.根据权利要求1至3中的任意一项所述的有源矩阵基板,
上述氧化物半导体TFT的上述源极电极与上述多个源极总线中的任意一个源极总线形成为一体。
7.根据权利要求1至3中的任意一项所述的有源矩阵基板,
上述源极金属层包含在从上述基板的法线方向观看时与上述氧化物半导体层的沟道区域重叠的遮光层。
8.根据权利要求1至3中的任意一项所述的有源矩阵基板,
上述氧化物半导体层包含In-Ga-Zn-O系半导体。
9.根据权利要求8所述的有源矩阵基板,
上述In-Ga-Zn-O系半导体包含结晶质部分。
10.一种带触摸传感器的液晶显示装置,其特征在于,具备:
权利要求1至3中的任意一项所述的有源矩阵基板;
相对基板,其以与上述有源矩阵基板相对的方式配置;以及
液晶层,其设置在上述有源矩阵基板与上述相对基板之间。
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US20190172882A1 (en) * | 2017-12-04 | 2019-06-06 | Lg Display Co., Ltd. | Display Device Including Touch Sensors and Method of Manufacturing the Same |
CN109638079A (zh) * | 2018-11-30 | 2019-04-16 | 武汉华星光电技术有限公司 | 一种阵列基板及显示面板 |
Cited By (2)
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CN115206252A (zh) * | 2021-04-07 | 2022-10-18 | 夏普显示科技株式会社 | 配线基板和显示装置 |
CN115206252B (zh) * | 2021-04-07 | 2024-05-31 | 夏普显示科技株式会社 | 配线基板和显示装置 |
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US20200387019A1 (en) | 2020-12-10 |
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