CN112039593B - Optical module - Google Patents
Optical module Download PDFInfo
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- CN112039593B CN112039593B CN202010929310.7A CN202010929310A CN112039593B CN 112039593 B CN112039593 B CN 112039593B CN 202010929310 A CN202010929310 A CN 202010929310A CN 112039593 B CN112039593 B CN 112039593B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
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Abstract
The application discloses an optical module, which comprises a circuit board, an optical transceiving component and a demultiplexing circuit, wherein the demultiplexing circuit is arranged on the circuit board and is used for demultiplexing a three-state signal transmitted by a golden finger pin into two paths of two-state signals; the demultiplexing circuit comprises a first comparator, a second comparator, a third comparator, an exclusive-OR gate, a voltage division circuit and an inverter, wherein the first comparator outputs a first signal for controlling the optical transceiving component according to a three-state signal transmitted by the golden finger pin and a first reference voltage; the second comparator outputs a first level signal according to the tri-state signal and the second reference voltage; the voltage division circuit is connected with the output end of the exclusive-OR gate, and the third comparator outputs a second level signal according to the tri-state signal and a third reference voltage output by the voltage division circuit; the exclusive-OR gate outputs a second signal for controlling the optical transceiver module according to the first and second level signals. The application adds the demultiplexing circuit on the circuit board, and converts the three-state signal into two paths of two-state signals through the demultiplexing circuit so as to be used by corresponding functional units in the module.
Description
Technical Field
The application relates to the technical field of optical communication, in particular to an optical module.
Background
As the demand for communications increases, the demand for XGSPON modules increases rapidly. According to the requirement of the XGS-PON standard protocol, the recovery time is required to be fast enough, so that a reset circuit is required to be added in practical application to help the system to reset quickly. Meanwhile, the XGS-PON protocol requires to support a 10G and 2.5G service mixed mode, and in order to improve the transmission quality and stability of receiving uplink by an OLT (Optical Line Terminal), it is necessary to increase a rate selection function to switch a system bandwidth, and select an input signal bandwidth channel according to a rate to switch between the 10G and 2.5G modes. Reset (Reset) and rate select (Ratesel) require system vendor MAC chip provisioning.
According to the design of system schemes of different manufacturers, the system manufacturers provide two schemes of Reset and rate selection signals, wherein one scheme is to provide two independent paths of Reset and rate selection signals, and the other scheme is to provide a three-state voltage control signal multiplexed by Ratesel/Reset. The current circuit scheme at the OLT module end has two types, one is to support a tri-state voltage input circuit, and the other is not to support a tri-state voltage input and needs independent input of reset and rate selection signals. The client system provides two independent signals, and the module also supports the application of two independent signal inputs, so that the optical module can be directly input; the tri-state voltage input is provided for a client system, and the module also supports the application of the tri-state voltage input, so that the tri-state voltage input can be directly input into the optical module.
However, a client system provides a Ratesel/Reset multiplexed tri-state voltage control signal, and a module does not support application of tri-state voltage input, so that the optical module cannot directly supply the tri-state voltage control signal to a corresponding functional unit in the module, and rapid Reset and system bandwidth switching cannot be performed.
Disclosure of Invention
The application provides an optical module, which aims to solve the problem that the optical module cannot be quickly reset and switched in system bandwidth due to the fact that a client system provides tri-state voltage input and the optical module does not support the application of the tri-state voltage input.
In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:
the embodiment of the application discloses an optical module, includes:
one end of the circuit board is provided with a golden finger pin;
the optical transceiving component is connected with the circuit board and used for transmitting and receiving optical signals;
the demultiplexing circuit is arranged on the circuit board and used for demultiplexing the three-state signals transmitted by the golden finger pins into two paths of two-state signals;
wherein the demultiplexing circuit comprises:
the positive end of the first comparator is connected with the golden finger pin, the negative end of the first comparator is connected with a first reference voltage, and the first comparator is used for outputting a first signal for controlling the optical transceiver module according to the voltage of the tri-state signal and the first reference voltage;
the positive end of the second comparator is connected with the golden finger pin, and the negative end of the second comparator is connected with a second reference voltage and used for outputting a first level signal according to the voltage of the tri-state signal and the second reference voltage;
the positive end of the third comparator is connected with the golden finger pin, and the negative end of the third comparator is connected with a third reference voltage and used for outputting a second level signal according to the voltage of the tri-state signal and the third reference voltage;
an exclusive-or gate, an input end of which receives the first level signal and the second level signal respectively, and outputs a second signal for controlling the optical transceiver module according to the first level signal and the second level signal;
one end of the voltage division circuit is connected with a power supply, the other end of the voltage division circuit is connected with the output end of the exclusive-OR gate, the negative end of the third comparator is connected into the voltage division circuit, and the negative end of the third comparator is connected with the output end of the exclusive-OR gate in parallel;
the optical module that this application provided includes circuit board, light receiving and dispatching subassembly and demultiplexing circuit, and the one end of circuit board is equipped with golden finger pin, and demultiplexing circuit receives the tristate signal of golden finger transmission to demultiplex tristate signal into two way two state signals, and two way two state signals transmit to light receiving and dispatching subassembly respectively. The demultiplexing circuit comprises a first comparator, a second comparator, a third comparator, an exclusive-or gate, a voltage division circuit and an inverter, wherein the positive end of the first comparator is connected with the golden finger pin, the negative end of the first comparator is connected with a first reference voltage, and a first signal for controlling the optical transceiving component can be output according to the voltage of the tri-state signal and the first reference voltage; the positive end of the second comparator is connected with the golden finger pin, the negative end of the second comparator is connected with a second reference voltage, and a first level signal can be output according to the voltage of the tri-state signal and the second reference voltage; the positive end of the third comparator is connected with the golden finger pin, the negative end of the third comparator is connected with a third reference voltage, and a second level signal can be output according to the voltage of the tri-state signal and the third reference voltage; the input end of the exclusive-OR gate receives a first level signal and a second level signal respectively, and can output a second signal for controlling the optical transceiver module according to the first level signal and the second level signal; one end of the voltage division circuit is connected with the power supply, the other end of the voltage division circuit is connected with the output end of the exclusive-OR gate, the negative end of the third comparator is connected into the voltage division circuit, and the negative end of the third comparator is connected with the output end of the exclusive-OR gate in parallel so as to provide a third reference voltage for the negative end of the third comparator. The application aims at the application that a client system provides tri-state voltage input but a module does not support the tri-state voltage input, a demultiplexing circuit is additionally arranged on a circuit board, and a tri-state signal is converted into two independent two-state signals through the demultiplexing circuit, wherein the two-state signals can be respectively used by corresponding functional units in an optical transceiving component.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a connection relationship of an optical communication terminal;
fig. 2 is a schematic structural diagram of an optical network terminal;
fig. 3 is a schematic structural diagram of an optical module according to an embodiment of the present application;
fig. 4 is an exploded schematic view of an optical module according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a circuit board in an optical module according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a demultiplexing circuit in an optical module according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a first demultiplexing unit in an optical module according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a second demultiplexing unit in an optical module according to an embodiment of the present application;
fig. 9 is a waveform diagram of a tri-state voltage signal slew rate selection signal in an optical module according to an embodiment of the present disclosure;
fig. 10 is a waveform diagram of converting a tri-state voltage signal into a two-state signal in an optical module according to an embodiment of the present disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
One of the core links of optical fiber communication is the interconversion of optical and electrical signals. The optical fiber communication uses optical signals carrying information to transmit in information transmission equipment such as optical fibers/optical waveguides, and the information transmission with low cost and low loss can be realized by using the passive transmission characteristic of light in the optical fibers/optical waveguides; meanwhile, the information processing device such as a computer uses an electric signal, and in order to establish information connection between the information transmission device such as an optical fiber or an optical waveguide and the information processing device such as a computer, it is necessary to perform interconversion between the electric signal and the optical signal.
The optical module realizes the function of interconversion of optical signals and electrical signals in the technical field of optical fiber communication, and the interconversion of the optical signals and the electrical signals is the core function of the optical module. The optical module is electrically connected with an external upper computer through a golden finger on an internal circuit board of the optical module, and the main electrical connection comprises power supply, I2C signals, data information, grounding and the like; the electrical connection mode realized by the gold finger has become the mainstream connection mode of the optical module industry, and on the basis of the mainstream connection mode, the definition of the pin on the gold finger forms various industry protocols/specifications.
Fig. 1 is a schematic diagram of connection relationship of an optical communication terminal. As shown in fig. 1, the connection of the optical communication terminal mainly includes interconnection among the optical network terminal 100, the optical module 200, the optical fiber 101, and the network cable 103.
One end of the optical fiber 101 is connected with a far-end server, one end of the network cable 103 is connected with local information processing equipment, and the connection between the local information processing equipment and the far-end server is completed by the connection between the optical fiber 101 and the network cable 103; and the connection between the optical fiber 101 and the network cable 103 is made by the optical network terminal 100 having the optical module 200.
An optical port of the optical module 200 is externally accessed to the optical fiber 101, and establishes bidirectional optical signal connection with the optical fiber 101; an electrical port of the optical module 200 is externally connected to the optical network terminal 100, and establishes bidirectional electrical signal connection with the optical network terminal 100; the optical module realizes the mutual conversion of optical signals and electric signals, thereby realizing the establishment of information connection between the optical fiber and the optical network terminal. Specifically, the optical signal from the optical fiber is converted into an electrical signal by the optical module and then input to the optical network terminal 100, and the electrical signal from the optical network terminal 100 is converted into an optical signal by the optical module and input to the optical fiber.
The optical network terminal is provided with an optical module interface 102, which is used for accessing an optical module 200 and establishing bidirectional electric signal connection with the optical module 200; the optical network terminal is provided with a network cable interface 104, which is used for accessing the network cable 103 and establishing bidirectional electric signal connection with the network cable 103; the optical module 200 is connected to the network cable 103 via the optical network terminal 100. Specifically, the optical network terminal transmits a signal from the optical module to the network cable and transmits the signal from the network cable to the optical module, and the optical network terminal serves as an upper computer of the optical module to monitor the operation of the optical module.
At this point, a bidirectional signal transmission channel is established between the remote server and the local information processing device through the optical fiber, the optical module, the optical network terminal and the network cable.
Common information processing apparatuses include routers, switches, electronic computers, and the like; the optical network terminal is an upper computer of the optical module, provides data signals for the optical module, and receives the data signals from the optical module, and the common upper computer of the optical module also comprises an optical line terminal and the like.
Fig. 2 is a schematic diagram of an optical network terminal structure. As shown in fig. 2, the optical network terminal 100 has a circuit board 105, and a cage 106 is disposed on a surface of the circuit board 105; an electric connector is arranged in the cage 106 and used for connecting an electric port of an optical module such as a golden finger; the cage 106 is provided with a heat sink 107, and the heat sink 107 has a first boss portion such as a fin that increases a heat radiation area.
The optical module 200 is inserted into the optical network terminal 100, specifically, an electrical port of the optical module is inserted into an electrical connector inside the cage 106, and an optical port of the optical module is connected to the optical fiber 101.
The cage 106 is positioned on the circuit board, and the electrical connector on the circuit board is wrapped in the cage, so that the electrical connector is arranged in the cage; the optical module is inserted into the cage, held by the cage, and the heat generated by the optical module is conducted to the cage 106 and then diffused by the heat sink 107 on the cage.
Fig. 3 is a schematic structural diagram of an optical module according to an embodiment of the present application, and fig. 4 is an exploded schematic diagram of the optical module according to the embodiment of the present application. As shown in fig. 3 and 4, an optical module 200 provided in the embodiment of the present application includes an upper housing 201, a lower housing 202, an unlocking component 203, a circuit board 300, and an optical transceiver module 400.
The upper shell 201 is covered on the lower shell 202 to form a wrapping cavity with two openings; the outer contour of the packaging cavity generally presents a square body. Specifically, the lower housing 202 includes a main board and two side boards located at two sides of the main board and arranged perpendicular to the main board; the upper shell comprises a cover plate, and the cover plate covers two side plates of the upper shell to form a wrapping cavity; the upper shell may further include two side walls disposed at two sides of the cover plate and perpendicular to the cover plate, and the two side walls are combined with the two side plates to cover the upper shell 201 on the lower shell 202.
The two openings can be two end openings (204, 205) located at the same end of the optical module, or two openings located at different ends of the optical module; one opening is an electric port 204, and a gold finger of the circuit board extends out of the electric port 204 and is inserted into an upper computer such as an optical network terminal; the other opening is an optical port 205 for external optical fiber access to connect with the optical transceiver module 400 inside the optical module; the photoelectric devices such as the circuit board 300 and the optical transceiver module 400 are positioned in the packaging cavity.
The assembly mode of combining the upper shell and the lower shell is adopted, so that the circuit board 300, the optical transceiver module 400 and other devices can be conveniently installed in the shells, and the upper shell and the lower shell form the outermost packaging protection shell of the module; the upper shell and the lower shell are made of metal materials generally, electromagnetic shielding and heat dissipation are achieved, the shell of the optical module cannot be made into an integral component generally, and therefore when devices such as a circuit board are assembled, the positioning component, the heat dissipation component and the electromagnetic shielding component cannot be installed, and production automation is not facilitated.
The unlocking component 203 is located on the outer wall of the wrapping cavity/lower shell 202, and is used for realizing the fixed connection between the optical module and the upper computer or releasing the fixed connection between the optical module and the upper computer.
The unlocking component 203 is provided with a clamping component matched with the upper computer cage; the end of the unlocking member 203 is pulled to make the unlocking member 203 relatively move on the surface of the outer wall; the optical module is inserted into the cage of the upper computer, and the optical module is fixed in the cage of the upper computer by the clamping component of the unlocking component 203; by pulling the unlocking member 203, the engaging member of the unlocking member 203 moves along with the unlocking member, and further, the connection relationship between the engaging member and the upper computer is changed, so that the engagement relationship between the optical module and the upper computer is released, and the optical module can be drawn out from the cage of the upper computer.
The circuit board 300 is provided with circuit traces, electronic components (such as capacitors, resistors, triodes, and MOS transistors), and chips (such as an MCU, a laser driver chip, a limiting amplifier chip, a clock data recovery CDR, a power management chip, and a data processing chip DSP).
The circuit board 300 is used to provide signal circuits for signal electrical connection, which can provide signals. The circuit board 300 connects the electrical devices in the optical module together according to the circuit design through circuit wiring to realize the electrical functions of power supply, electrical signal transmission, grounding and the like.
The circuit board is generally a hard circuit board, and the hard circuit board can also realize a bearing effect due to the relatively hard material of the hard circuit board, for example, the hard circuit board can stably bear a chip; when the optical transceiver component is positioned on the circuit board, the rigid circuit board can also provide stable bearing; the hard circuit board can also be inserted into an electric connector in the upper computer cage, and specifically, a metal pin/golden finger is formed on the surface of the tail end of one side of the hard circuit board and is used for being connected with the electric connector; these are not easily implemented with flexible circuit boards.
A flexible circuit board is also used in a part of the optical module to supplement a rigid circuit board; the flexible circuit board is generally used in combination with a rigid circuit board, for example, the rigid circuit board may be connected to the optical transceiver module by using the flexible circuit board.
In the embodiment of the present application, in order to be compatible with an optical network terminal deployed on a communication network downward and perform bandwidth upgrade of an access network with low cost and smoothly, a receiving end of an optical module on an OLT needs to be compatible with two rates of 10G and 2.5G; further, in order to respectively improve the burst sensitivity of the optical module on the OLT at the two rates, it is necessary to provide the TIA of the optical transceiver module 400 with the rate selection signal Ratesel and the Reset signal Reset. At present, there are two schemes when the optical network terminal 100 provides Ratesel and Reset, one scheme is to provide two independent Reset signals Reset and rate selection signals Ratesel, Reset high represents resetting, low represents not resetting, Ratesel high represents switching to a high rate bandwidth, and low represents switching to a low rate bandwidth; and the other is to provide a three-state voltage control signal multiplexed by Ratesel/Reset, wherein Ratesel/Reset high represents that Reset is carried out and the bandwidth is not switched, Ratesel/Reset represents that Reset is not carried out, the bandwidth is switched to a low-rate bandwidth, Ratesel/Reset low represents that Reset is not carried out, and the bandwidth is switched to a high-rate bandwidth. However, the receiving end circuit of the optical module has two schemes: one to support tri-state voltage input circuits and the other to not support tri-state voltage input requires independent inputs of Ratesel and Reset.
In order to solve the problem that the optical network terminal 100 provides a tri-state voltage input and the optical module 200 does not support the tri-state voltage input, the embodiment of the present application provides an optical module, in which a demultiplexing circuit is added on a circuit board 300, and a tri-state multiplexing signal is demultiplexed into two independent two-state signals through the demultiplexing circuit, so as to be used by corresponding functional units inside the optical module.
Fig. 5 is a schematic structural diagram of a circuit board 300 in an optical module according to an embodiment of the present disclosure. As shown in fig. 5, one end of the circuit board 300 is provided with a gold finger pin 301, the circuit board 300 is provided with a demultiplexing circuit 500, and the demultiplexing circuit 500 is connected to the gold finger pin 301 to receive the tri-state signal transmitted by the gold finger pin 301 and demultiplex the tri-state signal into two paths of two-state signals; the output end of the demultiplexing circuit 500 is connected to the optical transceiver module 400, and the two paths of two-state signals output by the demultiplexing circuit 500 are respectively transmitted to the optical transceiver module 400 for the optical transceiver module 400 to use.
Specifically, the optical transceiver module 400 may be connected to the circuit board 300 through a flexible board, the flexible board may be provided with a first BOSA pin and a second BOSA pin, and an output end of the demultiplexing circuit 500 is connected to the first BOSA pin and the second BOSA pin, respectively, so as to transmit two paths of two-state signals output by the demultiplexing circuit 500 to the optical transceiver module 400 through the first BOSA pin and the second BOSA pin, respectively, for use by corresponding functional units in the optical transceiver module 400.
The tri-state signal transmitted by the gold finger pin 301 is a Ratesel/Reset multiplexing signal obtained by multiplexing a Ratesel signal and a Reset signal, and the demultiplexing circuit 500 needs to demultiplex the Ratesel/Reset multiplexing signal into two independent Ratesel signals and Reset signals. Fig. 6 is a schematic structural diagram of a demultiplexing circuit 500 in an optical module according to an embodiment of the present disclosure. As shown in fig. 6, the demultiplexing circuit 500 may include a first demultiplexing unit 501 and a second demultiplexing unit 502, where the first demultiplexing unit 501 is configured to demultiplex a received tri-state signal into a Reset signal for a Reset operation of a corresponding functional unit in the optical transceiver module 400; the second demultiplexing unit 502 is configured to demultiplex the received tri-state signal into Ratesel signals for rate selective switching by corresponding functional units in the optical transceiver module 400.
Fig. 7 is a schematic structural diagram of a first demultiplexing unit 501 in an optical module according to an embodiment of the present application. As shown in fig. 7, the first demultiplexing unit 501 includes a first comparator, a positive terminal of the first comparator is connected to the gold finger pin 301 to receive the tri-state signal transmitted by the gold finger pin 301; the negative terminal of the first comparator is connected to a first reference voltage to provide a voltage to the negative terminal of the first comparator. The first comparator may output a first signal for controlling the optical transceiver module 400 according to the voltage of the tri-state signal and the first reference voltage, where the first signal is a demultiplexed Reset signal.
Specifically, the first comparator is a voltage comparator, compares the level of the tri-state signal at the positive terminal with the first reference voltage at the negative terminal according to the working principle of the voltage comparator, and if the level of the tri-state signal is higher than the first reference voltage, the first signal output by the output terminal of the first comparator is a high-level signal; if the level of the tri-state signal is lower than the first reference voltage, the first signal output by the output end of the first comparator is a low-level signal.
The three-state signal Ratesel/Reset transmitted by the golden finger pin 301 has a high level, a middle level and a low level, the voltage range of the high level is generally 1.9-3.3V, the voltage range of the middle level is 0.9-1.9V, the voltage range of the low level is 0-0.9V, and when the Ratesel/Reset is the high level, Reset is controlled; when Ratesel/Reset is in a middle level, controlling the bandwidth to be switched to a low-rate bandwidth, and resetting the Reset; when Ratesel/Reset is low, the control bandwidth is switched to the high rate bandwidth and Reset is not Reset. That is, when the tri-state signal Ratesel/Reset is at a high level, Reset is Reset, and when the tri-state signal Ratesel/Reset is at a middle level or a low level, Reset is not Reset.
In summary, the first reference voltage may be 1.9V, when the tri-state signal Ratesel/Reset is at a high level, the level of the tri-state signal is higher than the first reference voltage, the output first signal is a high level signal, and Reset is controlled; when the three-state signal Ratesel/Reset is at a medium level, the level of the three-state signal is lower than a first reference voltage, the output first signal is a low-level signal, and the Reset is controlled not to Reset; when the three-state signal Ratesel/Reset is at a low level, the level of the three-state signal is lower than the first reference voltage, the output first signal is a low-level signal, and the Reset is controlled not to Reset.
Fig. 8 is a schematic structural diagram of a second demultiplexing unit 502 in an optical module according to an embodiment of the present application. As shown in fig. 8, the second demultiplexing unit 502 includes a second comparator, a third comparator, an exclusive or gate, a voltage divider circuit and an inverter, wherein a positive terminal of the second comparator is connected to the gold finger pin 301 to receive the tri-state signal transmitted by the gold finger pin 301; the negative terminal of the second comparator is connected to a second reference voltage to provide a voltage to the negative terminal of the second comparator. The second comparator is a voltage comparator, and the second comparator can compare the voltage of the tri-state signal with the second reference voltage according to the working principle of the voltage comparator, so as to output the first level signal.
In the embodiment of the application, when the second reference voltage is 0.9V and the tristate signal Ratesel/Reset is at a high level, the level of the tristate signal is higher than that of the second reference voltage, and the output first level signal is a high level signal; when the tristate signal Ratesel/Reset is at a medium level, the level of the tristate signal is higher than the second reference voltage, and the output first level signal is a high level signal; when the three-state signal Ratesel/Reset is at a low level, the level of the three-state signal is lower than the second reference voltage, and the output first level signal is a low level signal.
The positive end of the third comparator is connected with the gold finger pin 301 to receive the tri-state signal transmitted by the gold finger pin 301; the negative terminal of the third comparator is connected to a third reference voltage to provide a voltage to the negative terminal of the third comparator. The third comparator is a voltage comparator, and the third comparator can compare the voltage of the tri-state signal with the third reference voltage according to the working principle of the voltage comparator, so as to output a second level signal.
The input end of the exclusive-or gate is respectively connected with the output end of the second comparator and the output end of the third comparator so as to respectively receive the first level signal and the second level signal, and the exclusive-or gate can output the second signal according to the received first level signal and the second level signal. First level signal and second level signal are two state signals, and it all has high level and low level, according to exclusive or gate theory of operation, and when the state of two way input signal is the same, exclusive or gate output low level, and when the state of two way input signal is opposite, exclusive or gate output high level, can know: when the first level signal is at a high level and the second level signal is at a high level, the output second signal is a low level signal; when the first level signal is at a high level and the second level signal is at a low level, the output second signal is a high level signal; when the first level signal is at a low level and the second level signal is at a high level, the output second signal is a high level signal; when the first level signal is at a low level and the second level signal is at a low level, the output second signal is a low level signal.
The negative end of the third comparator is connected with a voltage division circuit, one end of the voltage division circuit is connected with a power supply, the other end of the voltage division circuit is connected with the output end of the exclusive-OR gate, the voltage division circuit comprises a first voltage division unit and a second voltage division unit, the positive end of the first voltage division unit is connected with the power supply, the negative end of the first voltage division unit is connected with the positive end of the second voltage division unit, and the negative end of the second voltage division unit is connected with the output end of the exclusive-OR gate; and the negative end of the third comparator is connected with the positive end of the second voltage division unit, and the negative end of the third comparator is connected with the output ends of the second voltage division unit and the exclusive-OR gate in parallel. Namely, the sum of the third reference voltage input by the negative terminal of the third comparator and the output voltage of the second voltage division unit and the output voltage of the exclusive-or gate is the same. In the embodiment of the present application, the voltage dividing unit in the voltage dividing circuit may be a resistor, and the voltage dividing function is performed through two resistors.
According to the working principle of the exclusive-or gate, the second signal output by the output end of the exclusive-or gate only has two voltage states: high level and low level, in addition, in this application embodiment, the xor gate adopts 3.3V power supply to supply power, so the high level of the second signal is 3.3V, and the low level is 0V.
In the embodiment of the present application, the first voltage dividing unit and the second voltage dividing unit are taken as the first resistor R1 and the second resistor R2 for example. The voltage dividing circuit is powered by a 5V power supply, the first resistor R1 and the second resistor R2 divide the voltage of 5V, the resistance ratio of the first resistor R1 and the second resistor R2 is adjusted, and the voltage of the first resistor R1 and the voltage of the second resistor R2 can be changed. Since the second signal output by the xor gate is 3.3V or 0V, when the second signal output by the xor gate is 3.3V, and the voltage of the second resistor R2 is added, the value of the third reference voltage which is the same as the sum of the voltage of the second resistor R2 and the level of the second signal is greater than 3.3V (for example, the third reference voltage is 4V), so that the level of the tri-state signal input by the positive terminal of the third comparator is lower than the third reference voltage no matter whether the level of the tri-state signal is high level, medium level or low level, and the second level signal output by the third comparator is low level; when the second signal output by the xor gate is 0V, the third reference voltage input by the negative terminal of the third comparator is the same as the voltage of the second resistor R2, and therefore the magnitude of the third reference voltage depends on the voltage division of the second resistor R2.
According to the working principle of the exclusive-or gate, when the second signal output by the exclusive-or gate is at a low level, the first level signal output by the second comparator and the second level signal output by the third comparator are in the same level state, namely, at a high level or at a low level, when the three-state signal Ratesel/Reset is at a high level, the first level signal output by the second comparator is a high level signal, and then the second level signal output by the third comparator is also a high level signal; when the three-state signal Ratesel/Reset is at a low level, the first level signal output by the second comparator is a low level signal, and then the second level signal output by the third comparator should also be a low level signal. Thus, 0.9V ≦ third reference voltage ≦ 1.9V, and since the second comparator is different from the third comparator, the third reference voltage may be 1.9V.
In the embodiment of the present application, the third reference voltage is related to the output level of the xor gate and the voltage dividing circuit, and has two voltage states: 1.9V and greater than 3.3V. According to the working principle of the voltage comparator and the voltage division circuit, when the three-state signal Ratesel/Reset is a medium level or low level signal, the second level signal output by the third comparator is low level no matter the output state of the exclusive-OR gate; when the tri-state signal Ratesel/Reset is a high level signal, the level state of the second level signal output by the third comparator is related to the state of the output of the exclusive or gate.
The input terminal of the inverter is connected to the output terminal of the xor gate to receive the second signal output by the xor gate, and the second signal is output after being inverted, and the output inverted signal is a third signal for controlling the optical transceiver module 400.
Fig. 9 is a diagram illustrating a voltage state change of each port of a second demultiplexing unit in an optical module according to an embodiment of the present application. As shown in fig. 9, the tri-state signal Ratesel/Reset switches back and forth between three states of low level, middle level and high level, and when the tri-state signal Ratesel/Reset switches, the level state output by the second comparator, the level state output by the third comparator, the level state output by the xor gate and the level state output by the inverter change with the tri-state signal Ratesel/Reset, and specific changes can be seen in table 1.
TABLE 1 level relationship of tri-state signal Ratesel/Reset, second comparator, third comparator, XOR gate, inverter
In this embodiment of the application, the demultiplexed third signal output by the second demultiplexing unit 502 may be a rate selection signal, and when the third signal is at a high level, the control bandwidth is switched to a low-rate bandwidth (2.5G); when the third signal is low, the control bandwidth is switched to the high-rate bandwidth (10G).
Fig. 10 is a waveform diagram of converting a tri-state signal into a bi-state signal in an optical module according to an embodiment of the present disclosure. As shown in fig. 10, when the tri-state signal Ratesel/Reset is at a high level, the first signal Reset output by demultiplexing is at a high level, the Reset is controlled, and the third signal Ratesel output by demultiplexing has a high level and a low level, and at this time, the control bandwidth rate is not changed; when Ratesel/Reset is at a middle level, the first signal Reset output by demultiplexing is at a low level, the Reset is controlled not to be Reset, the third signal Ratesel output by demultiplexing is at a low level, and the bandwidth is controlled to be switched to a low-rate bandwidth; when Ratesel/Reset is in low level, the first signal Reset output by demultiplexing is in low level, the Reset is controlled not to Reset, the third signal Ratesel output by demultiplexing is in high level, and the bandwidth is controlled to be switched to high-rate bandwidth.
The application aims at the application that a client system provides three-state voltage input but a module does not support the three-state voltage input, a demultiplexing circuit is additionally arranged on a circuit board, a three-state signal Ratesel/Reset is demultiplexed into two independent speed selection signals Ratesel and Reset signals Reset through the demultiplexing circuit, the two independent speed selection signals Ratesel and Reset signals Reset can be respectively used by corresponding functional units in the module, and discharging Reset and speed switching operation of an optical module is achieved.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a circuit structure, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such circuit structure, article, or apparatus. Without further limitation, the presence of an element identified by the phrase "comprising an … …" does not exclude the presence of other like elements in a circuit structure, article or device comprising the element.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
The above-described embodiments of the present application do not limit the scope of the present application.
Claims (10)
1. A light module, comprising:
one end of the circuit board is provided with a golden finger pin;
the optical transceiving component is connected with the circuit board and used for transmitting and receiving optical signals;
the demultiplexing circuit is arranged on the circuit board and used for demultiplexing the three-state signals transmitted by the golden finger pins into two paths of two-state signals; the three-state signal is a multiplexing signal obtained by multiplexing a rate selection signal and a reset signal, and the two-state signal is an independent rate selection signal and an independent reset signal;
wherein the demultiplexing circuit comprises:
the positive end of the first comparator is connected with the golden finger pin, the negative end of the first comparator is connected with a first reference voltage, and the first comparator is used for outputting a first signal for controlling the optical transceiver module according to the voltage of the tri-state signal and the first reference voltage;
the positive end of the second comparator is connected with the golden finger pin, and the negative end of the second comparator is connected with a second reference voltage and used for outputting a first level signal according to the voltage of the tri-state signal and the second reference voltage;
the positive end of the third comparator is connected with the golden finger pin, and the negative end of the third comparator is connected with a third reference voltage and used for outputting a second level signal according to the voltage of the tri-state signal and the third reference voltage;
an exclusive-or gate, an input end of which receives the first level signal and the second level signal respectively, and outputs a second signal for controlling the optical transceiver module according to the first level signal and the second level signal;
and one end of the voltage division circuit is connected with a power supply, the other end of the voltage division circuit is connected with the output end of the exclusive-OR gate, and the negative end of the third comparator is connected with the output end of the exclusive-OR gate in parallel through part of the voltage division circuit.
2. The optical module of claim 1, wherein the demultiplexing circuit further comprises an inverter, an input end of which is connected to the output end of the exclusive or gate, and configured to invert the second signal output by the exclusive or gate and output a third signal for controlling the optical transceiver module.
3. The optical module according to claim 1, wherein when the tri-state signal input to the positive terminal of the first comparator is at a high level, the level of the tri-state signal is higher than the first reference voltage, and the output first signal is a high-level signal;
when the tri-state signal input by the positive terminal of the first comparator is at a medium level or a low level, the level of the tri-state signal is lower than the first reference voltage, and the output first signal is a low-level signal.
4. The light module of claim 1, wherein the second reference voltage is less than the third reference voltage.
5. The optical module according to claim 1, wherein when the tri-state signal input to the positive terminal of the second comparator is at a high level or a middle level, the level of the tri-state signal is higher than the second reference voltage, and the output first level signal is at a high level;
when the tri-state signal input by the positive terminal of the second comparator is at a low level, the level of the tri-state signal is lower than the second reference voltage, and the output first level signal is at a low level.
6. The optical module according to claim 5, wherein the voltage divider circuit comprises a first voltage divider unit and a second voltage divider unit, one end of the first voltage divider unit is connected to the power supply, one end of the second voltage divider unit is connected to the other end of the first voltage divider unit, the other end of the second voltage divider unit is connected to the output end of the exclusive or gate in series, and the output ends of the second voltage divider unit and the exclusive or gate are connected to the negative end of the third comparator in parallel.
7. The optical module according to claim 6, wherein the level of the first level signal is the same as that of the second level signal, and the second signal output from the exclusive or gate is at a low level; when the first level signal and the second level signal are different in level, the exclusive-or gate outputs the second signal as high level.
8. The optical module according to claim 7, wherein when the tri-state signal input to the positive terminal of the third comparator is at a middle level or a low level, the level of the tri-state signal is lower than the third reference voltage, and the output second level signal is at a low level;
when the tri-state signal input by the positive terminal of the third comparator is at a high level and the second signal is at a low level, the second level signal output by the third comparator is at a high level; when the tri-state signal input by the positive terminal of the third comparator is at a high level and the second signal is at a high level, the second level signal output by the third comparator is at a low level.
9. The optical module according to claim 3, wherein when the level of the tri-state signal is high, the first signal controls the optical transceiver module to discharge and reset; and when the level of the tri-state signal is a medium level or a low level, the first signal controls the optical transceiver component to discharge without resetting.
10. The optical module of claim 2, wherein when the level of the tri-state signal is a middle level, the third signal controls the bandwidth to be switched to a low-rate bandwidth; and when the level of the tri-state signal is low level, the third signal controls the bandwidth to be switched to high-rate bandwidth.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931971A (en) * | 2012-11-07 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Three-state control signal input/output (IO) circuit |
| CN103118251A (en) * | 2012-05-08 | 2013-05-22 | 友达光电股份有限公司 | Multi-level data transmission method and system |
| JP2014103725A (en) * | 2012-11-19 | 2014-06-05 | Fuji Electric Co Ltd | Three-level power conversion device and control method thereof |
| US9350529B1 (en) * | 2015-03-23 | 2016-05-24 | Realtek Semiconductor Corp. | Method and apparatus for detecting logical signal |
| CN206287838U (en) * | 2016-11-14 | 2017-06-30 | 深圳市沃特玛电池有限公司 | A kind of protection circuit |
| CN107251430A (en) * | 2015-03-06 | 2017-10-13 | 密克罗奇普技术公司 | Three input comparators |
| CN108736977A (en) * | 2018-03-29 | 2018-11-02 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module |
| CN110198190A (en) * | 2019-06-20 | 2019-09-03 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN111556384A (en) * | 2020-04-24 | 2020-08-18 | 东莞铭普光磁股份有限公司 | Optical module receiving circuit and optical module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880685B (en) * | 2018-05-09 | 2021-06-04 | 青岛海信宽带多媒体技术有限公司 | Optical module |
-
2020
- 2020-09-07 CN CN202010929310.7A patent/CN112039593B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103118251A (en) * | 2012-05-08 | 2013-05-22 | 友达光电股份有限公司 | Multi-level data transmission method and system |
| CN102931971A (en) * | 2012-11-07 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Three-state control signal input/output (IO) circuit |
| JP2014103725A (en) * | 2012-11-19 | 2014-06-05 | Fuji Electric Co Ltd | Three-level power conversion device and control method thereof |
| CN107251430A (en) * | 2015-03-06 | 2017-10-13 | 密克罗奇普技术公司 | Three input comparators |
| US9350529B1 (en) * | 2015-03-23 | 2016-05-24 | Realtek Semiconductor Corp. | Method and apparatus for detecting logical signal |
| CN206287838U (en) * | 2016-11-14 | 2017-06-30 | 深圳市沃特玛电池有限公司 | A kind of protection circuit |
| CN108736977A (en) * | 2018-03-29 | 2018-11-02 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module |
| CN110198190A (en) * | 2019-06-20 | 2019-09-03 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN111556384A (en) * | 2020-04-24 | 2020-08-18 | 东莞铭普光磁股份有限公司 | Optical module receiving circuit and optical module |
Non-Patent Citations (1)
| Title |
|---|
| 三电平DC/DC电源转换技术研究;李瑞生等;《电力***保护与控制》;20170601;第73-80页 * |
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