CN111999704B - Vehicle-mounted radar time sequence generation system and method based on VPX bus - Google Patents
Vehicle-mounted radar time sequence generation system and method based on VPX bus Download PDFInfo
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
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- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
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Abstract
The invention discloses a vehicle-mounted radar time sequence generation system and method based on a VPX bus, which belong to the technical field of radar data processing and comprise a time system and inertial navigation data input processing module, a servo azimuth input processing module, a VPX bus interface processing module, a time sequence generation module, a time sequence dynamic monitoring module and a time sequence output module, wherein the VPX bus interface processing module is respectively connected with the time system and inertial navigation data input processing module, the servo azimuth input processing module, the time sequence generation module and an upper computer, the time sequence dynamic monitoring module is respectively connected with the VPX bus interface processing module and the time sequence generation module, and the time sequence output module is connected with the time sequence generation module. The method has the characteristics of universal time sequence generation method, stable and reliable time sequence signals, flexible and various time sequence output interfaces and the like, can be applied to the development of multi-type vehicle-mounted radar, and effectively improves the development efficiency and reliability of the whole radar.
Description
Technical Field
The invention relates to the technical field of radar data processing, in particular to a vehicle-mounted radar time sequence generation system and method based on a VPX bus.
Background
In phased array radar, each subsystem of the radar such as a transmitting subsystem, a receiving subsystem, a signal processing subsystem and the like needs to work together orderly under the unified time sequence signal beat, so that the target detection task of the radar is completed together, and the stability and the reliability of the time sequence signal are vital to the stability of the detection capability of the whole radar. The generation mechanism and the generation method of the timing signal of the radar complete machine determine the quality of the timing signal to a great extent.
In order to meet the requirements of continuously increasing detection distance and continuously improving detection precision, the requirements of modern phased array radars on the processing capability of a signal processing platform architecture and a data processing platform architecture are also continuously improved. Conventional CPCI bus-based platform architectures have failed to meet the increasing demands for processing power, and in vehicle-mounted phased array radars, the radar needs to work on the fly, so that information such as time, position, attitude, and antenna orientation of the radar itself must be acquired in real time.
The conventional vehicle-mounted radar time sequence generation system has certain defects when in use, such as frequent and trivial reading operation, easy read-write conflict generation and unreliable transmission stability. Therefore, a vehicle radar time sequence generation system and a vehicle radar time sequence generation method based on a VPX bus are provided.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: how to solve the problems of frequent reading operation and the like in the using process of the conventional vehicle-mounted radar timing sequence generating system, and provides a vehicle-mounted radar timing sequence generating system based on a VPX bus.
The invention solves the technical problems through the following technical scheme that the invention comprises a timing system and inertial navigation data input processing module, a servo azimuth input processing module, a VPX bus interface processing module, a time sequence generating module, a time sequence dynamic monitoring module and a time sequence output module;
the time system and inertial navigation data input processing module is used for sampling, converting and storing the input time system and inertial navigation data; the servo azimuth input processing module is used for filtering, high-speed sampling, multiple detection processing and storage of input servo azimuth data; the VPX bus interface processing module is used for receiving time sequence control parameters sent by the upper computer and sorting high-speed VPX bus data into parameters required by time sequence generation meeting requirements; simultaneously uploading the processed time system data, inertial navigation data and radar servo azimuth data in real time; the time sequence generation module is used for generating a complete radar time sequence signal in real time according to the time sequence control parameters input by the VPX bus interface module; the time sequence output module is used for outputting time sequence signals through single-ended, differential or high-speed optical fiber interfaces; the time sequence dynamic monitoring module is used for dynamically monitoring the time sequence signals;
the VPX bus interface processing module is respectively connected with the timing system and inertial navigation data input processing module, the servo azimuth input processing module, the time sequence generating module and the upper computer, the time sequence dynamic monitoring module is respectively connected with the VPX bus interface processing module and the time sequence generating module, and the time sequence output module is connected with the time sequence generating module.
Furthermore, the time system and inertial navigation data input processing module comprises a time system data processing channel, the time system data processing channel comprises a first signal filtering module, a period detecting module and a reference counting processing module, the first signal filtering module, the period detecting module and the reference counting processing module are sequentially connected, the first signal filtering module is used for carrying out digital filtering processing on time system signals, the period detecting module is used for detecting whether the time system signal period is correct, and the reference counting processing module is used for counting and controlling a radar complete machine 20M clock by taking the time system signal as a time reference after confirming that the time system signal period is correct, generating step counting time data and storing the step counting time data.
Still further, the time system and inertial navigation data input processing module further comprises an inertial navigation data processing channel, wherein the inertial navigation data processing channel comprises a serial-parallel conversion module and a header detection module, the table tennis buffer control module is connected with the header detection module in sequence, the serial-parallel conversion module is used for carrying out serial-parallel conversion on the inertial navigation data, the header detection module is used for carrying out header detection on the converted inertial navigation data, and the table tennis buffer control is used for storing the inertial navigation data in a table tennis buffer mode after the header detection accords with the header detection.
Still further, the servo azimuth input processing module includes a second signal filtering module, a high-speed sampling module, a serial clock number counting module, a serial clock period counting module, and a decision processing module, where the second signal filtering module, the high-speed sampling module, the serial clock number counting module, the serial clock period counting module, and the decision processing module are sequentially connected, the second signal filtering module is used for filtering azimuth signals, the high-speed sampling module is used for performing multiple high-speed sampling on each serial azimuth signal, and determining whether data is valid according to multiple sampling values, the serial clock number counting module is used for counting the number of each serial clock, the serial clock period counting module is used for counting the total period of each serial clock, and the decision processing module is used for determining whether the serial clock of each serial clock is lack or exceeds the phenomenon of the agreed number, and is used for determining whether the serial clock is the agreed number.
Furthermore, the timing system data processing channel and the inertial navigation data processing channel are arranged in parallel, and the timing data output by the timing system data processing channel, the inertial navigation data output by the inertial navigation data processing channel and the azimuth data output by the servo azimuth input processing module are packaged together through the VPX bus interface processing module and uploaded to an upper computer.
Furthermore, the VPX bus interface processing module comprises a data packaging processing module and a data receiving processing module, wherein the data packaging processing module is connected with the upper computer through a transmitting port, and the data receiving processing module is connected with the upper computer through a receiving port.
Still further, the time sequence generation module comprises a parameter comparison module, a parameter analysis module, a control parameter processing module, a classification buffer memory module and a pulse counting RAM read control module, wherein the parameter comparison module, the parameter analysis module, the classification buffer memory module and the pulse counting RAM read control module are sequentially connected, the parameter comparison module is connected with the VPX bus interface processing module, the control parameter processing module is respectively connected with the parameter analysis module and the pulse counting RAM read control module, and the pulse counting RAM read control module is connected with the time sequence dynamic monitoring module.
Further, the working process of the parameter comparison module is as follows:
s11: after detecting the handshake signal of the upper computer, reading out the whole set of time sequence control parameters from the parameter buffer area, and putting the time sequence control parameters into a register group A for registering;
s12: after the first time of reading, reading out the whole set of time sequence control parameters from the parameter buffer area again, and putting the time sequence control parameters into a register group B for registering;
s13: and comparing the parameters in the register group A and the register group B one by one, and outputting the parameters in the register group B to the parameter analysis module after all the parameters are the same.
Furthermore, the classifying and buffering module comprises a plurality of data blocks, the plurality of parameters analyzed by the parameter analyzing module are classified and buffered in the plurality of data blocks, and the pulse count RAM reading control module respectively reads corresponding parameters from the data blocks under the control of the control parameter processing module.
Still further, the time sequence dynamic monitoring module comprises a leading pulse period and number monitoring module, a wave bit pulse period and number monitoring module, a frequency conversion pulse period and number monitoring module and a monitoring judgment module, wherein the leading pulse period and number monitoring module, the wave bit pulse period and number monitoring module and the frequency conversion pulse period and number monitoring module are respectively connected with the monitoring judgment module.
Still further, the time sequence output module comprises a time sequence output total control module, a first output module, a second output module and a third output module, wherein the time sequence output total control module is respectively connected with the first output module, the second output module, the third output module, the time sequence generation module and the monitoring judgment module.
The invention also provides a vehicle-mounted radar time sequence generation method based on the VPX bus, which comprises the following steps:
s1: sampling and serial-parallel converting the input time system and inertial navigation data through a high-frequency clock, and storing the generated time information and inertial navigation data dynamics; the high-frequency synchronous clock is utilized to complete the effective receiving processing and storage of the servo input azimuth data;
s2: the time information, inertial navigation data and azimuth data in the step S1 are arranged into a data packet which accords with the standard of the VPX bus;
s3: the VPX bus interface module is used for completing real-time issuing of time sequence control parameters and real-time uploading of time information, inertial navigation data and azimuth data;
s4: the time sequence logic generating module reads time sequence control parameters from the parameter buffer area in real time, and generates various corresponding time sequence signals according to the parameters and the radar working mode;
s5: outputting the time sequence signals in various modes through a time sequence output module; meanwhile, the time sequence dynamic monitoring module is utilized to dynamically sample the generated time sequence signals and report the sampling result in real time.
Compared with the prior art, the invention has the following advantages: according to the vehicle-mounted radar time sequence generation system and method based on the VPX bus, based on the VPX bus technology, externally input low-speed time system data, inertial navigation data and servo azimuth data are unified and arranged into frame format data conforming to the VPX bus standard, and then the frame format data is actively and regularly uploaded to a PowerPC computer, so that frequent and trivial reading operation of the PowerPC computer is effectively avoided; the transmission mechanism of the time sequence control parameters of the handshake is adopted, so that cache read-write conflict can be effectively avoided, and the transmission stability is improved; the design method of parameter multiple reading and comparison can reduce the error probability of time sequence control parameters in the transmission and reading processes; by adopting a time sequence design mode with definable parameters, each period of the leading pulse can be changed, and time sequence signals meeting different application occasions can be generated; the accurate receiving of azimuth signals can be effectively ensured by carrying out multiple high-frequency sampling processing and multiple detection processing on the externally input servo azimuth, and the interference of error data is avoided; the quality of the time sequence signal can be monitored in real time through the set time sequence dynamic monitoring module, and the time sequence signal quality can be reported in real time.
Drawings
FIG. 1 is a schematic block diagram of a vehicle radar timing generation system in accordance with a second embodiment of the present invention;
FIG. 2 is a schematic diagram of the operation of the timing and inertial navigation data input processing module in the second embodiment of the present invention;
FIG. 3 is a schematic diagram of a servo azimuth input processing module in a second embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the operation of a VPX bus interface processing module according to a second embodiment of the present invention;
FIG. 5 is a schematic diagram of a timing generation module according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a timing dynamic monitoring module according to a second embodiment of the present invention;
fig. 7 is a schematic diagram of the operation of the timing output module in the second embodiment of the present invention.
Detailed Description
The following describes in detail the examples of the present invention, which are implemented on the premise of the technical solution of the present invention, and detailed embodiments and specific operation procedures are given, but the scope of protection of the present invention is not limited to the following examples.
Example 1
The embodiment provides a technical scheme: a vehicle-mounted radar time sequence generating system based on a VPX bus comprises a time system and inertial navigation data input processing module, a servo azimuth input processing module, a VPX bus interface processing module, a time sequence logic generating module, a time sequence dynamic monitoring module, a time sequence output module and the like.
The embodiment also provides a vehicle-mounted radar time sequence generation method based on the system, which comprises the following steps:
the first step: sampling and serial-parallel converting the input time system and inertial navigation data through a high-frequency clock, and dynamically storing the generated time information and inertial navigation data into a opened double-port RAM cache in the FPGA;
and a second step of: the high-frequency synchronous clock is utilized to complete the effective receiving processing of the servo input azimuth, and azimuth data is also stored in the double-port RAM cache;
and a third step of: the time information, the inertial navigation data and the azimuth data are arranged into a data packet which accords with the standard of the VPX bus;
fourth step: the VPX bus interface module is used for completing real-time issuing of time sequence control parameters and real-time uploading of the time information, inertial navigation data and azimuth data, and a transmission mode based on handshake is adopted in the design, so that cache read-write conflict can be effectively avoided, and reliable transmission is realized;
fifth step: the time sequence logic generating module reads time sequence control parameters from the dual-port RAM cache in real time, generates various corresponding time sequence signals according to the parameters and the radar working mode, and adopts a design method that the parameters are read and judged for multiple times so as to read for the last time effectively in order to ensure the continuity and the reliability of time sequence;
sixth step: the time sequence signal is effectively and reliably output through a time sequence output module in various modes;
seventh step: the time sequence dynamic monitoring module dynamically samples the generated time sequence signals and reports the sampling result in real time so as to discover abnormality in time.
The time system and inertial navigation data input processing module, the servo azimuth input processing module, the VPX bus interface processing module, the time sequence logic generating module, the time sequence dynamic monitoring module and the time sequence output module in the vehicle-mounted radar time sequence generating system based on the VPX bus are all designed and realized in an FPGA.
The specific process of the second step is as follows:
firstly, carrying out filtering treatment on an externally input azimuth signal, and primarily filtering possible narrow burr signals; carrying out 10 times of high-speed sampling on each serial azimuth data, if the 10 times of sampling results are the same value, judging that the azimuth data are valid, and carrying out subsequent processing; counting the number of each group of serial clocks, and judging whether the serial clocks are the agreed number or not; and finally, counting the total period of each group of serial clocks, and judging whether the serial clocks of each group have the phenomenon of missing or being more than the appointed number of clocks. Through the specific steps, the effective and accurate receiving of the azimuth data can be ensured.
The fifth step comprises the following specific processes:
after the PowerPC computer sends out the time sequence control parameter writing-out mark, the time sequence generation module starts to read out the whole set of time sequence control parameters from the parameter buffer area and put the whole set of time sequence control parameters into the register group A for registering, and after the first reading-out, the whole set of time sequence control parameters are read out from the parameter buffer area and put the whole set of time sequence control parameters into the register group B for registering; and (3) carrying out one-by-one comparison on the parameters in the register group A and the register group B, and outputting the parameters in the register group B for time sequence generation after all the parameters are identical in comparison.
The time sequence generating module utilizes the radar complete machine reference clock to programmably generate radar time sequence signals such as wave position, leading and variable frequency triggering according to the predefined information such as working mode, pulse period, pulse number and the like in the parameter packet.
Example two
As shown in fig. 1, this embodiment provides a technical solution: a vehicle radar time sequence generating system based on VPX bus can be applied to a radar signal processing or data processing platform based on VPX bus architecture to generate radar complete machine time sequence, and each module of the system is designed and realized in an FPGA, and the system comprises a time system and inertial navigation data input processing module, a servo azimuth input processing module, a VPX bus interface processing module, a time sequence generating module, a time sequence dynamic monitoring module, a time sequence output module and the like;
the timing system and inertial navigation data input processing module and the servo azimuth input processing module can send accurate time information, real-time attitude information of a radar and real-time azimuth data of a radar antenna to a PowerPC computer through a VPX bus, and are used for realizing real-time scheduling and time sequence generation control of wave beams; the VPX bus interface processing module is mainly used for receiving time sequence control parameters sent by the PowerPC computer through the VPX bus, sorting high-speed VPX bus data into parameters required by time sequence generation meeting requirements, and uploading processed time system data, inertial navigation data and radar servo azimuth data in real time through the VPX bus; the time sequence generating module, the time sequence output module and the time sequence dynamic monitoring module generate the time sequence of the whole radar in real time according to the parameter information input by the VPX bus interface module, and can output the time sequence through single-ended, differential or high-speed optical fiber interfaces, and dynamically monitor time sequence signals.
In operation, the vehicle-mounted phased array radar needs to acquire information such as time, position, attitude and antenna azimuth in real time. As shown in fig. 2, the time reference signal PPS pulses from the time system device, after entering the FPGA, needs to perform digital filtering processing on the signal first; then, the PPS second pulse signal is subjected to period detection, whether the period of the monitoring signal is fixed to be 1 second or not is monitored, and if the period is found to be wrong, the alarm is timely given; after the PPS second pulse is judged to be normal, the clock of the whole machine 20M is counted and controlled as a time reference, time data of 0.05us step count is generated, and the time data enters a dual-port RAM for buffering. As shown in fig. 2, after inertial navigation data enter PFGA, conventional serial-parallel conversion is performed first, and after the character head is detected to be matched, ping pong is written into two pieces of dual-port RAM for buffering.
The flow of acquiring the servo azimuth data by the vehicle-mounted radar is shown in fig. 3, and equipment for generating the servo azimuth data is always in a strong electromagnetic interference environment, so that burrs are generated in signal transmission. Therefore, the signals also need to be filtered after the azimuth signals enter the FPGA; then, using a high-frequency clock of 100MHz in the FPGA to perform 10 times of high-speed sampling on each serial azimuth signal data, and if the 10 times of sampling result is the same value, judging that the bit data is valid, and performing subsequent processing; counting the number of each group of serial clocks, and judging whether the serial clocks are the agreed number or not; and simultaneously counting the total period of each group of serial clocks, and judging whether the serial clocks of each group have the phenomenon of missing or being more than the appointed number of clocks. Through multiple detection processing, effective and accurate reception of azimuth signal data can be ensured.
The time, inertial navigation data acquired in fig. 2 and azimuth data acquired in fig. 3, most of the conventional radar design, through different computer port addresses, multiple discrete and separate readings, result in lower processing efficiency of the PowerPC computer. In the invention, the 3 kinds of data are uniformly packed and processed by means of the VPX bus, and after being arranged into frame format data conforming to the VPX bus standard, the frame format data is actively and regularly uploaded to the PowerPC computer by the VPX bus interface processing module of the FPGA, and the periodical interval software of the regular uploading is controllable, thereby effectively avoiding frequent and trivial reading operation of the PowerPC computer.
As shown in fig. 4, the time, inertial navigation and azimuth data entering the FPGA are uploaded through the VPX bus interface module, a timing sending circuit is designed in the FPGA, the time system, inertial navigation and azimuth data in the dual-port RAM cache are read at fixed time, and the timing period is comprehensively determined according to the change period of the various data; after the data is read, the operations such as frame header addition, data rearrangement and the like are carried out through the data packaging processing module, and uploading operation is realized through the sending port of the SRIO IP core instantiated in the FPGA. The time sequence control parameters from the PowerPC computer enter the data receiving and processing module through the receiving port of the SRIO IP core, and after the processing of address matching, data length detection and the like is completed, the parameters are put into the dual-port RAM for caching.
As shown in fig. 5, the master clock adopted by the timing sequence generating module is a 10M clock generated after 20M clock frequency division of the radar complete machine reference. The time sequence generation module immediately starts to read time sequence control parameters cached in the dual-port RAM after detecting handshake signals of the PowerPC computer, registers data after reading the first cached data, re-reads the data once again from the dual-port RAM, compares the data blocks read twice one by one, and checks whether a data reading error occurs or not, wherein the data read twice is consistent under normal conditions. After the data comparison is correct, parameter analysis operation is carried out, control parameters such as radar working mode and the like, wave position parameters, leading parameters and variable frequency triggering parameters for time sequence pulse counting are separated from time sequence control parameter data packets, the wave position parameters, the leading parameters and the variable frequency triggering parameters are respectively written into three different double-port RAMs with smaller capacities (corresponding to the wave position parameters, the leading parameters and the variable frequency triggering RAMs in the figure 5 respectively) (for buffering, a pulse counting RAM reading control module respectively advances the information such as the number and the period of counting pulses required by reading the wave position from the wave position parameters, the leading parameters and the variable frequency triggering parameters before each wave position starts, and then under the control of a control parameter processing module, the control module utilizes 10M clock counting to generate preset pulse signals.
As shown in fig. 6, the timing dynamic monitoring module is also an important component of the system. The method mainly completes real-time monitoring of wave position signals, leading signals and variable frequency pulse signals. Taking a leading pulse period and number monitoring module as an example, the module mainly completes the detection of each leading pulse period and the detection of the leading pulse number in each wave bit period, judges whether the pulse period and the leading pulse number are consistent with the preset period and number, if so, the time sequence generating circuit works normally, otherwise, alarm processing is adopted, and a PowerPC computer is informed to resend the time sequence control parameters of the current wave bit, and the detection is carried out again until the operation is normal. The three detection results adopt a decision strategy that the whole error is reported if only one pulse goes wrong. The time sequence signal generated by the system is detected in real time through the module, so that the accuracy of time sequence generation of the invention is ensured.
As shown in fig. 7, the timing output module is the last link of the system. The time sequence signal generated by the time sequence generating module is not directly output, but is output after being controlled according to the monitoring result of the time sequence dynamic monitoring module. After the detection meets the requirements, single-ended time sequence signals, such as TTL output, are output after TTL output control; differential timing signals, such as RS422 level timing signals, are output after differential output control; the method comprises the steps that after a time sequence signal sent by an optical fiber is subjected to high-frequency sampling, a time sequence frame parameter packet with fixed data number and starting of a contracted frame head is generated on the rising edge of each time sequence pulse, and after clock domain conversion, the self-contained exemplified GTH module of an FPGA is utilized to realize the optical fiber sending of the radar time sequence signal.
In summary, the vehicle-mounted radar time sequence generating system and method based on the VPX bus in the embodiments above, based on the VPX bus technology, unifies the externally input low-speed time system data, inertial navigation data and servo azimuth data into frame format data conforming to the VPX bus standard, and then actively uploads the frame format data to the PowerPC computer at regular time, thereby effectively avoiding frequent and trivial reading operations of the PowerPC computer; the transmission mechanism of the time sequence control parameters of the handshake is adopted, so that cache read-write conflict can be effectively avoided, and the transmission stability is improved; the design method of parameter multiple reading and comparison can reduce the error probability of time sequence control parameters in the transmission and reading processes; by adopting a time sequence design mode with definable parameters, each period of the leading pulse can be changed, and time sequence signals meeting different application occasions can be generated; the accurate receiving of azimuth signals can be effectively ensured by carrying out multiple high-frequency sampling processing and multiple detection processing on the externally input servo azimuth, and the interference of error data is avoided; the quality of the time sequence signal can be monitored in real time through the set time sequence dynamic monitoring module, and the time sequence signal quality can be reported in real time.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (10)
1. A vehicle-mounted radar time sequence generation system based on a VPX bus is characterized in that: the system comprises a timing system and inertial navigation data input processing module, a servo azimuth input processing module, a VPX bus interface processing module, a time sequence generating module, a time sequence dynamic monitoring module and a time sequence output module;
the time system and inertial navigation data input processing module is used for sampling, converting and storing the input time system and inertial navigation data; the servo azimuth input processing module is used for filtering, high-speed sampling, multiple detection processing and storage of input servo azimuth data; the VPX bus interface processing module is used for receiving the time sequence control parameters and sorting the high-speed VPX bus data into parameters required by time sequence generation meeting the requirements; simultaneously uploading the processed time system data, inertial navigation data and radar servo azimuth data in real time; the time sequence generation module is used for generating a complete radar time sequence signal in real time according to the time sequence control parameters input by the VPX bus interface module; the time sequence output module is used for outputting time sequence signals outwards; the time sequence dynamic monitoring module is used for dynamically monitoring the time sequence signals;
the VPX bus interface processing module is respectively connected with the timing system and inertial navigation data input processing module, the servo azimuth input processing module, the time sequence generating module and the upper computer, the time sequence dynamic monitoring module is respectively connected with the VPX bus interface processing module and the time sequence generating module, and the time sequence output module is connected with the time sequence generating module.
2. The VPX bus-based vehicle radar timing generation system according to claim 1, wherein: the time system and inertial navigation data input processing module comprises a time system data processing channel, wherein the time system data processing channel comprises a first signal filtering module, a period detection module and a reference counting processing module, and the first signal filtering module, the period detection module and the reference counting processing module are sequentially connected.
3. The VPX bus-based vehicle radar timing generation system according to claim 2, wherein: the time system and inertial navigation data input processing module further comprises an inertial navigation data processing channel, wherein the inertial navigation data processing channel comprises a serial-parallel conversion module and a character head detection module, and the serial-parallel conversion module and the character head detection module are sequentially connected.
4. A VPX bus-based vehicle radar timing generation system according to claim 3, wherein: the servo azimuth input processing module comprises a second signal filtering module, a high-speed sampling module, a serial clock number counting module, a serial clock period counting module and a judging processing module, wherein the second signal filtering module, the high-speed sampling module, the serial clock number counting module, the serial clock period counting module and the judging processing module are sequentially connected, the serial clock number counting module is used for counting the number of each group of serial clocks, the serial clock period counting module is used for counting the total period of each group of serial clocks, and the judging processing module is used for judging whether the phenomenon that whether the serial clocks of each group lack or exceed the number of the appointed clocks or not and judging whether the serial clocks are the appointed numbers or not.
5. The VPX bus-based vehicle radar timing generation system according to claim 4, wherein: the time data processing channel and the inertial navigation data processing channel are arranged in parallel, and the time data output by the time data processing channel, the inertial navigation data output by the inertial navigation data processing channel and the azimuth data output by the servo azimuth input processing module are packaged and uploaded to an upper computer through the VPX bus interface processing module.
6. The VPX bus-based vehicle radar timing generation system according to claim 5, wherein: the VPX bus interface processing module comprises a data packaging processing module and a data receiving processing module, wherein the data packaging processing module is connected with the upper computer through a sending port, and the data receiving processing module is connected with the upper computer through a receiving port.
7. The VPX bus-based vehicle radar timing generation system according to claim 6, wherein: the time sequence generation module comprises a parameter comparison module, a parameter analysis module, a control parameter processing module, a classification buffer memory module and a pulse counting RAM read control module, wherein the parameter comparison module, the parameter analysis module, the classification buffer memory module and the pulse counting RAM read control module are sequentially connected, the parameter comparison module is connected with the VPX bus interface processing module, the control parameter processing module is respectively connected with the parameter analysis module and the pulse counting RAM read control module, and the pulse counting RAM read control module is connected with the time sequence dynamic monitoring module.
8. The VPX bus-based vehicle radar timing generation system according to claim 7, wherein: the working process of the parameter comparison module is as follows:
s11: after detecting the handshake signal of the upper computer, reading out the whole set of time sequence control parameters from the parameter buffer area, and putting the time sequence control parameters into a register group A for registering;
s12: after the first time of reading, reading out the whole set of time sequence control parameters from the parameter buffer area again, and putting the time sequence control parameters into a register group B for registering;
s13: and comparing the parameters in the register group A and the register group B one by one, and outputting the parameters in the register group B to the parameter analysis module after all the parameters are the same.
9. The VPX bus-based vehicle radar timing generation system according to claim 8, wherein: the classifying and caching module comprises a plurality of data blocks, a plurality of parameters analyzed by the parameter analyzing module are classified and cached in the data blocks, and under the control of the control parameter processing module, the pulse counting RAM reading control module reads corresponding parameters from the data blocks respectively.
10. A vehicle radar timing generation method based on a VPX bus, characterized by outputting a vehicle radar timing signal using the vehicle radar timing generation system according to any one of claims 1 to 9, comprising the steps of:
s1: sampling and serial-parallel converting the input time system and inertial navigation data through a high-frequency clock, and storing the generated time information and inertial navigation data dynamics; the high-frequency synchronous clock is utilized to complete the effective receiving processing and storage of the servo input azimuth data;
s2: the time information, inertial navigation data and azimuth data in the step S1 are arranged into a data packet which accords with the standard of the VPX bus;
s3: the VPX bus interface module is used for completing real-time issuing of time sequence control parameters and real-time uploading of time information, inertial navigation data and azimuth data;
s4: the time sequence logic generating module reads time sequence control parameters from the parameter buffer area in real time, and generates various corresponding time sequence signals according to the parameters and the radar working mode;
s5: outputting the time sequence signals in various modes through a time sequence output module; meanwhile, the time sequence dynamic monitoring module is utilized to dynamically sample the generated time sequence signals and report the sampling result in real time.
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