CN111965215A - Packaged chip defect detection device and method thereof - Google Patents
Packaged chip defect detection device and method thereof Download PDFInfo
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- CN111965215A CN111965215A CN202010814149.9A CN202010814149A CN111965215A CN 111965215 A CN111965215 A CN 111965215A CN 202010814149 A CN202010814149 A CN 202010814149A CN 111965215 A CN111965215 A CN 111965215A
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
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Abstract
A packaged chip defect detection method comprises the following steps: providing a detection circuit board for arranging the packaged chip; respectively applying a functional operation signal and a power supply signal which enable the packaged chip to execute a detection program to the packaged chip through a first interface and a second interface on the detection circuit board; and carrying out thermal image temperature sensing on the packaged chip to obtain a thermal imaging image, and judging whether the packaged chip has defects or not according to the thermal imaging image.
Description
Technical Field
The invention relates to the field of packaging, in particular to a packaged chip defect detection device and a method thereof.
Background
The semiconductor packaging technology is to cut, bond and wire the prepared wafer, and then cover the wafer with packaging material to form a packaged chip, so as to protect the circuit from the external environment. In order to detect a poorly performing packaged chip, it is generally necessary to slice the packaged chip and observe it by an electron microscope or the like to know the defect type of the abnormal packaged chip, but such a method is time-consuming and resource-consuming. Therefore, it is desirable to provide a packaged chip defect detecting apparatus and a method thereof to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a packaged chip defect detection device and a method thereof.
In order to achieve the above object, a first aspect of the present invention provides a packaged chip defect detection method, including the following steps:
providing a detection circuit board for arranging the packaged chip;
respectively applying a functional operation signal and a power supply signal which enable the packaged chip to execute detection to the packaged chip through a first interface and a second interface on the detection circuit board; and
and carrying out thermal image temperature sensing on the packaged chip to obtain a thermal imaging graph, and judging whether the packaged chip has defects according to the thermal imaging graph.
Further, the packaged chip is a Field Programmable Gate Array (FPGA) packaged chip.
Further, the package chip is any one of a Ball Grid Array (BGA) package chip, a Chip Size Package (CSP) package chip, and a Flip Chip (FC) package chip.
Furthermore, the detection circuit board further comprises a pin device (socket), one end of the pin device is connected with the first interface, and the other end of the pin device is connected with a pin on the packaged chip, so that the pin on the packaged chip receives the power supply signal.
Further, the photon wavelength for generating the thermal imaging graph is 350nm to 1100 nm.
Further, the detection procedure includes a leakage current detection procedure for detecting leakage current in the packaged chip.
Further, the functional operation signal is provided through firmware, and the firmware is a detection platform designed based on a programming language.
Further, the programming language is Python.
Further, the packaged chips comprise a defect-free packaged chip and a packaged chip to be tested, and the thermal imaging images of the defect-free packaged chip and the packaged chip to be tested are respectively obtained by the method so as to position the defect position.
Further, in the step of performing thermal image temperature sensing on the packaged chip to obtain the thermal imaging map, a thermal imaging generator is utilized to acquire the thermal imaging map, and a power line of the thermal imaging generator also provides VCCQ voltage to pins of the packaged chip.
The invention provides a packaged chip defect detection device, which is characterized by comprising a detection circuit board, wherein the packaged chip is arranged in the detection circuit board; and
a thermal imaging generator for performing thermal image temperature sensing on the packaged chip to obtain a thermal imaging map;
and respectively applying a functional operation signal and a power supply signal which enable the packaged chip to execute detection to the packaged chip through a first interface and a second interface on the detection circuit board so as to obtain the thermal imaging diagram while the packaged chip is in functional operation, and judging whether the packaged chip has defects according to the thermal imaging diagram.
Further, the packaged chip is a Field Programmable Gate Array (FPGA) packaged chip.
Further, the package chip is any one of a Ball Grid Array (BGA) package chip, a Chip Size Package (CSP) package chip, and a Flip Chip (FC) package chip.
Furthermore, the detection circuit board further comprises a pin device (socket), one end of the pin device is connected with the first interface, and the other end of the pin device is connected with a pin on the packaged chip, so that the pin on the packaged chip receives the power supply signal.
Further, the photon wavelength for generating the thermal imaging graph is 350nm to 1100 nm.
Further, the detection procedure includes a leakage current detection procedure for detecting leakage current in the packaged chip.
Further, the functional operation signal is provided through firmware, and the firmware is a detection platform designed based on a programming language.
Further, the programming language is Python.
Furthermore, the packaged chip comprises a defect-free packaged chip and a packaged chip to be tested, and the thermal imaging generator is used for respectively obtaining thermal imaging images of the defect-free packaged chip and the packaged chip to be tested so as to position the defect position.
Further, the power supply line of the thermal imaging generator also supplies VCCQ voltage to the pins of the packaged chip.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic diagram of a packaged chip defect detecting apparatus according to a first embodiment of the invention.
Fig. 2 is a flowchart of a method for detecting defects of a packaged chip according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a packaged chip defect detecting apparatus according to a second embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the particular embodiments described herein are illustrative only, and that the word "embodiment" as used in the description of the invention is intended to serve as an example, instance, or illustration, and is not intended to limit the invention.
Fig. 1 is a schematic diagram of a packaged chip defect detection apparatus according to a first embodiment of the invention. The packaged chip defect detecting apparatus includes a detection circuit board 20 and a thermal imaging generator 30, wherein the packaged chip 10 is disposed in the detection circuit board 20, and the thermal imaging generator 30 is configured to perform thermal image temperature sensing on the packaged chip 10 to obtain a thermal imaging image.
In this embodiment, the detection circuit board 20 further includes a pin (socket)21, a first interface 22, and a second interface 23, one end of the pin 21 is connected to the first interface 22 and the second interface 23, and the other end is connected to the pin 11 on the packaged chip 10 (the packaged chip 10 is disposed in the pin 21). One end of the first interface 22 is connected to a firmware (firmware)40, and one end of the second interface 23 is connected to a power supply 50. The firmware 40 causes the packaged chip 10 to perform detection by applying a functional operation signal to the first interface 22, and the power supply 50 causes the packaged chip 10 to form a thermal imaging map by applying a power signal (e.g., VCCQ voltage) to the second interface 23. For simplicity of illustration and description, the thick lines in fig. 1 are connecting lines, and specific connecting holes are not shown here, but this does not affect the inventive focus of the present invention, and therefore, this should not be construed as limiting the present invention. In a modification (not shown), the power signal may be provided by the detection circuit board 20.
Further, the package chip is a Field Programmable Gate Array (FPGA) package chip, and the package chip is any one of a Ball Grid Array (BGA) package chip, a Chip Size Package (CSP) package chip, and a Flip Chip (FC) package chip.
Further, the functional operation signal is provided through a firmware 40, and the firmware 40 is a test platform designed based on a programming language (e.g., Python) for controlling the signal timing or strength of the functional operation signal. It is understood that the firmware 40 may provide various functional operation signals (e.g., a leakage current functional operation signal for detecting leakage current to execute a leakage current detection program (program) and cooperate with a leakage current detection circuit in the packaged chip 10) to detect various defects of the packaged chip 10. In this embodiment, the firmware 40 may be disposed in the detection circuit board 20.
Referring to fig. 1 and fig. 2, fig. 2 is a flowchart of a method for detecting defects of a packaged chip according to an embodiment of the present invention, where the method includes the following steps:
step S10: a detection circuit board 20 is provided on which the packaged chip 10 is disposed.
Step S20: a functional operation signal and a power supply signal for enabling the packaged chip 10 to perform detection are respectively applied to the packaged chip 10 through the first interface 22 and the second interface 23 on the detection circuit board 20.
Step S30: and sensing the thermal image temperature of the packaged chip 10 to obtain the thermal imaging graph, and judging whether the packaged chip has defects according to the thermal imaging graph.
In this step, in order to detect these photons, the thermal image is obtained by capturing the photons with a dedicated camera 31 (e.g., a CCD camera) connected to the thermal image generator 30.
In this step, since the abnormal packaged chip usually has a temperature rise (i.e. a large number of photons are generated) due to the abnormality of local power consumption, if an abnormal hot spot (hotspot) appears on the thermal imaging graph, it indicates that the packaged chip is an abnormal packaged chip. Further, by using the optical emission microscopy analysis technique, the packaged chip 10 generates a large number of hot carriers (including electrons and holes) at abnormal positions under the excitation of the power signal, and the hot carriers transition within an energy band or between different energy bands to emit photons, so that the thermal imaging image can be obtained through the thermal imaging generator 30. The wavelength of the generated photons may fall in the range of visible to infrared light (e.g., in the range of 350nm to 1100 nm).
Further, the packaged chip 10 includes a defect-free packaged chip and a packaged chip to be tested, and the defect position can be located by respectively obtaining the thermal imaging maps of the defect-free packaged chip and the packaged chip to be tested by the method and comparing the difference between the two thermal imaging maps (i.e. whether an abnormal hot spot occurs).
In this step, if the packaged chip is an abnormal packaged chip, and after the position where the abnormality occurs is located according to the hot spot of the thermal imaging map, the packaged chip may be sliced by means of Physical Failure Analysis (PFA) (e.g., an electron microscope) to find out the cause of the abnormality.
In the prior art, when the leads are spherical (i.e., solder balls), in order to detect a bad-performing packaged chip, the solder balls on the bad-performing packaged chip may be first ground flat, and then a probe card (probe card) is used to apply a voltage or a current to the ground solder balls for probing detection, and the applied voltage or current may also cause the bad-performing packaged chip to generate a large number of hot carriers, thereby forming a thermal imaging diagram on a thermal imaging generator. According to the invention, the technical problem can be solved, the defect detection can be completed without any pretreatment on the packaged chip, and the trial and error cost is reduced.
Fig. 3 is a schematic diagram of a packaged chip defect detecting apparatus according to a second embodiment of the invention. The second embodiment of the present invention is different from the first embodiment of the present invention in that one end of the second interface 23 is connected to a power line of the thermal imaging generator 30, and the thermal imaging generator 30 also supplies the power signal (e.g., VCCQ voltage) to the pins of the packaged chip 10.
It is understood that the description details in fig. 1 to 3 may be combined with each other, and are not repeated herein.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (20)
1. A packaged chip defect detection method is characterized by comprising the following steps:
providing a detection circuit board for arranging the packaged chip;
respectively applying a functional operation signal and a power supply signal which enable the packaged chip to execute detection to the packaged chip through a first interface and a second interface on the detection circuit board; and
and carrying out thermal image temperature sensing on the packaged chip to obtain a thermal imaging graph, and judging whether the packaged chip has defects according to the thermal imaging graph.
2. The method of claim 1, wherein: the packaging chip is a Field Programmable Gate Array (FPGA) packaging chip.
3. The method of claim 1, wherein: the package chip is any one of a Ball Grid Array (BGA) package chip, a Chip Size Package (CSP) package chip, and a Flip Chip (FC) package chip.
4. The method of claim 1, wherein: the detection circuit board further comprises a pin device (socket), one end of the pin device is connected with the first interface, and the other end of the pin device is connected with a pin on the packaging chip, so that the pin on the packaging chip receives the power supply signal.
5. The method of claim 1, wherein: the photon wavelength for generating the thermal imaging map is 350nm to 1100 nm.
6. The method of claim 1, wherein: the detection program includes a leakage current detection program for detecting leakage current in the packaged chip.
7. The method of claim 1, wherein: the functional operation signal is provided through firmware, and the firmware is a detection platform designed based on a programming language.
8. The method of claim 1, wherein: the programming language is Python.
9. The method of claim 1, wherein: the packaging chips comprise a defect-free packaging chip and a packaging chip to be tested, and the thermal imaging images of the defect-free packaging chip and the packaging chip to be tested are respectively obtained by the method to be used for positioning the defect position.
10. The method of claim 1, wherein: in the step of performing thermal image temperature sensing on the packaged chip to obtain the thermal imaging map, a thermal imaging generator is utilized to acquire the thermal imaging map, and a power line of the thermal imaging generator also provides VCCQ voltage to pins of the packaged chip.
11. A packaged chip defect detection device is characterized by comprising
The detection circuit board is provided with the packaging chip; and
a thermal imaging generator for performing thermal image temperature sensing on the packaged chip to obtain a thermal imaging map;
and respectively applying a functional operation signal and a power supply signal which enable the packaged chip to execute detection to the packaged chip through a first interface and a second interface on the detection circuit board so as to obtain the thermal imaging diagram while the packaged chip is in functional operation, and judging whether the packaged chip has defects according to the thermal imaging diagram.
12. The packaged chip defect detection apparatus of claim 1, wherein: the packaging chip is a Field Programmable Gate Array (FPGA) packaging chip.
13. The packaged chip defect detection apparatus of claim 1, wherein: the package chip is any one of a Ball Grid Array (BGA) package chip, a Chip Size Package (CSP) package chip, and a Flip Chip (FC) package chip.
14. The packaged chip defect detection apparatus of claim 1, wherein: the detection circuit board further comprises a pin device (socket), one end of the pin device is connected with the first interface, and the other end of the pin device is connected with a pin on the packaging chip, so that the pin on the packaging chip receives the power supply signal.
15. The packaged chip defect detection apparatus of claim 1, wherein: the photon wavelength for generating the thermal imaging map is 350nm to 1100 nm.
16. The packaged chip defect detection apparatus of claim 1, wherein: the detection program includes a leakage current detection program for detecting leakage current in the packaged chip.
17. The packaged chip defect detection apparatus of claim 1, wherein: the functional operation signal is provided through firmware, and the firmware is a detection platform designed based on a programming language.
18. The packaged chip defect detection apparatus of claim 1, wherein: the programming language is Python.
19. The packaged chip defect detection apparatus of claim 1, wherein: the packaging chip comprises a defect-free packaging chip and a packaging chip to be tested, and thermal imaging pictures of the defect-free packaging chip and the packaging chip to be tested are respectively obtained through the thermal imaging generator so as to position a defect position.
20. The packaged chip defect detection apparatus of claim 1, wherein: the power supply line of the thermal imaging generator also provides VCCQ voltage to the pins of the packaged chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010814149.9A CN111965215A (en) | 2020-08-13 | 2020-08-13 | Packaged chip defect detection device and method thereof |
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| CN202010814149.9A CN111965215A (en) | 2020-08-13 | 2020-08-13 | Packaged chip defect detection device and method thereof |
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