CN111952308A - 具有辅助栅的闪存存储器及其制作方法 - Google Patents

具有辅助栅的闪存存储器及其制作方法 Download PDF

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CN111952308A
CN111952308A CN201910444569.XA CN201910444569A CN111952308A CN 111952308 A CN111952308 A CN 111952308A CN 201910444569 A CN201910444569 A CN 201910444569A CN 111952308 A CN111952308 A CN 111952308A
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floating gates
gate
flash memory
substrate
auxiliary gate
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许汉杰
许正源
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Powerchip Technology Corp
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Abstract

本发明公开一种具有辅助栅的闪存存储器及其制作方法，该具有辅助栅的闪存存储器具有两个浮动栅设置在基底上、一绝缘层形成在该两个浮动栅以及该基底上、一辅助栅设置在该两个浮动栅之间，其中该辅助栅有部分包覆住该两个浮动栅、以及两个选择栅，分别设置在该两个浮动栅外侧且有部分与该浮动栅重叠。

Description

具有辅助栅的闪存存储器及其制作方法
技术领域
本发明涉及一种闪存存储器，更具体言之，其涉及一种具有辅助栅的闪存存储器结构，可降低闪存存储器所需的工作电压。
背景技术
闪存存储器(flash memory)问世至今已有30余年，有别于挥发性存储器如动态随机存取存储器(DRAM)或是静态随机存取存储器(SRAM)，闪存存储器是一种非挥发性存储器，其应用层面极为广泛，特别是在消费性电子产品方面，包括个人计算机、行动通讯产品、数字相机等，都需要具有体积小、容量大、低耗电、可修改等特性的存储装置，闪存存储器无疑符合上述所有要求。
一般闪存存储器写入资料(program)的原理是利用热电子注入(hot electroninjection)或是源极侧注入(source side injection)等方式来将电子写进存储单元的浮动栅极中，浮动栅极就像是位能阱一样将电子存储于其中；而抹除资料(数据)通常则是利用反向的FN隧穿效应来达成。上述写入或抹除状态会决定浮动栅中电子的多寡，进而影响浮动栅下方的通道电场，故根据所读出的电流大小就可以判定出该存储单元的资料态。
在闪存存储器的运作中，浮动栅的耦合率(coupling ratio)会影响到闪存存储器的读取/写入速度，其与浮动栅和源极之间的重叠面积有关，重叠面积越大，耦合率越好，存储单元所需的工作电压也可降低。然而，随着制作工艺技术的进步，现今浮动栅的尺寸不断地微缩，已经来到了纳米尺度的级别。虽然浮动栅的单元尺寸持续的缩小，但是写入与抹除动作所需的电压并没有按比例地缩小。在先进一代的制作工艺中，这样的负担越来越大，特别是对于嵌入式的非挥发性存储器应用，其周边电路相关的高压晶体管制作变得越来越困难和昂贵，而如果采用加大浮动栅的尺寸来增加耦合率的作法，其无疑又增加了存储单元的尺寸，违背电子元件尺寸微缩的发展前提。
发明内容
有鉴于现有技术中的闪存存储器需要高工作电压且尺寸不易微缩，本发明特此提出了一种新颖的闪存存储器结构，其具备一额外的辅助栅来分担所需的工作电压，进而能够缩小存储器单元的尺寸。
本发明的其一面向在于一种具有辅助栅的闪存存储器，包含一基底、两个浮动栅，设置在该基底上、一绝缘层，共形地形成在该两个浮动栅以及该基底上、一辅助栅，设置在该两个浮动栅之间的该绝缘层上，其中该辅助栅有部分包覆住该两个浮动栅、以及两个选择栅，分别设置在该两个浮动栅外侧的该绝缘层上，其中该选择栅有部分与该浮动栅重叠。
本发明的另一面向在于一种制作具有辅助栅的闪存存储器的方法，包含提供一基底，该基底上依序具有一隧穿氧化层与一第一多晶硅层、进行一第一蚀刻制作工艺蚀刻该多晶硅层以及该隧穿氧化层，以形成两个浮动栅、在该两个浮动栅以及该基底上形成一共形的绝缘层、在该绝缘层上形成一第二多晶硅层、以及进行一第二蚀刻制作工艺蚀刻该第二多晶硅层，以形成一辅助栅与两个选择栅，其中该辅助栅形成在该两个浮动栅之间的该绝缘层上，且该辅助栅有部分包覆住该两个浮动栅，该两个选择栅分别形成在该两个浮动栅外侧的该绝缘层上，且该选择栅有部分与该浮动栅重叠。
本发明的这类目的与其他目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后必然可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1为本发明优选实施例一示例性的闪存存储器截面示意图；以及
图2～图9为本发明优选实施例图1所示闪存存储器的制作流程的截面示意图。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
符号说明
1 闪存存储器
100 基底
102 浮动栅
102a 多晶硅层
102c 表面
104 隧穿氧化层
104a 氧化层
106 源极
108 绝缘层
110 辅助栅
112 选择栅
114 漏极
116 尖端部位
118 氮化硅层
118a 开口
120 牺牲氧化层
122 多晶硅层
124 光致抗蚀剂
BL 位线
OC 工作电压控制电路
SLC 来源线电压控制电路
WLC 字符线电压控制电路
具体实施方式
现在下文将详细说明本发明的示例性实施例，其会参照附图示出所描述的特征以便阅者理解并实现技术效果。阅者将可理解文中的描述仅通过例示的方式来进行，而非意欲要限制本案。本案的各种实施例和实施例中彼此不冲突的各种特征可以以各种方式来加以组合或重新设置。在不脱离本发明的精神与范畴的情况下，对本案的修改、等同物或改进对于本领域技术人员来说是可以理解的，并且旨在包含在本案的范围内。
阅者应能容易理解，本案中的「在…上」、「在…之上」和「在…上方」的含义应当以广义的方式被解读，以使得「在…上」不仅表示「直接在」某物「上」而且还包括在某物「上」且其间有居间特征或层的含义，并且「在…之上」或「在…上方」不仅表示「在」某物「之上」或「上方」的含义，而且还可以包括其「在」某物「之上」或「上方」且其间没有居间特征或层(即，直接在某物上)的含义。
此外，诸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空间相关术语在本文中为了描述方便可以用于描述一个元件或特征与另一个或多个元件或特征的关系，如在附图中示出的。
如本文中使用的，术语「基底」是指向其上增加后续材料的材料。可以对基底自身进行图案化。增加在基底的顶部上的材料可以被图案化或可以保持不被图案化。此外，基底可以包括广泛的半导体材料，例如硅、锗、砷化镓、磷化铟等。或者，基底可以由诸如玻璃、塑胶或蓝宝石晶片的非导电材料制成。
如本文中使用的，术语「层」是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构的厚度的均质或非均质连续结构的区域。例如，层可以位于在连续结构的顶表面和底表面之间或在顶表面和底表面处的任何水平面对之间。层可以水准、竖直和/或沿倾斜表面延伸。基底可以是层，其中可以包括一个或多个层，和/或可以在其上、其上方和/或其下方具有一个或多个层。层可以包括多个层。例如，互连层可以包括一个或多个导体和接触层(其中形成触点、互连线和/或通孔)和一个或多个介电层。
此外，下述的方法与结构是着重在单一存储器单元的形成与特征，在实际制作中，会同时有一整个阵列的这些存储器单元被形成在基底的存储单元区中。较佳来说，这些存储器单元会形成在成栏的主动(有源)区域中，其由绝缘区域所分隔，这些主动区域与绝缘区域的形成都是现有技术。
[存储器结构]
现在请参照图1，其为根据本发明优选实施例一示例性的闪存存储器截面示意图。闪存存储器1可以建构在一半导体基底100中的存储单元(cell)区的主动区域上。例如，半导体基底100可为一P型硅基底，其上具有多个由浅沟槽隔离结构(shallow trenchisolation,STI)或是场氧化结构(field oxide)所界定出来的主动区域，闪存存储器1则形成在这些主动区域上。然而，应了解其他的半导体基底如硅覆绝缘层基底(silicon-on-insulator,SOI)或是外延基底也可应用在本发明中。
每个闪存存储器1都包含两个浮动栅102成对地设置在基底100上，呈现出镜像单元组架构。两个浮动栅102之间彼此相隔一段距离，以提供用来设置辅助栅的空间，其与基底100之间形成有隧穿氧化层(tunnel oxide)104将浮动栅102与基底100彼此电性隔绝。浮动栅102可以多晶硅材料制成，隧穿氧化层104则可为氧化硅层。两个浮动栅102之间的基底100中形成有一源极106，源极106有部分区域会与两个浮动栅102重叠，以提供浮动栅102较佳的耦合率(coupling ratio)。
一绝缘层108共形地形成在两个浮动栅102以及基底100上。一辅助栅110设置在两个浮动栅102之间的绝缘层108上，其通过绝缘层108而与两个浮动栅102电性隔绝。需注意在本实施例中，有部分的辅助栅110会嵌入两个浮动栅102之间的空间中，且有部分的辅助栅110会与两个浮动栅102重叠，使得辅助栅110会包覆住所邻接部分的该两个浮动栅102，如此可通过辅助栅110进一步增进浮动栅102的耦合率。
两个选择栅112分别设置在两个浮动栅102外侧的绝缘层108上，其中部分的选择栅112会与浮动栅102重叠，以提供电子抹除路径。两个漏极114分别形成在两个选择栅112外侧的基底100中。辅助栅110与选择栅112都可以多晶硅材料形成，且由于在同一道制作工艺中形成的缘故，其顶面可能齐高。绝缘层108则可为氧化硅层，与隧穿氧化层104同样具有隧穿特性。须注意在本实施例中，浮动栅102的外侧角落会以特殊制作工艺形成具有向上突起的尖端部位116。此尖端部位116会与选择栅112重叠，其可促进闪存存储器的抹除运作。
前述实施例为本发明闪存存储器1的基本结构，其各部位还会进一步电连接到其他的外部结构来达成读取/写入/抹除等运作。复参照图1，在本实施例中，闪存存储器1的源极106即为一来源线(source line)，其会电连接到一来源线电压控制电路SLC，以控制来源线的电压。闪存存储器1的辅助栅110会电连接到一工作电压控制电路OC，以控制辅助栅110的电压。在本实施例中，闪存存储器1的选择栅112即为字符线(word line)，每列存储器单元的选择栅112共同作为单一的字符线，其会电连接到一字符线电压控制电路WLC，以控制选择栅112的电压。闪存存储器1的漏极114会电连接到一位线(bit line)BL，其可能设置在整个闪存存储器1的上方，而每条位线BL还会进一步连接到一位线电压控制电路(未示出)，以控制位线BL以及其所连接的漏极114的电压。
[运作方式]
在存储器的写入资料(program)运作中，当想要所选的存储器单元被执行写入，其漏极114会被施加0伏，选择栅112会被施加一正压，其接近选择栅112所界定的MOS结构的临界电压，约为3.3伏。而源极106与辅助栅110都会被施加一正压，约为6伏。从漏极114生成的电子会因为源极106与辅助栅110的正压从漏极114经由选择栅112下方的通道流向源极106。当电子来到浮动栅102下方的区域时，由于浮动栅102与带有较高正压的源极106以及辅助栅110具有较强的电容耦合，电子会被加速且会穿过隧穿氧化层104而被注入浮动栅102中，如此电子就被存储在所选择的存储器单元中，如图1中的路径①，此即源极测注入或热电子注入原理。在此运作中，源极106与辅助栅110可分担写入浮动栅102所需的高正压，故所需施加的正压仅需现有技术的一半即可，约为6伏。如此，存储器对于周边高压电路的需求就没有那么严格，存储单元的尺寸也可进一步的缩小。
在存储器的读取运作中，源极106与辅助栅110会被接地，漏极114会被施加一读取电压，约为1伏，而选择栅112会被施加装置的供压(Vcc)。在这样的情况下，如果浮动栅102是带正电的(即没有电子存储在浮动栅102中)，那浮动栅102下方的通道会被开路，选择栅112下方的通道也会因为供压的关系被开路，使得电子从源极106流到漏极114，如此存储器会被测为“1”的资料态。另一方面，如果浮动栅102是带负电的，那浮动栅102下方的通道会闭路，没有电子会从源极106流到漏极114，如此存储器会被测为“0”的资料态。
最后，在存储器的抹除运作中，源极106与漏极114都会被接地，选择栅112会被施加一正压，约为6伏。较特别的是，辅助栅110会被施加一负压，约为-5伏。选择栅112的正压以及辅助栅110的负压会促使浮动栅102中的电子因为反向FN隧穿机制而穿过浮动栅102与选择栅112之间的绝缘层，如图1中的路径②，使得浮动栅102中的电子被清空而带正电。该处尖锐的浮动栅102尖端部位116可以增强此反向FN隧穿机制，使得抹除的速度更快。值得注意的是，辅助栅110在此运作中也如同写入运作起到了分担电压的效果，有别于现有技术仅通过选择栅或额外设置的抹除栅来施加高正压(如10-12伏)抹除电子，本案的辅助栅110在另一侧提供了一半的负压推力，使得选择栅112一侧只要约一半的正压(即6伏)即可达成FN隧穿，如此可以降低周边高压电路的需求并可进一步缩小存储单元尺寸。
[制作方法]
现在请依序参照图2～图9，其绘示出根据本发明优选实施例图1所示的闪存存储器1的制作流程的截面示意图。首先请参照图2，提供一基底100，如P型硅基底或是其他的半导体基底如硅覆绝缘层基底或是外延基底，其上可具有多个由浅沟槽隔离结构或是场氧化结构所界定出来的主动区域。由于上述的主动区域与隔离结构的制作并非本发明的重点，此处将省略其制作流程，图中所示的基底一律为存储单元区中的主动区域。一氧化层104a，如氧化硅，形成在基底100上。氧化层104a可使用氧化或沉积(如化学气相沉积，CVD)等现有技术形成在基底100上。一多晶硅层102a形成在氧化层104a的顶面上。多晶硅层102a可使用低压化学气相沉积(LPCVD)等现有技术沉积在氧化层104a上。一氮化硅层118形成在多晶硅层102a的顶面上，其较佳使用CVD方式形成。在实施例中，氮化硅层118是用来界定浮动栅的，其上会使用光刻技术形成开口118a而裸露出下方的多晶硅层102a。
接下来请参照图3。进行一热氧化制作工艺，使得从开口118a裸露出的多晶硅层102a氧化成为牺牲氧化层120。此热氧化步骤所形成的牺牲氧化层120会具有透镜形状的外型，其周围接近氮化硅层118的部位会渐缩并稍微延伸到氮化硅层118的下方。因为牺牲氧化层120的形成，剩余的多晶硅层102a会具有倾斜的表面102c。
接下来请参照图4。进行一选择性蚀刻步骤移除氮化硅层118以及前述制作工艺中形成的牺牲氧化层120，裸露出下方的多晶硅层102a。如此，多晶硅层102a会具有一从两侧向下凹的表面102c，即使得多晶硅层102a形成相对突出的部位。
接下来请参照图5。使用光致抗蚀剂进行一各向异性蚀刻制作工艺来界定出浮动栅102。此各向异性蚀刻步骤会移除前述多晶硅层102a的下凹表面102c以外的部分以及下凹表面102c中间的部分，如此即能形成如图5所示镜像成对、外侧具有尖锐的尖端部位116的浮动栅102。需注意此步骤同时也会移除多晶硅层102a下方部分的氧化层104a，形成浮动栅102与基底100之间的隧穿氧化层104。
接下来请参照图6。进行一离子注入制作工艺在两个浮动栅102之间的基底100中形成源极106(即来源线)，期间可搭配热扩散制作工艺使得掺杂的源极106扩散延伸至浮动栅102，使得部分的源极106会与两个浮动栅102重叠，以达到电容耦合。之后，在两个浮动栅102与基底100的表面上形成一层共形的绝缘层108。绝缘层108可使用热氧化以及/或高温氧化沉积等制作工艺来形成。
接下来请参照图7。在绝缘层108形成另一厚的多晶硅层122，其可使用低压化学气相沉积方式形成，并在多晶硅层122上形成光致抗蚀剂124，其中光致抗蚀剂124会具有预定的辅助栅图案与选择栅图案，其裸露出部分的多晶硅层122。
接下来请参照图8。以光致抗蚀剂124为掩模进行一各向异性蚀刻制作工艺移除裸露的多晶硅层122，如此即形成了如图8所示的辅助栅110以及选择栅112。可以看到辅助栅110形成在两个浮动栅102之间，其通过绝缘层108与两个浮动栅102电性隔绝。有部分的辅助栅110嵌入两个浮动栅102之间的空间中，且有部分的辅助栅110会与两个浮动栅102重叠，使得辅助栅110会包覆住所邻接部分的两个浮动栅102，如此可通过辅助栅110进一步增进浮动栅102的耦合率。两个选择栅112则分别设置在两个浮动栅102外侧的绝缘层108上，其中部分的选择栅112会与浮动栅102重叠，以提供电子抹除路径。由于在同一道制作工艺中形成的缘故，辅助栅110与选择栅112的顶面可能齐高。光致抗蚀剂124在辅助栅110与选择栅112形成后可以加以移除。
最后请参照图9。在形成选择栅112之后，进行另一离子注入制作工艺在两个选择栅112外侧的基底100中形成漏极114，如此即完成了本发明闪存存储器1的基本结构。之后，还可进行如接触结构以及金属导线等互连结构的制作，来将源极106、漏极114、辅助栅110以及选择栅112连接到所需的电压控制电路如位线BL、字符线电压控制电路WLC、来源线电压控制电路SLC、工作电压控制电路OC等，如此即完成了闪存存储器1的制作。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种具有辅助栅的闪存存储器，其特征在于，包含：
基底；
两个浮动栅，设置在该基底上；
绝缘层，共形地形成在该两个浮动栅以及该基底上；
辅助栅，设置在该两个浮动栅之间的该绝缘层上，其中该辅助栅有部分包覆住该两个浮动栅；
两个选择栅，分别设置在该两个浮动栅外侧的该绝缘层上，其中该选择栅有部分与该浮动栅重叠。
2.如权利要求1所述的具有辅助栅的闪存存储器，还包含：
源极，形成在该两个浮动栅之间的该基底中，其中该源极有部分与该两个浮动栅重叠；以及
两个漏极，分别形成在该两个选择栅的外侧该基底中。
3.如权利要求2所述的具有辅助栅的闪存存储器，其中该源极为来源线，该漏极连接到位线，该选择栅为字符线，该辅助栅连接到工作电压控制电路。
4.如权利要求3所述的具有辅助栅的闪存存储器，其中在该闪存存储器的写入运作中，该辅助栅连接到该工作电压控制电路所提供的正压，而在该闪存存储器的抹除运作中，该辅助栅连接到该工作电压控制电路所提供的负压。
5.如权利要求1所述的具有辅助栅的闪存存储器，还包含隧穿氧化层，形成在该两个浮动栅与该基底之间。
6.如权利要求1所述的具有辅助栅的闪存存储器，其中该浮动栅与该选择栅重叠部分的角落具有向上突起的尖端部位。
7.如权利要求1所述的具有辅助栅的闪存存储器，其中该辅助栅与该两个选择栅是由同一多晶硅层构成并且两者的顶面齐高。
8.如权利要求1所述的具有辅助栅的闪存存储器，其中该浮动栅、该辅助栅以及该选择栅的材料都为多晶硅。
9.一种制作具有辅助栅的闪存存储器的方法，包含：
提供基底，该基底上依序具有隧穿氧化层与第一多晶硅层；
进行第一蚀刻制作工艺蚀刻该多晶硅层以及该隧穿氧化层，形成两个浮动栅；
在该两个浮动栅以及该基底上形成一共形的绝缘层；
在该绝缘层上形成第二多晶硅层；以及
进行第二蚀刻制作工艺蚀刻该第二多晶硅层，以形成一辅助栅与两个选择栅，其中该辅助栅形成在该两个浮动栅之间的该绝缘层上，且该辅助栅有部分包覆住该两个浮动栅，该两个选择栅分别形成在该两个浮动栅外侧的该绝缘层上，且该选择栅有部分与该浮动栅重叠。
10.如权利要求9所述的制作具有辅助栅的闪存存储器的方法，其中形成该两个浮动栅的步骤还包含：
在该第一多晶硅层上形成氮化硅层，其中该氮化硅层具有开口裸露出该第一多晶硅层；
进行热氧化制作工艺，使从该开口裸露出的该第一多晶硅层氧化成牺牲氧化层；以及
进行选择性蚀刻制作工艺移除该氮化硅层以及该牺牲氧化层，使得该第一多晶硅层具有从两侧向下凹的表面。
11.如权利要求10所述的制作具有辅助栅的闪存存储器的方法，其中该第一蚀刻制作工艺移除具有下凹表面的部分该第一多晶硅层，形成外侧具有向上突起的尖端部位的该两个浮动栅。
12.如权利要求9所述的制作具有辅助栅的闪存存储器的方法，还包含：
进行第一离子注入制作工艺在该浮动栅之间的该基底中形成源极，其中该源极有部分与该两个浮动栅重叠；以及
进行第二离子注入制作工艺在该两个选择栅的外侧的该基底中分别形成漏极。
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