CN111951852A - Nonvolatile memory processing method and device - Google Patents
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Abstract
The embodiment of the invention provides a nonvolatile memory processing method and a nonvolatile memory processing device, wherein the method comprises the following steps: under the condition that the short-circuited word lines exist in the nonvolatile memory, determining the number of the short-circuited word lines and a target storage block corresponding to the short-circuited word lines; merging the word lines in the target memory block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines; and when the target storage block is subjected to preset processing, processing is carried out by taking the target word line as a unit word line. According to the embodiment of the invention, the word lines of the originally abandoned bad blocks are merged to obtain the target storage Block which can be used as the storage space, so that the accessible space of the nonvolatile memory is improved.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for processing a nonvolatile memory.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices have been developed. For example, a non-volatile Memory NAND Flash (NAND Flash Memory) is taken as an example, and the NAND Flash stores data by performing read-write operation on a Memory cell (Memory cell), has the advantages of high rewriting speed, large storage capacity and the like, and is widely used in electronic products. During the production and use of the nonvolatile memory, a phenomenon (WL-WL short) in which adjacent Word Lines (WL) are short-circuited may occur due to a production process or other reasons, and since the read-write operation of the NAND Flash is WL-based, the short-circuit phenomenon causes an error in read-write.
In the prior art, if a WL-WL short occurs in the nonvolatile memory, a whole Block (memory Block) corresponding to a word line with a short circuit is marked as a bad Block, for example, as shown in fig. 1, a situation that WL2 and WL3 are short-circuited is shown, in the prior art, a Block where WL2 and WL3 are located is marked as a bad Block, and the bad Block is idle and cannot be used for reading and writing operations and the like in subsequent reading, writing, erasing operations and the like of the nonvolatile memory.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: discarding the Block with the word line shorted reduces the accessible space of the non-volatile memory.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present invention provide a method and an apparatus for processing a nonvolatile memory, so as to improve an accessible space of the nonvolatile memory.
According to a first aspect of the present invention, there is provided a non-volatile memory processing method, the method comprising:
under the condition that the short-circuited word lines exist in the nonvolatile memory, determining the number of the short-circuited word lines and a target storage block corresponding to the short-circuited word lines;
merging the word lines in the target memory block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines;
and when the target storage block is subjected to preset processing, processing is carried out by taking the target word line as a unit word line.
Optionally, before determining the number of the short word lines and the target memory block corresponding to the short word lines when the short word lines are detected to exist in the nonvolatile memory, the method further includes:
detecting whether a shorted word line exists in the non-volatile memory.
Optionally, the detecting whether there is a short word line in the nonvolatile memory includes:
for a first word line and a second word line adjacent in the nonvolatile memory, applying a first voltage to the first word line and applying a second voltage to the second word line; wherein a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value;
judging whether the drop value of the first voltage of the first word line is larger than a second preset voltage value or not, or whether the drop value of the second voltage of the second word line is larger than the second preset voltage value or not within a preset time;
and under the condition that the drop value of the first voltage of the first word line is greater than the second preset voltage value or the drop value of the second voltage of the second word line is greater than the second preset voltage value, determining that the first word line and the second word line are short-circuited word lines.
Optionally, the method further includes:
setting a target identifier of the target storage block, wherein the target identifier comprises: a target word line address for each of the target word lines.
Optionally, when performing the preset processing on the target memory block, performing the processing by using the target word line as a unit word line includes:
when the target storage block is subjected to preset processing, determining a to-be-processed address in the target identifier;
performing the preset processing on the address to be processed; wherein the preset processing comprises: a read process or a write process.
According to a second aspect of the present invention, there is provided a non-volatile memory processing apparatus, the apparatus comprising:
the determining module is used for determining the number of the short-circuited word lines and the target storage block corresponding to the short-circuited word lines under the condition that the short-circuited word lines are detected in the nonvolatile memory;
the merging module is used for merging the word lines in the target storage block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines;
and the processing module is used for processing the word lines by taking the target word lines as units when the target storage block is subjected to preset processing.
Optionally, the method further includes:
and the detection module is used for detecting whether the word line with the short circuit exists in the nonvolatile memory.
Optionally, the detection module includes:
a voltage application submodule for applying a first voltage to a first word line and applying a second voltage to a second word line adjacent to the first word line and the second word line in the nonvolatile memory; wherein a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value;
the first judgment submodule is used for judging whether the drop value of the first voltage of the first word line is larger than a second preset voltage value or not, or whether the drop value of the second voltage of the second word line is larger than the second preset voltage value or not within a preset time;
and the second determining submodule is used for determining that the first word line and the second word line are short-circuited word lines under the condition that the drop value of the first voltage of the first word line is greater than the second preset voltage value or the drop value of the second voltage of the second word line is greater than the second preset voltage value.
Optionally, the method further includes:
a setting module, configured to set a target identifier of the target storage block, where the target identifier includes: a target word line address for each of the target word lines.
Optionally, the processing module includes:
a to-be-processed address determining submodule, configured to determine a to-be-processed address in the target identifier when performing preset processing on the target storage block;
the processing submodule is used for carrying out the preset processing on the address to be processed; wherein the preset processing comprises: a read process or a write process.
In the embodiment of the invention, under the condition that a short-circuited word line exists in a nonvolatile memory, the number of the short-circuited word lines and a target memory block corresponding to the short-circuited word line are determined firstly, then the word lines in the target memory block are merged into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line, and the short-circuited word line is included in one of the target word lines, namely the short-circuited word line is merged into one target word line, so that the adjacent target word lines do not have a short-circuit phenomenon in the target word lines, and further, when the target memory block is subjected to preset processing such as reading and writing, the target memory block can be correctly read and written by using the target word line as a unit word line. That is, in the embodiment of the present invention, word line merging is performed on the originally discarded bad blocks to obtain the target memory Block that can be used as a memory space, so that the accessible space of the nonvolatile memory is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a word line short circuit provided in the prior art;
FIG. 2 is a flow chart of a method for processing a non-volatile memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a word line merge according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for processing a non-volatile memory according to the present invention;
FIG. 5 is a block diagram of a non-volatile memory processing device according to an embodiment of the present invention;
FIG. 6 is a detailed block diagram of a nonvolatile memory processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 2, a flowchart of a processing method of a nonvolatile memory is shown, which may specifically include the following steps:
step 101: and under the condition that the short-circuited word lines exist in the nonvolatile memory, determining the number of the short-circuited word lines and the target memory block corresponding to the short-circuited word lines.
In the embodiment of the present invention, the adjacent word lines in the nonvolatile memory may be subjected to short circuit detection, specifically, if the adjacent word lines are short-circuited, the potentials of the adjacent word lines tend to be the same, so that the adjacent word lines in the nonvolatile memory may be subjected to short circuit detection according to the principle.
In a specific application, in the case that a short-circuited word line is detected in the nonvolatile memory, the number of the short-circuited word lines can be determined, for example, two adjacent word lines may be short-circuited, or three adjacent word lines may be short-circuited, or four adjacent word lines may be short-circuited, etc.; further, the number of the shorted word lines may be: the maximum number of word lines that are shorted; after the short word line is determined, the target memory block corresponding to the short word line can be determined according to the address corresponding to the short word line.
Step 102: merging the word lines in the target memory block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines.
In the embodiment of the present invention, the word line that is shorted needs to be set in one target word line to enable the adjacent target word lines not to be shorted, and therefore, after the number of shorted word lines is determined, the word lines in the target memory block may be merged into a plurality of target word lines in a manner of merging a preset number of adjacent word lines into one target word line, specifically, the preset number needs to be greater than or equal to the number of shorted word lines to enable the shorted word lines to be included in one of the plurality of target word lines, for example, as shown in fig. 3, if only the word line WL2 is shorted with the word line WL3, the number of shorted word lines may be determined to be 2, and therefore, the preset number may be set to 2, then WL0 and WL1 are merged into one target word line, WL2 and WL3 are merged into one target word line, and WL4 and WL4 are merged into one target word line, it is understood that the target word line may use any one address of a plurality of word lines included in the target word line as a target address, so that when the target memory block is subsequently processed, the target word line may correspond to the corresponding target word line according to the target address.
Step 103: and when the target storage block is subjected to preset processing, processing is carried out by taking the target word line as a unit word line.
In the embodiment of the present invention, the preset process may be a read process or a write process, and when the read process or the write process is performed on the target memory block, the word line may be processed in units of target word lines. For example, taking a Block including 62 word lines, the number of the word lines in which the short circuit occurs being 2, and the preset number being 2 as an example, the 62 word lines of the Block may be merged into 31 target word lines, the access space corresponding to the 31 target word lines is an available access space, and based on the 31 word lines, the read processing or the write processing may be performed in the target memory Block.
In summary, in the embodiments of the present invention, when a short-circuited word line is detected in a nonvolatile memory, the number of the short-circuited word lines and a target memory block corresponding to the short-circuited word line are determined, and then word lines in the target memory block are merged into a plurality of target word lines in a manner that a preset number of adjacent word lines are merged into one target word line, where the short-circuited word line is included in one of the target word lines, that is, the short-circuited word line is merged into one target word line, so that there is no short circuit phenomenon in adjacent target word lines in the target word lines, and further, when performing preset processing such as reading and writing on the target memory block, the target memory block may perform correct reading and writing on the word lines in units of the target word lines. That is, in the embodiment of the present invention, word line merging is performed on the originally discarded bad blocks to obtain the target memory Block that can be used as a memory space, so that the accessible space of the nonvolatile memory is improved.
Example two
Referring to fig. 4, a specific flowchart of a nonvolatile memory processing method is shown, which may specifically include the following steps:
step 201: detecting whether a shorted word line exists in the non-volatile memory.
In the embodiment of the present invention, the adjacent word lines in the nonvolatile memory may be subjected to short circuit detection, specifically, if the adjacent word lines are short-circuited, the potentials of the adjacent word lines tend to be the same, so that the adjacent word lines in the nonvolatile memory may be subjected to short circuit detection according to the principle.
As a specific implementation manner of the embodiment of the present invention, the detecting whether there is a short-circuited word line in the nonvolatile memory includes:
substep a1 (not shown): for a first word line and a second word line adjacent in the nonvolatile memory, applying a first voltage to the first word line and applying a second voltage to the second word line; wherein a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value.
In the embodiment of the invention, the first voltage applied to the first word line can be larger than the second voltage applied to the second word line; the first voltage applied to the first word line may also be smaller than the second voltage applied to the second word line, and it is only necessary that a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value. In a specific application, the first preset voltage may be set according to an actual application scenario, which is not specifically limited in the embodiment of the present invention.
Substep a2 (not shown): and judging whether the drop value of the first voltage of the first word line is greater than a second preset voltage value or not, or whether the drop value of the second voltage of the second word line is greater than the second preset voltage value or not within preset time.
In the embodiment of the invention, after the first voltage is applied to the first word line and the second voltage is applied to the second word line, because a voltage difference exists between the first voltage and the second voltage, the situation that the higher voltage is close to the lower voltage can occur; for example, taking the first voltage as 27V and the second voltage as 3V as an example, if the first word line and the second word line are shorted, the 27V voltage of the first word line approaches the second voltage at a faster speed, so that it can be determined whether a drop value of the first voltage of the first word line is greater than a second preset voltage value within a preset time, and if the drop value is greater than the second preset voltage value, it indicates that the first word line and the second word line are shorted. It is understood that the first voltage may also be smaller than the second voltage, and when the drop value of the second voltage of the second word line is larger than the second preset voltage value, it may be said that the first word line and the second word line are short-circuited, which is not described herein again.
Substep a3 (not shown): and under the condition that the drop value of the first voltage of the first word line is greater than the second preset voltage value or the drop value of the second voltage of the second word line is greater than the second preset voltage value, determining that the first word line and the second word line are short-circuited word lines.
In the embodiment of the present invention, as described in sub-step a2, when the drop value of the first voltage of the first word line is greater than the second preset voltage value, or the drop value of the second voltage of the second word line is greater than the second preset voltage value, it is determined that the first word line and the second word line are short-circuited word lines, which is not described herein again.
Step 202: and under the condition that the short-circuited word lines exist in the nonvolatile memory, determining the number of the short-circuited word lines and the target memory block corresponding to the short-circuited word lines.
Step 203: merging the word lines in the target memory block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines.
In a specific application, step 203 may also be implemented as follows: only by merging the short-circuited word lines into one valid word line in the target memory block, and keeping the other word lines unchanged, the target memory block may also be used as an accessible space, which is not specifically limited in the embodiment of the present invention.
Step 204: setting a target identifier of the target storage block, wherein the target identifier comprises: a target word line address for each of the target word lines.
In the embodiment of the present invention, for each target word line, the target word line address may be: in practical applications, a person skilled in the art may also define the target word line address of the target word line as needed, which is not specifically limited in the embodiment of the present invention.
Step 205: and when the target storage block is subjected to preset processing, determining a to-be-processed address in the target identifier.
In a specific application, when performing a preset process of a read process or a write process on a target memory block, a to-be-processed address is generally required to be determined in a target memory block, for example, when performing the write process, a write address is required to be selected, and when performing the read process, a read address is required to be determined.
Step 206: performing the preset processing on the address to be processed; wherein the preset processing comprises: a read process or a write process.
In summary, in the embodiments of the present invention, when a short-circuited word line is detected in a nonvolatile memory, the number of the short-circuited word lines and a target memory block corresponding to the short-circuited word line are determined, and then word lines in the target memory block are merged into a plurality of target word lines in a manner that a preset number of adjacent word lines are merged into one target word line, where the short-circuited word line is included in one of the target word lines, that is, the short-circuited word line is merged into one target word line, so that there is no short circuit phenomenon in adjacent target word lines in the target word lines, and further, when performing preset processing such as reading and writing on the target memory block, the target memory block may perform correct reading and writing on the word lines in units of the target word lines. That is, in the embodiment of the present invention, word line merging is performed on the originally discarded bad blocks to obtain the target memory Block that can be used as a memory space, so that the accessible space of the nonvolatile memory is improved.
EXAMPLE III
Referring to fig. 5, there is shown a block diagram of a non-volatile memory processing apparatus, which may specifically include:
a determining module 510, configured to determine, when it is detected that a short-circuited word line exists in the nonvolatile memory, the number of the short-circuited word line and a target memory block corresponding to the short-circuited word line;
a merging module 520, configured to merge word lines in the target memory block into a plurality of target word lines in a manner that a preset number of adjacent word lines are merged into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines;
the processing module 530 is configured to perform word line processing in units of the target word line when performing preset processing on the target memory block.
Preferably, referring to fig. 6, on the basis of fig. 5, the apparatus further comprises:
a detecting module 540, configured to detect whether there is a short word line in the nonvolatile memory.
The detection module 540 includes:
a voltage application submodule for applying a first voltage to a first word line and applying a second voltage to a second word line adjacent to the first word line and the second word line in the nonvolatile memory; wherein a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value;
the first judgment submodule is used for judging whether the drop value of the first voltage of the first word line is larger than a second preset voltage value or not, or whether the drop value of the second voltage of the second word line is larger than the second preset voltage value or not within a preset time;
and the second determining submodule is used for determining that the first word line and the second word line are short-circuited word lines under the condition that the drop value of the first voltage of the first word line is greater than the second preset voltage value or the drop value of the second voltage of the second word line is greater than the second preset voltage value.
Preferably, the method further comprises the following steps:
a setting module 550, configured to set a target identifier of the target storage block, where the target identifier includes: a target word line address for each of the target word lines.
The processing module 530 includes:
a to-be-processed address determining submodule, configured to determine a to-be-processed address in the target identifier when performing preset processing on the target storage block;
the processing submodule is used for carrying out the preset processing on the address to be processed; wherein the preset processing comprises: a read process or a write process.
In the embodiment of the invention, under the condition that a short-circuited word line exists in a nonvolatile memory, the number of the short-circuited word lines and a target memory block corresponding to the short-circuited word line are determined firstly, then the word lines in the target memory block are merged into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line, and the short-circuited word line is included in one of the target word lines, namely the short-circuited word line is merged into one target word line, so that the adjacent target word lines do not have a short-circuit phenomenon in the target word lines, and further, when the target memory block is subjected to preset processing such as reading and writing, the target memory block can be correctly read and written by using the target word line as a unit word line. That is, in the embodiment of the present invention, word line merging is performed on the originally discarded bad blocks to obtain the target memory Block that can be used as a memory space, so that the accessible space of the nonvolatile memory is improved.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), electrically-processable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (fransitory media), such as modulated data signals and carrier waves.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable non-volatile memory processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable non-volatile memory processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable non-volatile processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable non-volatile memory processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The present invention provides a nonvolatile memory processing method and a nonvolatile memory processing apparatus, which have been described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A non-volatile memory processing method, the method comprising:
under the condition that the short-circuited word lines exist in the nonvolatile memory, determining the number of the short-circuited word lines and a target storage block corresponding to the short-circuited word lines;
merging the word lines in the target memory block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines;
and when the target storage block is subjected to preset processing, processing is carried out by taking the target word line as a unit word line.
2. The method of claim 1, wherein in the case that the short-circuited word line is detected in the nonvolatile memory, determining the number of the short-circuited word lines and the target memory block corresponding to the short-circuited word line further comprises:
detecting whether a shorted word line exists in the non-volatile memory.
3. The method of claim 2, wherein said detecting whether a shorted word line exists in the non-volatile memory comprises:
for a first word line and a second word line adjacent in the nonvolatile memory, applying a first voltage to the first word line and applying a second voltage to the second word line; wherein a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value;
judging whether the drop value of the first voltage of the first word line is larger than a second preset voltage value or not, or whether the drop value of the second voltage of the second word line is larger than the second preset voltage value or not within a preset time;
and under the condition that the drop value of the first voltage of the first word line is greater than the second preset voltage value or the drop value of the second voltage of the second word line is greater than the second preset voltage value, determining that the first word line and the second word line are short-circuited word lines.
4. The method of claim 1, further comprising:
setting a target identifier of the target storage block, wherein the target identifier comprises: a target word line address for each of the target word lines.
5. The method according to claim 4, wherein the performing the preset processing on the target memory block by using the target word line as a unit word line comprises:
when the target storage block is subjected to preset processing, determining a to-be-processed address in the target identifier;
performing the preset processing on the address to be processed; wherein the preset processing comprises: a read process or a write process.
6. A non-volatile memory processing apparatus, the apparatus comprising:
the determining module is used for determining the number of the short-circuited word lines and the target storage block corresponding to the short-circuited word lines under the condition that the short-circuited word lines are detected in the nonvolatile memory;
the merging module is used for merging the word lines in the target storage block into a plurality of target word lines in a mode of merging a preset number of adjacent word lines into one target word line; wherein the preset number is greater than or equal to the number of the short-circuited word lines, and the short-circuited word lines are included in one of the plurality of target word lines;
and the processing module is used for processing the word lines by taking the target word lines as units when the target storage block is subjected to preset processing.
7. The apparatus of claim 6, further comprising:
and the detection module is used for detecting whether the word line with the short circuit exists in the nonvolatile memory.
8. The apparatus of claim 7, wherein the detection module comprises:
a voltage application submodule for applying a first voltage to a first word line and applying a second voltage to a second word line adjacent to the first word line and the second word line in the nonvolatile memory; wherein a voltage difference between the first voltage and the second voltage is greater than a first preset voltage value;
the first judgment submodule is used for judging whether the drop value of the first voltage of the first word line is larger than a second preset voltage value or not, or whether the drop value of the second voltage of the second word line is larger than the second preset voltage value or not within a preset time;
and the second determining submodule is used for determining that the first word line and the second word line are short-circuited word lines under the condition that the drop value of the first voltage of the first word line is greater than the second preset voltage value or the drop value of the second voltage of the second word line is greater than the second preset voltage value.
9. The apparatus of claim 6, further comprising:
a setting module, configured to set a target identifier of the target storage block, where the target identifier includes: a target word line address for each of the target word lines.
10. The apparatus of claim 9, wherein the processing module comprises:
a to-be-processed address determining submodule, configured to determine a to-be-processed address in the target identifier when performing preset processing on the target storage block;
the processing submodule is used for carrying out the preset processing on the address to be processed; wherein the preset processing comprises: a read process or a write process.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020145907A1 (en) * | 2001-04-10 | 2002-10-10 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device having word line defect check circuit |
| US20060233014A1 (en) * | 2005-04-18 | 2006-10-19 | Jong-Hoon Oh | Redundancy circuits for semiconductor memory |
| CN101271732A (en) * | 2007-03-19 | 2008-09-24 | 力晶半导体股份有限公司 | Method for testing a word line failure |
| US20170098478A1 (en) * | 2015-10-02 | 2017-04-06 | Macronix International Co., Ltd. | Method and apparatus for improving yield for non-volatile memory |
-
2019
- 2019-05-14 CN CN201910399735.9A patent/CN111951852A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020145907A1 (en) * | 2001-04-10 | 2002-10-10 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device having word line defect check circuit |
| US20060233014A1 (en) * | 2005-04-18 | 2006-10-19 | Jong-Hoon Oh | Redundancy circuits for semiconductor memory |
| CN101271732A (en) * | 2007-03-19 | 2008-09-24 | 力晶半导体股份有限公司 | Method for testing a word line failure |
| US20170098478A1 (en) * | 2015-10-02 | 2017-04-06 | Macronix International Co., Ltd. | Method and apparatus for improving yield for non-volatile memory |
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