CN111937118A - Capping layers of hafnium oxide based ferroelectric materials - Google Patents

Capping layers of hafnium oxide based ferroelectric materials Download PDF

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CN111937118A
CN111937118A CN201980024523.0A CN201980024523A CN111937118A CN 111937118 A CN111937118 A CN 111937118A CN 201980024523 A CN201980024523 A CN 201980024523A CN 111937118 A CN111937118 A CN 111937118A
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hfo
layer
capping layer
capping
depositing
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衡石·亚历山大·尹
朱忠伟
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Lam Research Corp
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Abstract

Formation of ferroelectric hafnium oxide (HfO) in substrate processing system2) The method comprises the following steps: deposition of HfO on a substrate2A layer; in the HfO2Depositing a capping layer over the layer; making the HfO2Annealing the layer and the capping layer to form a ferroelectric hafnium HfO2(ii) a And selectively etching the capping layer to remove the capping layer without etchingRemoving the HfO2And (3) a layer.

Description

Capping layers of hafnium oxide based ferroelectric materials
Cross Reference to Related Applications
This application claims the benefit of U.S. provisional application No.62/651,466 filed on 2.4.2018. The entire disclosure of the above-referenced application is incorporated herein by reference.
Technical Field
The present disclosure relates to methods for processing substrates, and more particularly to methods for reducing leakage current in hafnium oxide based ferroelectric materials.
Background
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Based on hafnium oxide (HfO)2) The discovery of ferroelectric properties in the materials of (a) has stimulated research into ferroelectric memories (ferams). Conventional ferroelectric materials, such as lead zirconate titanate (PZT), do not have a sufficient switching window for thicknesses below 50 nanometers (nm). Therefore, PZT cannot be used for devices with feature sizes smaller than 50 nm.
HfO due to high coercive field2The ferroelectric switch of (3) has a hysteresis as low as 6nm in thickness. HfO2And is also an ideal choice for 3D memory structures. HfO2Have been widely used as gate dielectrics in CMOS technology. In these applications, conformal Atomic Layer Deposition (ALD) is used to deposit HfO2. Thus, HfO2It may be suitable to integrate into 3D FeRAM using current 3D NAND integration schemes.
Disclosure of Invention
Formation of ferroelectric hafnium oxide (HfO) in substrate processing system2) The method comprises the following steps: deposition of HfO on a substrate2A layer; in the HfO2Depositing a capping layer over the layer; making the HfO2Annealing the layer and the capping layer to formFerroelectric hafnium HfO2(ii) a And selectively etching the capping layer to remove the capping layer without removing the HfO2And (3) a layer.
In other features, the capping layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon dioxide (SiO)2) And alumina (Al)2O3) Materials in the group consisting of. The capping layer does not include any one of titanium and tantalum. The method also includes nitriding the HfO prior to depositing the capping layer2And (3) a layer. The method also includes after removing the capping layer, after the HfO2A top electrode is deposited over the layer. The top electrode comprises a material selected from the group consisting of titanium, tantalum, and tungsten.
In other features, selectively etching the capping layer includes wet etching the capping layer using a dilute hydrofluoric acid solution. Selectively etching the capping layer includes dry plasma etching the capping layer using plasma generated from at least one of a fluorocarbon plasma and a halogen plasma. Making the HfO2Annealing the layer and the capping layer to form a ferroelectric hafnium HfO2Comprising performing a rapid thermal annealing process at a temperature in the range of 500 to 1000 ℃.
In other features, the method further comprises depositing a bottom electrode on the substrate, wherein depositing the HfO2Layer including depositing the HfO on the bottom electrode2And (3) a layer. The method also includes applying the HfO to the substrate before depositing the capping layer2The layer is subjected to plasma treatment. The method further comprises the following steps: repairing the HfO after selectively etching the capping layer2A layer; and in repairing the HfO2After the layer, on the HfO2A top electrode is deposited over the layer. Repairing the HfO2The layer includes an additional HfO2Depositing a material to the HfO2On the layer.
A method configured to form ferroelectric hafnium oxide (HfO) on a substrate in a processing chamber2) The system comprises: a gas delivery system configured to supply a process gas to the process chamber; and a Radio Frequency (RF) generation system configured to select within the processing chamberPlasma is selectively generated. A controller is configured to: depositing HfO on the substrate2Layer on the HfO2Depositing a capping layer on the layer to cause the HfO to2Annealing the layer and the capping layer to form a ferroelectric hafnium HfO2(ii) a And selectively etching the capping layer to remove the capping layer without removing the HfO2And (3) a layer.
In other features, the capping layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon dioxide (SiO)2) And alumina (Al)2O3) Materials in the group consisting of. The capping layer does not include any one of titanium and tantalum. The controller is further configured to cause the HfO to be deposited before depositing the capping layer2The layer is nitrided. The controller is further configured to remove the capping layer after HfO2A top electrode is deposited over the layer. The top electrode comprises a material selected from the group consisting of titanium, tantalum, and tungsten.
In other features, selectively etching the capping layer includes wet etching the capping layer using a dilute hydrofluoric acid solution. Selectively etching the capping layer includes dry plasma etching the capping layer using plasma generated from at least one of a fluorocarbon plasma and a halogen plasma. Making the HfO2Annealing the layer and the capping layer to form a ferroelectric hafnium HfO2The method comprises the following steps: the rapid thermal annealing process is performed at a temperature in the range of 500 to 1000 ℃.
In other features, the controller is further configured to deposit a bottom electrode on the substrate, wherein depositing the HfO2Layer including depositing the HfO on the bottom electrode2And (3) a layer. The controller is further configured to treat the HfO prior to depositing the capping layer2The layer is subjected to plasma treatment. The controller is further configured to: repairing the HfO after selectively etching the capping layer2A layer; and in repairing the HfO2After the layer, on the HfO2A top electrode is deposited over the layer. Repairing the HfO2The layer includes an additional HfO2Material depositionTo the HfO2On the layer.
Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Drawings
The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
FIG. 1 is a schematic diagram of a process for forming ferroelectric hafnium oxide (HfO) according to the present disclosure2) A functional block diagram of an exemplary substrate processing system of layers;
FIGS. 2A to 2F are diagrams for forming an HfO including ferroelectric material2A side cross-sectional view of an exemplary process of the apparatus of (1);
FIGS. 3A and 3B are diagrams for repairing ferroelectric HfO2A side cross-sectional view of an exemplary process of layers;
fig. 4A-4F are diagrams for forming a structure including ferroelectric HfO in accordance with the present disclosure2A side cross-sectional view of an exemplary process of the apparatus of (1); and
FIG. 5 illustrates the formation of a ferroelectric HfO using a sacrificial capping layer in accordance with the present disclosure2Exemplary method of layer.
In the drawings, reference numbers may be repeated to identify similar and/or identical elements.
Detailed Description
HfO2Is an obstacle to commercialization of FeRAM applications. Although the temperature of 600-650 deg.C is high enough to deposit amorphous HfO2Crystallizes into a ferroelectric phase, but many integration schemes require a thermal budget of at least 1000 ℃. Higher process temperatures can cause HfO-based defects by increasing leakage current and/or shorting the device2The FeRAM is degraded. Leakage sources after high temperature anneal including top electrode/HfO2Defects are generated at the interface. Another source of leakage current includes HfO2The membrane of (a) is broken. With HfO2From the top and bottom electrodes (usually TiN) will diffuse freely to HfO2This eventually renders the device useless. For example, the top electrode is onUsed as a cap during annealing to prevent HfO2The layer transforms into a thermodynamically stable monoclinic phase. In monoclinic phase, HfO2Is not ferroelectric.
Systems and methods in accordance with the present disclosure enable a capping layer configured to form a ferroelectric HfO with reduced defects and leakage on a semiconductor substrate2And (3) a layer. For example, the capping layer may comprise an oxide and/or nitride other than TiN or for nitriding HfO2And (3) a layer. For example, the capping layer may include silicon nitride (SiN), silicon dioxide (SiO)2) Alumina (Al)2O3) Silicon oxynitride (SiO)xNy) Aluminum nitride (AlN), aluminum oxynitride (AlO)xNy) And the like. In some examples, the capping layer may include titanium or tantalum, such as tantalum pentoxide (Ta)2O5) Tantalum oxynitride (TaO)xNy) Titanium oxide (TiO)2) Titanium oxynitride (TiO)xNy) And the like. The material of the capping layer is chosen such that the ferroelectric HfO2Will pass through to HfO2Formed by annealing, and can be annealed from HfO2The capping layer is selectively removed (e.g., etched by dry or wet etching) and atoms in the capping layer do not diffuse to the HfO2In addition, HfO is not removed2Oxygen atom in (1). The material of the capping layer may also be selected to reduce interfacial stress and tune the HfO2Grain size and orientation, switching speed, residual polarization, and other properties.
The capping layer helps the orthorhombic ferroelectric HfO during annealing2While eliminating HfO caused by Ti diffusion2Degradation of (2). The capping layer may then be removed and a top electrode deposited on the HfO2The above. In some examples, HfO may be performed after annealing and before top electrode deposition2To repair HfO caused by annealing2Any rupture in (a). For example, HfO2The additional deposition may include performing two or more deposition cycles.
FIG. 1 illustrates a method for deposition and deposition using Atomic Layer Deposition (ALD) in accordance with the present disclosureSelectively doped HfO2Layer and depositing a capping layer to form ferroelectric HfO2Exemplary substrate processing system 100. Although in this example the HfO is performed in the same processing chamber2Deposition and doping of layers and deposition of capping layers, but separate process chambers may be used. For example, one or more deposition or etching steps may be performed using a transformer-coupled plasma (TCP) chamber, a Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber, a high pressure cvd (hpcvd) chamber, and/or a processing chamber using a remote plasma source, as described below.
Substrate processing system 100 includes a process chamber 102, process chamber 102 enclosing other components of substrate processing system 100 and containing an RF plasma. The substrate processing chamber 102 includes an upper electrode 104 and a substrate support, such as an electrostatic chuck (ESC) 106. During operation, substrate 108 is disposed on ESC 106.
For example only, the upper electrode 104 may include a showerhead 109 that introduces and distributes process gases. The showerhead 109 may comprise a stem that includes one end that is coupled to a top surface of the process chamber. The base portion is generally cylindrical and extends radially outwardly from the opposite end of the stem portion at a location spaced from the top surface of the process chamber. The substrate-facing surface or face plate of the base portion of the showerhead includes a plurality of holes for the flow of process or purge gases therethrough. Alternatively, the upper electrode 104 may comprise a conductive plate and the process gas may be introduced in another manner.
The ESC106 includes a conductive substrate 110 that serves as a lower electrode. The substrate 110 supports a heating plate 112, which may correspond to a ceramic multi-zone heating plate. A thermal resistance layer 114 may be disposed between the heating plate 112 and the substrate 110. The base plate 110 may include one or more coolant channels 116 for flowing coolant through the base plate 110.
The RF generation system 120 generates and outputs an RF voltage to one of the upper electrode 104 and the lower electrode (e.g., the substrate 110 of the ESC 106). The other of the upper electrode 104 and the substrate 110 may be DC grounded, AC grounded, or floating. By way of example only, the RF generation system 120 may include an RF voltage generator 122 that generates an RF voltage that is fed to the upper electrode 104 or the substrate 110 by a matching and distribution network 124. In other examples, the plasma may be generated inductively or remotely.
The gas delivery system 130 includes one or more gas sources 132-1, 132-2, …, and 132-N (collectively gas sources 132), where N is an integer greater than zero. The gas source provides one or more deposition precursors and mixtures thereof. The gaseous precursor may include for HfO2Layer and/or other layers. The gas source may also supply a purge gas and other gas species (e.g., Ar/H) containing nitrogen species for plasma nitridation and/or for other plasma treatments2、NH3、O2、O3Etc.) of a gas. Vaporized precursors may also be used. Gas source 132 is connected to manifold 138 by valves 134-1, 134-2, …, and 134-N (collectively referred to as valves 134) and mass flow controllers 136-1, 136-2, …, and 136-N (collectively referred to as mass flow controllers 136). The output of the manifold 138 is supplied to the process chamber 102. For example only, the output of the manifold 138 is supplied to the showerhead 109. In some examples, an optional ozone generator 140 may be provided between the mass flow controller 136 and the manifold 138. In some examples, the substrate processing system 100 may include a liquid precursor delivery system 141. The liquid precursor delivery system 141 may be incorporated within the gas delivery system 130 as shown, or may be external to the gas delivery system 130. The liquid precursor delivery system 141 is configured to provide a precursor that is liquid and/or solid at room temperature via bubbler, direct liquid injection, vapor pumping, and the like.
The temperature controller 142 may be connected to a plurality of heat control elements (TCEs) 144 disposed in the heater plate 112. For example, TCE 144 may include, but is not limited to, a respective large TCE corresponding to each zone in a multi-zone heating plate and/or an array of micro TCEs disposed across multiple zones of a multi-zone heating plate, as described in more detail in fig. 2A and 2B. A temperature controller 142 can be used to control a plurality of heating elements 144 to control the temperature of ESC106 and substrate 108.
The temperature controller 142 may be in communication with a coolant assembly 146 (e.g., including a coolant pump, a coolant reservoir, or a coolant source) to control the flow of coolant through the passage 116. The temperature controller 142 operates the coolant assembly 146 to selectively flow coolant through the channels 116 to cool the ESC 106.
A valve 150 and pump 152 can be used to evacuate the reactants from the process chamber 102. The system controller 160 can be used to control the components of the substrate processing system 100. Robot 170 can be used to transfer substrates to ESC106 and remove substrates from ESC 106. For example, robot 170 can transfer substrates between ESC106 and load lock 172. Although the temperature controller 142 is shown as a separate controller, the temperature controller 142 may be implemented within the system controller 160.
Referring now to fig. 2A, 2B, 2C, 2D, 2E, and 2F, a method for forming a (HfO) -based film in device 200 is shown2) Exemplary processes for ferroelectric materials of (1). In fig. 2A, the apparatus 200 includes a substrate (e.g., one or more underlying layers) 204 and an interface layer 208 disposed on the underlying layer 204. For example, underlayer 204 comprises silicon (Si). In some examples, the interfacial layer 208 corresponds to a bottom electrode comprising titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W), although other electrode materials may be used. Other examples include, but are not limited to, platinum (Pt), gold (Au), palladium (Pd), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), and the like. In other examples, the interfacial layer 208 may comprise silicon dioxide (SiO)2) Or silicon oxynitride (SiON). In some examples, the interfacial layer 208 is deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). In other examples, the interfacial layer 208 may be formed via thermal oxidation of Si. For example, the interface layer 208 may be formed by: in the presence of nitrogen species (e.g. N)2O or N2) Thermally oxidizing Si to form SiON, and oxidizing SiO2Plasma nitridation is performed, and so on.
As shown in FIG. 2B, HfO is deposited on the interfacial layer 2082 Layer 212. In some examples, deposited HfO2The thickness of layer 212 is in the range of 2nm to 12 nm. In some examples, HfO is doped using a dopant species selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), and/or lanthanum (La)2 Layer 212 is doped. In some examples, Atomic Layer Deposition (ALD) is used to deposit HfO2Layer 212, but may beOther processes are used. For example, thermal ALD or plasma enhanced ALD may be used. In some examples, HfO2Layer 212 is undoped. In other examples, HfO2Layer 212 is doped to a predetermined doping level that is greater than 0 mol% to less than or equal to 60 mol% of the selected dopant species. In some examples, HfO is used2 Layer 212 is doped to a predetermined doping level of 3 mol% to 5 mol% of the selected dopant species. HfO2Layer 212 may be amorphous.
Optionally performing a treatment on HfO2Plasma treatment of layer 212. For example, HfO2Layer 212 is nitrided by a plasma containing nitrogen species. For example, molecular nitrogen (N) may be used2) A gas. In some examples, the nitriding is performed for a predetermined period of time in a range from 15s to 60 s. In some examples, the RF power may be in the range of 100W to 15 kW. In some examples, the plasma power is in the range of 500W to 1200W. In some examples, the RF frequency may be in the range of 1MHz to 15 MHz. In some examples, the RF frequency is 2.0MHz and/or 13.56 MHz.
After the plasma treatment, as shown in FIG. 2C, after HfO2A top electrode 216 is deposited over layer 212. In some examples, the top electrode 216 comprises TiN, TaN, or W, but other electrode materials (e.g., Pt, Au, Pd, Al, Mo, Ni, Ti, etc.) may be used. In some examples, the top electrode 216 is deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). After depositing the top electrode 216, the apparatus 200 is annealed at a predetermined temperature of 500 ℃ to 1100 ℃. In other examples, the annealing temperature is 800 ℃ to 1000 ℃.
After annealing, the top electrode 216 is patterned as shown in fig. 2D, 2E and 2F. For example, as shown in FIG. 2D, a mask 220 may be deposited. The mask 220 may include platinum (Pt). As shown in fig. 2E, the top electrode 216 is etched using wet etching or dry etching. In some examples, mask 220 is optionally removed after etching, as shown in fig. 2F. In other examples, the mask is not removed.
Referring now to FIGS. 3A and 3B, there is shownAn exemplary process for repairing a device 300 is shown, the device 300 comprising a ferroelectric HfO formed in the manner shown in fig. 2A-2F2Layer 304. As shown in fig. 3A, annealing the apparatus 300 (e.g., as described above in fig. 2C) may result in HfO2A break in layer 304. For example, the one or more cracks 308 may extend partially or completely through the HfO2Layer 304. Thus, additional HfO may be performed2Deposition step (e.g., in one or more cycles) to deposit on HfO2Depositing a thin HfO over layer 3042 Film 312 to fill crack 308 and/or repair HfO2Other defects on the surface of layer 304, as shown in FIG. 3B. HfO2Cracks 308 and other defects (e.g., HfO) on the surface of the layer 3042Defects at the interface between layer 304 and the top electrode) may promote diffusion of Ti or Ta atoms from the top and bottom electrodes to the HfO2In layer 304, leakage current is increased, shorting device 300, etc., and may cause device 300 to fail.
Referring now to fig. 4A, 4B, 4C, 4D, 4E, and 4F, the formation of a (HfO) -based layer in a device 400 using a sacrificial capping layer in accordance with the present disclosure is shown2) Exemplary processes for ferroelectric materials of (1). In fig. 4A, the apparatus 400 includes a substrate (e.g., one or more underlying layers) 404 and an interface layer 408 disposed on the underlying layer 404. For example, underlayer 404 comprises silicon (Si), germanium (Ge), silicon-germanium (Si)xGe(1-x)) And the like. In some examples, the interfacial layer 408 corresponds to a bottom electrode comprising titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W), although other electrode materials (e.g., Pt, Au, Pd, Al, Mo, Ni, Ti, etc.) may be used. In other examples, the interfacial layer 408 may comprise silicon dioxide (SiO)2) Or silicon oxynitride (SiON). In some examples, the interfacial layer 408 is deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD).
As shown in fig. 4B, HfO is deposited on the interfacial layer 4082 Layer 412. In some examples, deposited HfO2The thickness of layer 412 is in the range of 2nm to 12 nm. In some examples, a dopant selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), and/or lanthanum (La) is usedDoping HfO with a substance2Layer 412. In some examples, Atomic Layer Deposition (ALD) is used to deposit HfO2Layer 412, but other processes may be used. For example, thermal ALD or plasma enhanced ALD may be used. In some examples, HfO2Layer 412 is undoped. In other examples, HfO2Layer 412 is doped to a predetermined doping level that is greater than 0 mol% to less than or equal to 60 mol% of the selected dopant species. In some examples, HfO is used2 Layer 412 is doped to a predetermined doping level of 3 mol% to 5 mol% of the selected dopant species. HfO2Layer 412 may be amorphous.
Optionally performing a treatment on HfO2Plasma treatment of layer 412. For example, HfO2Layer 412 is nitrided by a plasma containing a nitrogen species. For example, molecular nitrogen (N) may be used2) A gas. In some examples, the nitriding is performed for a predetermined period of time in the range of 15s to 60 s. In some examples, the RF power may be in the range of 100W to 15 kW. In some examples, the plasma power is in the range of 500W to 1200W. In some examples, the RF frequency may be in the range of 1MHz to 15 MHz. In some examples, the RF frequency is 2.0MHz and/or 13.56 MHz.
After the plasma treatment, as shown in FIG. 4C, after HfO2A capping layer 416 (e.g., a sacrificial dielectric layer) is deposited over layer 412. In some examples, capping layer 416 includes a material for nitridizing HfO2An oxide and/or nitride of a layer other than TiN. For example, capping layer 416 may comprise silicon nitride (SiN), silicon dioxide (SiO)2) Alumina (Al)2O3) Silicon oxynitride (SiO)xNy) Aluminum nitride (AlN), aluminum oxynitride (AlO)xNy) Tantalum pentoxide (Ta)2O5) Tantalum oxynitride (TaO)xNy) Titanium oxide (TiO)2) Titanium oxynitride (TiO)xNy) And the like. In some examples, capping layer 416 is deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). After depositing the cap layer 416, the apparatus 400 is brought to a predetermined temperature in the range of 500 ℃ to 1100 ℃Annealing at low temperature to form ferroelectric HfO2. In other examples, the annealing temperature is in a range of 800 ℃ to 1000 ℃.
After annealing, as shown in FIG. 4D, from HfO2Layer 412 removes cap layer 416 (e.g., by dry etching or wet etching). For example, it can be used in combination with HfO2The removal of cap layer 416 is performed in a different processing chamber than the deposition of layer 412 and cap layer 416. A mask configured to selectively remove capping layer 416 without removing HfO may be used2The material of layer 412 to perform the etch. In other words, the etch is configured to selectively etch the material of the capping layer 416.
In an exemplary wet etch process, a dilute hydrofluoric acid (HF) solution may be supplied to the process chamber to selectively etch the SiN-containing cap layer 416. In one example, the diluted hydrofluoric acid solution may comprise hydrofluoric acid dissolved in an aqueous or non-aqueous (e.g., alcohol) solvent. The ratio of solvent to hydrofluoric acid in the solution may be between 10: 1 and 100: 1. The dilute hydrofluoric acid solution is selective to etching SiN. In contrast, HfO2Stable in dilute hydrofluoric acid. For example, exposure to wet etch using dilute hydrofluoric acid for ten minutes may result from HfO2Layer 412 is etched to less than 0.2nm of material while cap layer 416 is completely removed.
Is configured at HfO2An exemplary dry plasma etch process for upper selective etching of SiN may use, but is not limited to, a process consisting of fluoromethane (CH)3F) And molecular oxygen (O)2) Nitrogen trifluoride (NF)3) And chlorine (Cl)2)、NF3And O2And tetrafluoromethane (CF)4) And O2The plasma generated. Configured to selectively etch on HfO2SiO on2May be used with a dry plasma etch process consisting of CF4And O2The plasma generated. In contrast, with boron trichloride (BCl)3) The generated plasma can substantially etch the HfO2Layer 412. Therefore, for selectively dry etching on HfO2Suitable plasmas of SiN above may comprise fluorocarbon and/or halogen plasmas.
After removal of capping layer 416, one or more additional repair and/or cleaning steps may be performed to repair HfO that may be present during annealing and etching of capping layer 4162Any damage caused by layer 412. For example, the repairing step may include performing one or more HfOs2Deposition cycle to deposit on HfO2Depositing additional HfO over layer 4122A material.
Then, as shown in FIG. 4E, in HfO2A top electrode 420 is deposited over layer 412. In some examples, the top electrode 420 comprises TiN, TaN, or W, but other electrode materials (e.g., Pt, Au, Pd, Al, Mo, Ni, Ti, etc.) may be used. In some examples, the top electrode 420 is deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). After depositing the top electrode 420, the top electrode 420 may be patterned as shown in fig. 4F (e.g., by depositing a mask on the top electrode 420, etching the top electrode 420, removing the mask, etc.).
Referring now to fig. 5, a method for forming ferroelectric HfO using a sacrificial capping layer in accordance with the present disclosure2The exemplary method 500 of layers begins at 504. At 508, a substrate is provided. For example, a substrate containing one or more underlying layers is disposed on a substrate support in a substrate processing chamber. At 512, an interfacial layer is deposited on the substrate. The interfacial layer may comprise silicon dioxide (SiO)2) Or silicon oxynitride (SiON), and/or may correspond to a bottom electrode comprising titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W). The interfacial layer may be deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). At 516, doped or undoped HfO2A layer is deposited on the interfacial layer (e.g., using ALD). At 520, optionally performing a smoothing of the HfO2Plasma treatment of the layer. For example, HfO2The layer may be nitrided by a plasma containing a nitrogen species.
At 524, at HfO2A capping layer (e.g., a sacrificial capping layer) is deposited over the layer. For example, the capping layer may include silicon nitride (SiN), silicon dioxide (SiO)2) Alumina (Al)2O3) Silicon oxynitride (SiO)xNy) Aluminum nitride (A)lN), aluminum oxynitride (AlO)xNy) Tantalum pentoxide (Ta)2O5) Tantalum oxynitride (TaO)xNy) Titanium oxide (TiO)2) Titanium oxynitride (TiO)xNy) And the like. The capping layer may be deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). At 528, the substrate, the interface layer, and the HfO are formed2The layer and the capping layer are annealed at a predetermined temperature in the range of 500 ℃ to 1100 ℃ (e.g., 800 ℃ to 1000 ℃) to form ferroelectric HfO2. At 532, the cap layer is removed (e.g., by dry or wet etching). At 536, one or more additional repair and/or cleaning steps may optionally be performed. For example, the repairing step may include performing one or more HfOs2Deposition cycle to deposit on HfO2Depositing additional HfO over the layer2A material.
At 540, a top electrode (e.g., TiN, TaN, or W) is deposited on the nitrided HfO2On the layer. For example, the top electrode is deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). The top electrode can be patterned at 544 (e.g., a mask can be patterned over the top electrode) and etched at 548. The method 500 ends at 550.
The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps of the method may be performed in a different order (or simultaneously) without altering the principles of the present disclosure. Furthermore, although each embodiment is described above as having certain features, any one or more of those features described with respect to any embodiment of the present disclosure may be implemented in and/or combined with the features of any other embodiment, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and substitutions of one or more embodiments with one another remain within the scope of the present disclosure.
Various terms are used to describe spatial and functional relationships between elements (e.g., between modules, circuit elements, between semiconductor layers, etc.), including "connected," joined, "" coupled, "" adjacent, "" immediately adjacent, "" on top, "" above, "" below, "and" disposed. Unless a relationship between first and second elements is explicitly described as "direct", when such a relationship is described in the above disclosure, the relationship may be a direct relationship, in which no other intermediate elements are present between the first and second elements, but may also be an indirect relationship, in which one or more intermediate elements are present (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B and C" should be interpreted to mean logic (a OR B OR C) using a non-exclusive logic OR (OR), and should not be interpreted to mean "at least one of a, at least one of B, and at least one of C".
In some implementations, the controller is part of a system, which may be part of the above example. Such systems may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (wafer susceptors, gas flow systems, etc.). These systems may be integrated with electronics for controlling the operation of semiconductor wafers or substrates before, during, and after their processing. The electronic device may be referred to as a "controller," which may control various components or subcomponents of one or more systems. Depending on the process requirements and/or type of system, the controller can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, Radio Frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools, and/or load locks connected or interfaced with specific systems.
Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and/or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and so forth. An integrated circuit may include a chip in firmware that stores program instructions, a Digital Signal Processor (DSP), a chip defined as an Application Specific Integrated Circuit (ASIC), and/or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be in the form of various separate settings (or program files) that are sent to the controller to define the operating parameters for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to complete one or more process steps during fabrication of one or more layer(s), material, metal, oxide, silicon dioxide, surface, circuitry, and/or die of a wafer.
In some implementations, the controller can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the systems. For example, the controller may be in the "cloud" or all or part of a fab (fab) host system, which may allow remote access to wafer processing. The computer may implement remote access to the system to monitor the current progress of the manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or begin a new process. In some examples, a remote computer (e.g., a server) may provide the process recipe to the system over a network (which may include a local network or the internet). The remote computer may include a user interface that enables parameters and/or settings to be entered or programmed and then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool, such that the controller is configured to interface with or control the tool. Thus, as described above, the controllers can be distributed, for example, by including one or more discrete controllers networked together and operating toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller for such purposes may be one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely located (e.g., at a platform level or as part of a remote computer), which combine to control a process on the chamber.
Example systems can include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a Physical Vapor Deposition (PVD) chamber or module, a Chemical Vapor Deposition (CVD) chamber or module, an Atomic Layer Deposition (ALD) chamber or module, an Atomic Layer Etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that can be associated with or used in the manufacture and/or preparation of semiconductor wafers.
As described above, depending on the process step or steps to be performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, neighboring tools, tools located throughout a factory, a host computer, another controller, or a tool used in material transport to transport wafer containers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

Claims (26)

1. Formation of ferroelectric hafnium oxide (HfO) in substrate processing system2) The method of (1), the method comprising:
deposition of HfO on a substrate2A layer;
in the HfO2Depositing a capping layer over the layer;
making the HfO2Annealing the layer and the capping layer to form a ferroelectric hafnium HfO2(ii) a And
selectively etching the capping layer to remove the capping layer without removing the HfO2And (3) a layer.
2. The method of claim 1, wherein the capping layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon dioxide (SiO)2) And alumina (Al)2O3) Materials in the group consisting of.
3. The method of claim 1, wherein the capping layer does not comprise any one of titanium and tantalum.
4. The method of claim 1, further comprising nitriding the HfO prior to depositing the capping layer2And (3) a layer.
5. The method of claim 1, further comprising after removing the capping layer, after the HfO2A top electrode is deposited over the layer.
6. The method of claim 5, wherein the top electrode comprises a material selected from the group consisting of titanium, tantalum, and tungsten.
7. The method of claim 1, wherein selectively etching the capping layer comprises wet etching the capping layer using a dilute hydrofluoric acid solution.
8. The method of claim 1, wherein selectively etching the capping layer comprises dry plasma etching the capping layer using a plasma generated from at least one of a fluorocarbon plasma and a halogen plasma.
9. The method of claim 1, wherein the HfO is allowed to stand out2Layer and stationAnnealing the capping layer to form a ferroelectric hafnium HfO2Comprising performing a rapid thermal annealing process at a temperature in the range of 500 to 1000 ℃.
10. The method of claim 1, further comprising depositing a bottom electrode on the substrate, wherein the HfO is deposited2Layer including depositing the HfO on the bottom electrode2And (3) a layer.
11. The method of claim 1, further comprising subjecting the HfO to a treatment prior to depositing the capping layer2The layer is subjected to plasma treatment.
12. The method of claim 1, further comprising:
repairing the HfO after selectively etching the capping layer2A layer; and
repairing the HfO2After the layer, on the HfO2A top electrode is deposited over the layer.
13. The method of claim 12, wherein the HfO is repaired2The layer includes an additional HfO2Depositing a material to the HfO2On the layer.
14. A method configured to form ferroelectric hafnium oxide (HfO) on a substrate in a processing chamber2) The system of (1), the system comprising:
a gas delivery system configured to supply a process gas to the process chamber;
a Radio Frequency (RF) generation system configured to selectively generate a plasma within the processing chamber; and
a controller configured to control the gas delivery system and the RF generation system to,
depositing HfO on the substrate2A layer of a material selected from the group consisting of,
in the HfO2A cover layer is deposited on the layer(s),
making the HfO2Layer and stationAnnealing the capping layer to form a ferroelectric hafnium HfO2(ii) a And
selectively etching the capping layer to remove the capping layer without removing the HfO2And (3) a layer.
15. The system of claim 14, wherein the capping layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon dioxide (SiO)2) And alumina (Al)2O3) Materials in the group consisting of.
16. The system of claim 14, wherein the capping layer does not include any of titanium and tantalum.
17. The system of claim 14, wherein the controller is further configured to cause the HfO to be deposited prior to depositing the capping layer2The layer is nitrided.
18. The system of claim 14, wherein the controller is further configured to, after removing the capping layer, after HfO2A top electrode is deposited over the layer.
19. The system of claim 18, wherein the top electrode comprises a material selected from the group consisting of titanium, tantalum, and tungsten.
20. The system of claim 14, wherein selectively etching the capping layer comprises wet etching the capping layer using a dilute hydrofluoric acid solution.
21. The system of claim 14, wherein selectively etching the capping layer comprises dry plasma etching the capping layer using a plasma generated from at least one of a fluorocarbon plasma and a halogen plasma.
22. The system of claim 14, wherein the HfO is reacted2Annealing the layer and the capping layer to form a ferroelectric hafnium HfO2The method comprises the following steps: the rapid thermal annealing process is performed at a temperature in the range of 500 to 1000 ℃.
23. The system of claim 14, wherein the controller is further configured to deposit a bottom electrode on the substrate, wherein the HfO is deposited2Layer including depositing the HfO on the bottom electrode2And (3) a layer.
24. The system of claim 14, wherein the controller is further configured to treat the HfO prior to depositing the capping layer2The layer is subjected to plasma treatment.
25. The system of claim 14, wherein the controller is further configured to:
repairing the HfO after selectively etching the capping layer2A layer; and
in repairing the HfO2After the layer, on the HfO2A top electrode is deposited over the layer.
26. The system of claim 25, wherein the HfO is repaired2The layer includes an additional HfO2Depositing a material to the HfO2On the layer.
CN201980024523.0A 2018-04-02 2019-03-26 Capping layers of hafnium oxide based ferroelectric materials Pending CN111937118A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447508A (en) * 2020-11-24 2021-03-05 湘潭大学 Method for enhancing hafnium oxide (HfO) by plasma technology2) Method for determining ferroelectric properties of ferroelectric thin film

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890272A (en) * 2019-11-22 2020-03-17 中国科学院微电子研究所 Preparation method of hafnium oxide based ferroelectric film
US20230360932A1 (en) * 2022-05-03 2023-11-09 Samsung Electronics Co., Ltd. Method of fabricating an electrode structure and apparatus for fabricating the electrode structure

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356558A (en) 2003-05-30 2004-12-16 Toshio Goto Apparatus and method for coating
US6785120B1 (en) * 2003-07-03 2004-08-31 Micron Technology, Inc. Methods of forming hafnium-containing materials, methods of forming hafnium oxide, and capacitor constructions comprising hafnium oxide
US7008833B2 (en) 2004-01-12 2006-03-07 Sharp Laboratories Of America, Inc. In2O3thin film resistivity control by doping metal oxide insulator for MFMox device applications
US7402472B2 (en) 2005-02-25 2008-07-22 Freescale Semiconductor, Inc. Method of making a nitrided gate dielectric
US7709402B2 (en) * 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
JP2007318018A (en) 2006-05-29 2007-12-06 Toshiba Corp Ferroelectric memory cell and its manufacturing method
KR20080010623A (en) * 2006-07-27 2008-01-31 삼성전자주식회사 Nonvolatile semiconductor memory device and method for manufacturing the same
KR100877100B1 (en) * 2007-04-16 2009-01-09 주식회사 하이닉스반도체 Methods for manufacturing non-volatile memory device
WO2011101931A1 (en) 2010-02-17 2011-08-25 パナソニック株式会社 Semiconductor device and method for manufacturing same
US8724369B2 (en) * 2010-06-18 2014-05-13 Sandisk 3D Llc Composition of memory cell with resistance-switching layers
DE102011076695B4 (en) * 2011-05-30 2013-05-08 Globalfoundries Inc. Embedded strain inducing material transistors formed in cavities formed by an oxidation etch process
US8846443B2 (en) * 2011-08-05 2014-09-30 Intermolecular, Inc. Atomic layer deposition of metal oxides for memory applications
WO2013177326A1 (en) * 2012-05-25 2013-11-28 Advanced Technology Materials, Inc. Silicon precursors for low temperature ald of silicon-based thin-films
JP2014053568A (en) 2012-09-10 2014-03-20 Toshiba Corp Ferroelectric memory and method of manufacturing the same
US9231206B2 (en) 2013-09-13 2016-01-05 Micron Technology, Inc. Methods of forming a ferroelectric memory cell
US9269785B2 (en) * 2014-01-27 2016-02-23 Globalfoundries Inc. Semiconductor device with ferroelectric hafnium oxide and method for forming semiconductor device
US10242989B2 (en) 2014-05-20 2019-03-26 Micron Technology, Inc. Polar, chiral, and non-centro-symmetric ferroelectric materials, memory cells including such materials, and related devices and methods
US9647207B2 (en) * 2015-01-26 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Resistive random access memory (RRAM) structure
US9496169B2 (en) * 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
US10192751B2 (en) * 2015-10-15 2019-01-29 Lam Research Corporation Systems and methods for ultrahigh selective nitride etch
US9793397B1 (en) * 2016-09-23 2017-10-17 International Business Machines Corporation Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor
CN111954932A (en) * 2018-01-25 2020-11-17 株式会社半导体能源研究所 Semiconductor device with a plurality of semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447508A (en) * 2020-11-24 2021-03-05 湘潭大学 Method for enhancing hafnium oxide (HfO) by plasma technology2) Method for determining ferroelectric properties of ferroelectric thin film

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