CN111934531A - Three-phase neutral-line-free power factor correction circuit based on server data center - Google Patents
Three-phase neutral-line-free power factor correction circuit based on server data center Download PDFInfo
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- CN111934531A CN111934531A CN202010660748.XA CN202010660748A CN111934531A CN 111934531 A CN111934531 A CN 111934531A CN 202010660748 A CN202010660748 A CN 202010660748A CN 111934531 A CN111934531 A CN 111934531A
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- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4216—Arrangements for improving power factor of AC input operating from a three-phase input voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to the technical field of servers, and provides a three-phase neutral-line-free power factor correction circuit based on a server data center, which comprises an A-phase power factor correction circuit, a B-phase power factor correction circuit and a C-phase power factor correction circuit, so that the maximum voltage borne by a switching tube is half of the bus voltage, the voltage output level is increased, the harmonic content is smaller, the switching frequency is higher and lower on the premise of the same harmonic content, and the efficiency is improved.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a three-phase neutral-line-free power factor correction circuit based on a server data center.
Background
With the development of information technology, the scale of data centers is getting larger and larger, the capacity of power distribution systems is getting larger and larger, the single-phase UPS or HVDC system is difficult to meet customer requirements due to the limitation of excessive input current, three-phase input UPS and HVDC are generated at the same time, and the design scheme of three-phase neutral-line-free three-phase power factor correction circuits is becoming more important.
In the existing three-phase no-neutral three-phase power factor correction circuit, the single-phase input inductor is large in size and low in efficiency.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a three-phase neutral-line-free power factor correction circuit based on a server data center, and aims to solve the problems that in the three-phase neutral-line-free three-phase power factor correction circuit in the prior art, when single-phase input is used, the inductance is large, and the efficiency is low.
The technical scheme provided by the invention is as follows: a three-phase neutral-line-free power factor correction circuit based on a server data center comprises an A-phase power factor correction circuit, a B-phase power factor correction circuit and a C-phase power factor correction circuit;
the A-phase power factor correction circuit is connected with an A-phase voltage input end through a Boost inductor L1, the other end of the Boost inductor L1 is connected with a first switch tube group in series, the other end of the first switch tube group is connected with an equivalent capacitor C1 through a node Midpoint, the other end of the equivalent capacitor C1 is connected with a level VDC + point, a bus line led out by the node Midpoint is connected with the equivalent resistor C2 in series and then is connected with the level VDC-point, a first circuit node is arranged on a line between the Boost inductor L1 and the first switch tube group, a line led out by the first circuit node is connected with a diode D1 in series and then is connected with the level VDC + point, and another line led out by the first circuit node is connected with a diode D2 in series and then is connected with the level VDC-point;
the B-phase power factor correction circuit is connected with a B-phase voltage input end through a Boost inductor L2, the other end of the Boost inductor L2 is connected with a second switch tube group in series, the other end of the second switch tube group is converged to the node Midpoint, a second circuit node is arranged on a circuit between the Boost inductor L2 and the second switch tube group, a circuit led out from the second circuit node is connected with the level VDC + point after being connected with a diode D3 in series, and the second circuit node is connected with the level VDC-point after being led out from the other circuit and connected with a diode D4 in series;
the C-phase power factor correction circuit is connected with a C-phase voltage input end through a Boost inductor L3, the other end of the Boost inductor L3 is connected with a third switching tube group in series, the other end of the third switching tube group is converged to the node Midpoint, a third circuit node is arranged on a circuit between the Boost inductor L3 and the third switching tube group, a circuit led out from the third circuit node is connected with the level VDC + point after being connected with a diode D5 in series, and the other circuit led out from the third circuit node is connected with the level VDC-point after being connected with a diode D6 in series.
As an improved scheme, the first switch tube group comprises a switch tube Q1 with an anti-parallel diode and a switch tube Q2 with an anti-parallel diode which are connected in series in sequence;
the gates of the switch tube Q1 with the anti-parallel diode and the switch tube Q2 with the anti-parallel diode are respectively connected with two static contacts of the switch S1.
As an improved scheme, in the a-phase power factor correction circuit, when the driving signal is high, the switching tube Q1 is turned on or the switching tube Q2 is turned on, when the switching tube Q1 is turned on, the alternating voltage is in a positive half cycle, and when the switching tube Q2 is turned on, a negative half cycle of the alternating voltage is obtained;
when the driving signal is low, the switching tube Q1 and the switching tube Q2 are both turned off, and when the voltage is in a positive half cycle, the A-phase upper bridge arm diode D1 is turned on; when the voltage is negative for half a cycle, the a-phase lower arm diode D2 is turned on.
As a modified scheme, the second switch tube group comprises a switch tube Q3 with an anti-parallel diode and a switch tube Q4 with an anti-parallel diode which are connected in series in sequence;
the gates of the switch tube Q3 with the anti-parallel diode and the switch tube Q4 with the anti-parallel diode are respectively connected with two static contacts of the switch S2.
As an improved scheme, in the B-phase power factor correction circuit, when the driving signal is high, the switching tube Q3 is turned on or the switching tube Q4 is turned on, when the switching tube Q3 is turned on, the alternating voltage is in a positive half cycle, and when the switching tube Q4 is turned on, a negative half cycle of the alternating voltage is obtained;
when the driving signal is low, the switching tube Q3 and the switching tube Q4 are both turned off, and when the voltage is in a positive half cycle, the B-phase upper bridge arm diode D3 is turned on; when the voltage is negative for half a cycle, the B-phase lower arm diode D4 is turned on.
As a modified scheme, the third switching tube group comprises a switching tube Q5 with an anti-parallel diode and a switching tube Q6 with an anti-parallel diode which are connected in series in sequence;
the gates of the switch tube Q5 with the anti-parallel diode and the switch tube Q6 with the anti-parallel diode are respectively connected with two static contacts of the switch S3.
As an improved scheme, in the C-phase power factor correction circuit, when the driving signal is high, the switching tube Q5 is turned on or the switching tube Q6 is turned on, when the switching tube Q5 is turned on, the ac voltage is in a positive half cycle, and when the switching tube Q6 is turned on, a negative half cycle of the ac voltage;
when the driving signal is low, the switching tube Q5 and the switching tube Q6 are both turned off, and when the voltage is in a positive half cycle, the C-phase upper bridge arm diode D5 is turned on; when the voltage is negative for half a cycle, the C-phase lower arm diode D6 is turned on.
In the embodiment of the invention, the three-phase neutral-line-free power factor correction circuit based on the server data center comprises an A-phase power factor correction circuit, a B-phase power factor correction circuit and a C-phase power factor correction circuit, so that the maximum voltage borne by a switching tube is half of the bus voltage, the voltage output level is increased, the harmonic content is smaller, the switching frequency is higher and lower on the premise of the same harmonic content, and the efficiency is improved.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a schematic diagram of a three-phase neutral-less PFC circuit of a server-based data center according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a three-phase neutral-less power factor correction circuit based on a server data center according to a second embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are merely for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.
Fig. 1 is a schematic diagram of a three-phase neutral-less power factor correction circuit based on a server data center according to an embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown in the diagram.
The three-phase neutral-line-free power factor correction circuit based on the server data center comprises an A-phase power factor correction circuit, a B-phase power factor correction circuit and a C-phase power factor correction circuit;
the A-phase power factor correction circuit is connected with an A-phase voltage input end through a Boost inductor L1, the other end of the Boost inductor L1 is connected with a first switch tube group in series, the other end of the first switch tube group is connected with an equivalent capacitor C1 through a node Midpoint, the other end of the equivalent capacitor C1 is connected with a level VDC + point, a bus line led out by the node Midpoint is connected with the equivalent resistor C2 in series and then is connected with the level VDC-point, a first circuit node 1 is arranged on a line between the Boost inductor L1 and the first switch tube group, a line led out by the first circuit node 1 is connected with a diode D1 in series and then is connected with the level VDC + point, and the other line led out by the first circuit node 1 is connected with a diode D2 in series and then is connected with the level VDC-point;
the B-phase power factor correction circuit is connected with a B-phase voltage input end through a Boost inductor L2, the other end of the Boost inductor L2 is connected in series with a second switch tube group, the other end of the second switch tube group is converged to the node Midpoint, a second circuit node 2 is arranged on a circuit between the Boost inductor L2 and the second switch tube group, a circuit led out from the second circuit node 2 is connected in series with a diode D3 and then is connected with the level VDC + point, and another circuit led out from the second circuit node 2 is connected with the level VDC-point after being connected in series with a diode D4;
the C-phase power factor correction circuit is connected with a C-phase voltage input end through a Boost inductor L3, the other end of the Boost inductor L3 is connected with a third switching tube group in series, the other end of the third switching tube group is converged to the node Midpoint, a third circuit node 3 is arranged on a circuit between the Boost inductor L3 and the third switching tube group, a circuit led out from the third circuit node 4 is connected with the level VDC + point after being connected with a diode D5 in series, and another circuit led out from the third circuit node 4 is connected with the level VDC-point after being connected with a diode D6 in series.
In this embodiment, as shown in fig. 2, the first switching tube group includes a switching tube Q1 with an anti-parallel diode and a switching tube Q2 with an anti-parallel diode connected in series;
the grid electrodes of the switching tube Q1 with the anti-parallel diode and the switching tube Q2 with the anti-parallel diode are respectively connected with two static contacts of a switch S1;
the second switch tube group comprises a switch tube Q3 with an anti-parallel diode and a switch tube Q4 with an anti-parallel diode which are sequentially connected in series;
the grid electrodes of the switching tube Q3 with the anti-parallel diode and the switching tube Q4 with the anti-parallel diode are respectively connected with two static contacts of a switch S2;
the third switching tube group comprises a switching tube Q5 with an anti-parallel diode and a switching tube Q6 with an anti-parallel diode which are sequentially connected in series;
the gates of the switch tube Q5 with the anti-parallel diode and the switch tube Q6 with the anti-parallel diode are respectively connected with two static contacts of the switch S3.
In the embodiment of the invention, shown in combination with fig. 1 and 2:
in the A-phase power factor correction circuit, when a driving signal is high, a switching tube Q1 is conducted or a switching tube Q2 is conducted, when the switching tube Q1 is conducted, the alternating current voltage is in a positive half cycle, and when the switching tube Q2 is conducted, the negative half cycle of the alternating current voltage is;
when the driving signal is low, the switching tube Q1 and the switching tube Q2 are both turned off, and when the voltage is in a positive half cycle, the A-phase upper bridge arm diode D1 is turned on; when the voltage is negative for half a cycle, the A-phase lower bridge arm diode D2 is conducted;
in the B-phase power factor correction circuit, when a driving signal is high, a switching tube Q3 is conducted or a switching tube Q4 is conducted, when the switching tube Q3 is conducted, the alternating current voltage is in a positive half cycle, and when the switching tube Q4 is conducted, the negative half cycle of the alternating current voltage is;
when the driving signal is low, the switching tube Q3 and the switching tube Q4 are both turned off, and when the voltage is in a positive half cycle, the B-phase upper bridge arm diode D3 is turned on; when the voltage is negative for half a cycle, the B-phase lower bridge arm diode D4 is conducted;
in the C-phase power factor correction circuit, when the driving signal is high, the switching tube Q5 is turned on or the switching tube Q6 is turned on, when the switching tube Q5 is turned on, the ac voltage is in the positive half cycle, and when the switching tube Q6 is turned on, the negative half cycle of the ac voltage;
when the driving signal is low, the switching tube Q5 and the switching tube Q6 are both turned off, and when the voltage is in a positive half cycle, the C-phase upper bridge arm diode D5 is turned on; when the voltage is negative for half a cycle, the C-phase lower arm diode D6 is turned on.
In the embodiment of the invention, as shown in fig. 1 and fig. 2, a control block diagram of a three-phase three-level power factor correction circuit is shown in the following figures, double-loop control of a voltage outer loop and a current inner loop is adopted, and the voltage loop obtains stable direct-current bus voltage for a post-stage circuit; the current loop obtains input current close to sine, and the requirements of THD and PF are met.
Specifically, the error between the bus voltage set value Vref and the actual value (E1+ E2) is multiplied by the input voltage waveform after passing through the voltage controller, and the multiplied voltage waveform is used as the ac current set value; after the error between the set value and the actual value of the alternating current passes through the current controller, the conduction time and sequence of the switching tube are controlled through high-frequency triangular wave modulation, namely, the current flowing through the switching tube and the diode is controlled, and the proper bus voltage and the proper alternating input current are obtained through the closed-loop control. The controllers of the voltage outer ring and the current outer ring adopt PI regulators, and the zero pole of the controller can be regulated according to requirements.
In the embodiment of the invention, the maximum voltage borne by the switching tube after the single-phase power factor correction circuit is changed into the three-phase power factor correction circuit is only half of the bus voltage; the voltage output level is increased, the harmonic content is reduced, and the harmonic content is closer to a sine wave; dv/dt is reduced, electromagnetic interference is reduced; under the same harmonic content, the switching frequency is reduced, and the efficiency is improved. Under the same Boost inductance, the input ripple current is smaller than that of a single-phase power factor correction circuit, that is, when the inductance is designed according to certain ripple requirements, the inductance of three levels can be designed to be smaller. Because the condition of capacitor direct connection does not exist, switch dead time does not need to be set between the capacitors, and the design of a control circuit and a driving circuit is simplified.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (7)
1. A three-phase neutral-line-free power factor correction circuit based on a server data center is characterized by comprising an A-phase power factor correction circuit, a B-phase power factor correction circuit and a C-phase power factor correction circuit;
the A-phase power factor correction circuit is connected with an A-phase voltage input end through a Boost inductor L1, the other end of the Boost inductor L1 is connected with a first switch tube group in series, the other end of the first switch tube group is connected with an equivalent capacitor C1 through a node Midpoint, the other end of the equivalent capacitor C1 is connected with a level VDC + point, a bus line led out by the node Midpoint is connected with the equivalent resistor C2 in series and then is connected with the level VDC-point, a first circuit node is arranged on a line between the Boost inductor L1 and the first switch tube group, a line led out by the first circuit node is connected with a diode D1 in series and then is connected with the level VDC + point, and another line led out by the first circuit node is connected with a diode D2 in series and then is connected with the level VDC-point;
the B-phase power factor correction circuit is connected with a B-phase voltage input end through a Boost inductor L2, the other end of the Boost inductor L2 is connected with a second switch tube group in series, the other end of the second switch tube group is converged to the node Midpoint, a second circuit node is arranged on a circuit between the Boost inductor L2 and the second switch tube group, a circuit led out from the second circuit node is connected with the level VDC + point after being connected with a diode D3 in series, and the second circuit node is connected with the level VDC-point after being led out from the other circuit and connected with a diode D4 in series;
the C-phase power factor correction circuit is connected with a C-phase voltage input end through a Boost inductor L3, the other end of the Boost inductor L3 is connected with a third switching tube group in series, the other end of the third switching tube group is converged to the node Midpoint, a third circuit node is arranged on a circuit between the Boost inductor L3 and the third switching tube group, a circuit led out from the third circuit node is connected with the level VDC + point after being connected with a diode D5 in series, and the other circuit led out from the third circuit node is connected with the level VDC-point after being connected with a diode D6 in series.
2. The three-phase neutral-less power factor correction circuit based on the server data center of claim 1, wherein the first switch tube group comprises a switch tube Q1 with an anti-parallel diode and a switch tube Q2 with an anti-parallel diode which are connected in series in sequence;
the gates of the switch tube Q1 with the anti-parallel diode and the switch tube Q2 with the anti-parallel diode are respectively connected with two static contacts of the switch S1.
3. The three-phase neutral-less power factor correction circuit based on the server data center of claim 2, wherein in the A-phase power factor correction circuit, when the driving signal is high, the switch Q1 is turned on or the switch Q2 is turned on, when the switch Q1 is turned on, the AC voltage is in a positive half cycle, when the switch Q2 is turned on, the negative half cycle of the AC voltage is;
when the driving signal is low, the switching tube Q1 and the switching tube Q2 are both turned off, and when the voltage is in a positive half cycle, the A-phase upper bridge arm diode D1 is turned on; when the voltage is negative for half a cycle, the a-phase lower arm diode D2 is turned on.
4. The three-phase neutral-less power factor correction circuit based on the server data center of claim 1, wherein the second switch tube group comprises a switch tube Q3 with an anti-parallel diode and a switch tube Q4 with an anti-parallel diode which are connected in series in sequence;
the gates of the switch tube Q3 with the anti-parallel diode and the switch tube Q4 with the anti-parallel diode are respectively connected with two static contacts of the switch S2.
5. The three-phase neutral-less power factor correction circuit based on the server data center of claim 4, wherein in the B-phase power factor correction circuit, when the driving signal is high, the switch Q3 is turned on or the switch Q4 is turned on, when the switch Q3 is turned on, the AC voltage is in a positive half cycle, when the switch Q4 is turned on, the negative half cycle of the AC voltage is;
when the driving signal is low, the switching tube Q3 and the switching tube Q4 are both turned off, and when the voltage is in a positive half cycle, the B-phase upper bridge arm diode D3 is turned on; when the voltage is negative for half a cycle, the B-phase lower arm diode D4 is turned on.
6. The three-phase centerless power factor correction circuit based on the server data center as claimed in claim 1, wherein the third switch tube group comprises a switch tube Q5 with anti-parallel diode and a switch tube Q6 with anti-parallel diode connected in series in sequence;
the gates of the switch tube Q5 with the anti-parallel diode and the switch tube Q6 with the anti-parallel diode are respectively connected with two static contacts of the switch S3.
7. The three-phase neutral-less power factor correction circuit based on the server data center of claim 6, wherein in the C-phase power factor correction circuit, when the driving signal is high, the switch Q5 is turned on or the switch Q6 is turned on, when the switch Q5 is turned on, the AC voltage is in a positive half cycle, when the switch Q6 is turned on, the negative half cycle of the AC voltage is;
when the driving signal is low, the switching tube Q5 and the switching tube Q6 are both turned off, and when the voltage is in a positive half cycle, the C-phase upper bridge arm diode D5 is turned on; when the voltage is negative for half a cycle, the C-phase lower arm diode D6 is turned on.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010660748.XA CN111934531A (en) | 2020-07-10 | 2020-07-10 | Three-phase neutral-line-free power factor correction circuit based on server data center |
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| CN202010660748.XA CN111934531A (en) | 2020-07-10 | 2020-07-10 | Three-phase neutral-line-free power factor correction circuit based on server data center |
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