CN111916539B - Front-mounted integrated unit diode chip - Google Patents
Front-mounted integrated unit diode chip Download PDFInfo
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- CN111916539B CN111916539B CN201910379235.9A CN201910379235A CN111916539B CN 111916539 B CN111916539 B CN 111916539B CN 201910379235 A CN201910379235 A CN 201910379235A CN 111916539 B CN111916539 B CN 111916539B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
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Abstract
The invention provides a forward integrated unit diode chip, which comprises a first conductive type electrode, a second conductive type electrode and a diode mesa structure positioned between the first conductive type electrode and the second conductive type electrode; the diode mesa structure comprises n diode units, wherein n is more than or equal to 2. The n diode units comprise a quantum well active region positioned on the first conduction type layer, a second conduction type layer positioned on the quantum well active region, an insulating medium layer positioned on the first conduction type layer and partially covering the second conduction type layer, and a transparent electrode positioned on the second conduction type layer and partially covering the insulating medium layer, wherein the second conduction type electrode is positioned on the insulating medium layer and partially covers the transparent electrode. The invention solves the problems that the thickness of the transparent electrode limits the transverse diffusion of current and the luminous efficiency of the LED in the prior art, improves the lumen output of the unit diode chip per unit area and reduces the lumen cost.
Description
Technical Field
The invention relates to the field of semiconductor material and device process, in particular to a semiconductor photoelectric device.
Background
The conventional forward-mounted integrated unit diode chip has uneven current diffusion, which causes the loss of luminous efficiency, the heat dissipation of the diode unit diode chip under the existing structure is realized by a sapphire substrate, and the heat dissipation is poor, so that the efficiency and the stability of the unit diode chip are influenced, therefore, the main application field of the forward-mounted light-emitting diode unit diode chip is the market of medium-small power unit diode chips below 0.5 watt, and the forward-mounted light-emitting diode chip cannot provide a product with high lumen output per unit area. The non-uniformity of current diffusion, the non-uniformity of heat diffusion and the non-uniformity of light extraction cause the LED to have great limitations on three important parameters of lumen efficiency, lumen density output and lumen cost, and the current integral diode technology on the market cannot provide an effective solution.
One prior art is U.S. patent application publication No. US6614056B1, shown in fig. 1, 21/23 being an N-type electrode and 19/20ab being a P-type electrode. The mechanism of current diffusion is as follows: and after the ITO (indium tin oxide) and the p-GaN form ohmic contact, 19/20ab metal is deposited on the ITO, holes are diffused to the p-GaN in an electrode wire mode and reach the quantum well active region, and electrons diffused from the quantum well active region and the 21/22N-type electrode are radiated and recombined to emit light, so that the light-emitting LED device is obtained. By adopting ITO transparent conductive ohmic contact and a current diffusion mode of a metal lead, the total current diffusion is very uneven because the ITO resistivity is high and the conductivity of the p-type GaN material is poor. And considering the problem of absorption of light by ITO, the thickness of the ITO layer cannot be too large, which also limits the overall current spreading. In addition, because the current diffusion length of the LED unit diode chip is inversely proportional to the square root of the current density, the current diffusion length is shorter under the injection of large current, so that the current diffusion of the unit diode chip is more uneven, the efficiency is lower, and the heat dissipation is more difficult.
Non-uniformity in current spreading of the diode chip of the forward integrated unit results in a loss of luminous efficiency. The heat dissipation of the diode unit diode chip under the existing structure is realized by the sapphire substrate, and the heat dissipation is poor, so that the efficiency and the stability of the diode unit chip are affected, and therefore, the main application field of the normally installed light emitting diode unit chip is the market of medium and small power unit diode chips below 0.5 watt, and a product with high lumen output per unit area cannot be provided. The non-uniformity of current diffusion, the non-uniformity of heat diffusion and the non-uniformity of light extraction cause the current to have great limitations on three important parameters of lumen efficiency, lumen density output and lumen cost, and the forward-mounted light-emitting diode technology in the current market cannot provide an effective solution.
Second prior art conference paper of SPIE Vol.10021100210X-12016, as shown in FIG. 2, the near-field analysis diagram (upper) and the normalized current distribution diagram (lower) on the middle line of the LED chip being mounted, the size of the chip is 1.2mm × 1.2 mm. Near field analysis chartThe light intensity distribution in (1) is proportional to the distribution of current spreading. It can be seen that the concentration is 7A/cm2When the current is small, the current density in some edge regions is less than 80% of that in the middle region, and when the current is increased by 70A/cm2By this time, the current density in some regions of the edge is less than even 50% of the middle region. Therefore, the luminous efficiency, heat dissipation and stability of the LED under high current are severely limited.
The thickness of a transparent conductive film ITO (transparent electrode) in the current LED design is generally about 60-120 nanometers, and the thicker ITO absorbs light more, so that the light emitting efficiency of the LED is reduced. And the thinner the ITO thickness is, the larger the sheet resistance is, resulting in the poorer lateral current spreading efficiency. Therefore, the thickness of ITO in the existing LED design is usually limited to a process window of 60-120 nm.
Disclosure of Invention
The invention provides a forward-mounted integrated unit diode chip with small unit size and thin transparent electrode, aiming at solving the problem that the thickness of the transparent electrode has overlarge influence on the light-emitting efficiency and current diffusion of an LED chip in the prior art.
To achieve the above object, the present invention provides a forward integrated unit diode chip, comprising: a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure between the first conductivity type electrode and the second conductivity type electrode; the diode mesa structure comprises n diode units, wherein the n diode units are arranged in a geometric shape, n is more than or equal to 2, and the mesa structure area is determined according to the current diffusion length;
the n diode units comprise an insulating medium layer, a transparent electrode, a first conduction type layer, a first conduction type electrode, a second conduction type layer and a second conduction type electrode, wherein the second conduction type electrode and the quantum well active region are positioned on the first conduction type layer, the second conduction type layer is positioned on the quantum well active region, the insulating medium layer is positioned on the first conduction type layer and partially covers the second conduction type layer, the transparent electrode is positioned on the second conduction type layer and partially covers the insulating medium layer, and the second conduction type electrode is positioned on the insulating medium layer and partially covers the transparent electrode.
Preferably, the second conductive type electrode, the transparent electrode and the second conductive type layer are not connected in the vertical direction; and the insulating medium layer partially covering the second conductive type layer is a current blocking layer.
Preferably, the diode mesa structure includes a trench structure, and the trench structure is located between the diode cells.
Preferably, the thickness of the transparent electrode is 60 to 120 nanometers, or 1 to 60 nanometers.
Preferably, the diode mesa structure includes a first conductive type pad and a second conductive type pad, the first conductive type electrode is connected to the first conductive type pad, and the second conductive type electrode is connected to the second conductive type pad.
Preferably, the insulating medium layer partially covers the second conductive type layer to form a first contact surface; the transparent electrode covers the insulating medium layer to form a second contact surface; the second conductive type electrode partially covers the transparent electrode to form a third contact surface.
Preferably, the first contact surface area is greater than the third contact surface area.
Preferably, the first contact surface area is 0.001 micrometers × 0.001 micrometers to 200 micrometers × 200 micrometers; the area of the second contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer; the area of the third contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer.
Preferably, the first contact surface longitudinal length is greater than the third contact surface longitudinal length.
Preferably, the longitudinal length of the first contact surface is 0.001 to 200 micrometers; the longitudinal length of the second contact surface is 0.001-200 microns; the longitudinal length of the third contact surface is 0.001-200 microns.
Preferably, the diode mesa structure includes a line-type electrode line; the line type electrode lines include a first conductive type electrode line and a second conductive type electrode line.
Preferably, the first conductive type electrode is connected to the first conductive type pad and the first conductive type electrode line, and the second conductive type electrode is connected to the second conductive type pad by the second conductive type electrode line.
Preferably, the line-type electrode line is an inter-diode-unit electrode connecting line.
Preferably, the insulating dielectric layer material is silicon dioxide, aluminum oxide, silicon nitride.
Preferably, the diode unit is connected in a manner that: parallel connection, series connection or series-parallel connection mixing with set proportion.
Preferably, the diode unit is shaped as follows: triangle, square, rectangle, pentagon, hexagon, circle, arbitrary self-defined shape.
Preferably, the number of the diode units is 2 to 1000 hundred million.
Preferably, the length of the diode unit along the Y-axis direction is 0.001-200 microns.
Preferably, the width of the line-type electrode line is 0.001 to 20 micrometers, and the thickness of the line-type electrode line is 0.001 to 10 micrometers.
Preferably, the layout mode of the line-type electrode lines is as follows: more than 1 first conductive type electrode wires surround the layout of the table top; or more than 1 second conductive type electrode wires surround the mesa layout; or the first conductive type electrode wires and the second conductive type electrode wires are distributed in equal quantity; or the first type electrode wires and the second type electrode wires are parallel and are in insulated overlapping layout in a vertical space, and insulating medium materials are arranged between the overlapping parts of the electrode wires with different conductive types; or the first conductive type electrode wires and the second conductive type electrode wires are in insulated vertical crossing layout, and insulating medium materials are arranged between crossing parts of the different conductive type electrode wires; or the first conductive type electrode wire and the second conductive type electrode wire are partially or completely designed in a non-linear layout;
preferably, the non-linear layout includes a polygonal line layout and a curved line layout.
Preferably, the line-shaped electrode wire is made of a line-shaped metal and/or an indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.
Preferably, the diode mesa structure comprises a hole structure.
Preferably, an intrinsic gallium nitride layer is arranged between the diode mesa structure and the substrate.
Preferably, the substrate is located on a mirror.
Preferably, the mirror material is silver, aluminum or a distributed bragg mirror. Preferably, the cross-sectional shape of the trench in the diode mesa structure is triangular, quadrilateral, arc, or any other defined shape.
The forward-mounted integrated unit diode chip adopted by the invention breaks through the limitation of the existing forward-mounted LED technology in three aspects of light, electricity and heat through the nanometer-micron size structure effect. The area of the first contact surface is larger than that of the third contact surface, and the longitudinal length of the first contact surface is larger than that of the third contact surface, so that the current blocking layer can spatially separate the current diffusion of the second conduction type electrode and the second conduction type layer in the vertical direction. The reduction of the size of the integrated unit diode chip brings larger side wall heat dissipation area, has better heat dissipation performance, and can allow the injection of super-large current density without influencing the stability of the integrated unit diode chip. The thickness of the transparent electrode is less than 60 nanometers, and the light absorption capacity is weak, so that the light emitting efficiency of the LED is improved, and the bottleneck of the thickness of the transparent electrode in the prior art is solved. The size design of the unit diode chip is controlled within the current diffusion length, and the geometric optimization design mode with higher degree of freedom can simultaneously solve the problem of uneven current diffusion of an n-electrode and a p-electrode which troubles the design of the LED unit diode chip, thereby obtaining higher photoelectric conversion efficiency/lumen efficiency; the nano-micro structure of each diode unit and the hole structure in the table top can increase the light-emitting area of the side wall, so that the light extraction efficiency is improved.
Drawings
Fig. 1 is a diagram of a prior art diode cell structure.
Fig. 2 is a structure diagram of a diode cell of the prior art.
Fig. 3 is a top view of a diode chip of a forward-mounted integrated unit according to an embodiment of the invention.
Fig. 4 is a top view of a diode chip of a forward-mounted integrated unit according to a second embodiment of the present invention.
Fig. 5 is a top view of a diode chip of a forward-mounted integrated unit according to a third embodiment of the present invention.
Fig. 6 is a schematic diagram of a diode unit in a mesa structure of a forward integrated unit diode chip according to the present invention.
Fig. 7 is a partial three-dimensional view of a mesa structure of a forward integrated unit diode chip provided by the present invention.
The semiconductor device comprises a first conduction type electrode 1, a second conduction type electrode 2, a transparent electrode 3, an insulating medium layer 4, a second conduction type layer 5, a quantum well active region (MQWs)6, a first conduction type layer 7, an intrinsic gallium nitride layer 8, a substrate 9, a reflector 10, a first conduction type bonding pad 11, a second conduction type bonding pad 12, a first conduction type electrode wire 13, a second conduction type electrode wire 14, a mesa structure 15, a diode unit 16 and a groove structure 17.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of the present invention.
In view of the great limitations of the three important parameters of the existing diode structure, namely, the lumen efficiency, the lumen density output and the lumen cost, the embodiment of the invention provides a forward-mounted integrated unit diode with high lumen efficiency and high lumen density output, and the invention is described in detail below with reference to the attached drawings.
A forward integrated cell diode chip comprising: a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure between the first conductivity type electrode and the second conductivity type electrode; the diode mesa structure comprises n diode units which are arranged in a geometric shape, wherein n is larger than or equal to 2, and the area of the mesa structure is determined according to the current diffusion length.
The n diode units comprise an insulating medium layer, a transparent electrode, a first conduction type layer, a first conduction type electrode, a second conduction type layer and a second conduction type electrode, wherein the second conduction type electrode and the quantum well active region are positioned on the first conduction type layer, the second conduction type layer is positioned on the quantum well active region, the insulating medium layer is positioned on the first conduction type layer and partially covers the second conduction type layer, the transparent electrode is positioned on the second conduction type layer and partially covers the insulating medium layer, and the second conduction type electrode is positioned on the insulating medium layer and partially covers the transparent electrode. The second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the vertical direction; and the insulating medium layer partially covering the second conductive type layer is a current blocking layer.
The diode mesa structure comprises a groove structure, the groove structure is located between the diode units, the diode mesa structure further comprises a first conduction type bonding pad and a second conduction type bonding pad, the first conduction type electrode is connected with the first conduction type bonding pad, and the second conduction type electrode is connected with the second conduction type bonding pad. The diode mesa structure also comprises a line-shaped electrode wire, the width of the line-shaped electrode wire is 0.001-20 microns, and the thickness of the line-shaped electrode wire is 0.001-10 microns. The line-type electrode wire comprises a first conductive type electrode wire and a second conductive type electrode wire, the first conductive type electrode is connected with the first conductive type welding disc and the first conductive type electrode wire, and the second conductive type electrode is connected with the second conductive type welding disc through the second conductive type electrode wire. The line-type electrode wire is an electrode connecting wire between the diode units. The first conductive type electrode is an n-type electrode, the second conductive type electrode is a p-type electrode, the first conductive type bonding pad is an n-type bonding pad, the second conductive type electrode is a p-type bonding pad, the first conductive type electrode wire is an n-type electrode wire, the second conductive type electrode wire is a p-type electrode wire, the first conductive type layer is an n-GaN layer, and the second conductive type layer is a p-GaN layer.
The layout mode of the linear electrode wires is as follows: more than 1 first conductive type electrode wires surround the layout of the table top; or more than 1 second conductive type electrode wires surround the mesa layout; or the first conductive type electrode wires and the second conductive type electrode wires are distributed in equal quantity; or the first type electrode wires and the second type electrode wires are parallel and are in insulated overlapping layout in a vertical space, and insulating medium materials are arranged between the overlapping parts of the electrode wires with different conductive types; or the first conductive type electrode wires and the second conductive type electrode wires are in insulated vertical crossing layout, and insulating medium materials are arranged between crossing parts of the different conductive type electrode wires; or the first conductive type electrode wire and the second conductive type electrode wire are partially or completely designed in a non-linear layout; the non-linear layout includes a broken line layout and a curve layout. The line-shaped electrode wire is made of line-shaped metal and/or indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.
The insulating dielectric layer partially covers the second conductive type layer to form a first contact surface. The transparent electrode covers the insulating medium layer to form a second contact surface. The second conductive type electrode partially covers the transparent electrode to form a third contact surface. The first contact surface area, the second contact surface area and the third contact surface area are different in size or partially equal in size, and the first contact surface area is larger than the third contact surface area. The first contact surface area is 0.001 micrometer x 0.001 micrometer to 200 micrometer x 200 micrometer, the second contact surface area is 0.001 micrometer x 0.001 micrometer to 200 micrometer x 200 micrometer, and the third contact surface area is 0.001 micrometer x 0.001 micrometer to 200 micrometer x 200 micrometer. The longitudinal length of the first contact surface, the longitudinal length of the second contact surface and the longitudinal length of the third contact surface are different or partially equal, and the longitudinal length of the first contact surface is greater than the longitudinal length of the third contact surface. The longitudinal length of the first contact surface is 0.001-200 micrometers, the longitudinal length of the second contact surface is 0.001-200 micrometers, and the longitudinal length of the third contact surface is 0.001-200 micrometers.
The thickness of the transparent electrode is 60-120 nm, or 1-60 nm, and the insulating dielectric layer is made of silicon dioxide, aluminum oxide, and silicon nitride.
The connection mode of the diode unit is as follows: parallel connection, series connection or series-parallel connection mixing with set proportion. The diode unit shape is: triangle, square, rectangle, pentagon, hexagon, circle, arbitrary self-defined shape. The number of the diode units is 2-1000 hundred million. The length of the diode unit along the Y-axis direction is 0.001-200 microns.
The diode mesa structure comprises a hole structure, an intrinsic gallium nitride layer is arranged between the diode mesa structure and a substrate, the substrate is positioned on a reflector, and the reflector is made of silver, aluminum or a distributed Bragg reflector.
Example 1
The present embodiment provides a forward integrated unit diode chip, as shown in fig. 3, including: n-type electrode 1, n-type pad 11, p-type pad 12, n-type electrode line 13, p-type electrode line 14, diode mesa 15, diode cell 16, and trench 17. The diode mesa structure includes 6 rows of a total of 52 equally sized and evenly distributed square diode cells 16 having a length of 40 microns along the Y-axis. The diode mesa structure is arranged in a square shape, and the size of the mesa structure is smaller than the diffusion length of current injection. The diode units are in a shape of a positive rectangle and are distributed according to uniform symmetrical arrangement.
In some preferred embodiments, the diode cell has a length of 100 nanometers along the Y-axis; in other preferred embodiments, the diode cell has a length of 10 nanometers along the Y-axis.
The first conductive type electrode wires 13 and the second conductive type electrode wires 14 are line type electrode wires, the width of the line type electrode wires is 0.001-20 micrometers, the thickness of the line type electrode wires is 0.001-10 micrometers, the electrode wires are made of indium tin oxide materials, and the line type electrode wires are designed in a straight line layout mode. The first conductive type bonding pad 11 and the second conductive type bonding pad 12 are in the shape of an arc-shaped irregular polygon, the number of the bonding pads is 1, and the bonding pads are located on the edge of the mesa structure. The grooves 17 are cross-shaped, have a rectangular cross section and are uniformly distributed in the horizontal direction.
As shown in fig. 6, the n diode units in the diode mesa structure comprise an n-type pad 11, a p-type electrode 2, a transparent electrode 3, an insulating medium layer 4, an n-GaN layer 7, a p-GaN layer 5 and a quantum well active region 6. The p-type electrode 2 and the quantum well active region 6 are located on the n-GaN layer 7, the p-GaN layer 5 is located on the quantum well active region 6, the insulating medium layer 4 is located on the n-GaN layer 7 and partially covers the p-GaN layer 5, the transparent electrode 3 is located on the p-GaN layer 5 and partially covers the insulating medium layer 4, and the p-type electrode 2 is located on the insulating medium layer 4 and partially covers the transparent electrode 3.
As shown in FIG. 7, the insulating medium layer 4 partially covers the p-GaN layer 5 to form a first contact surface, the transparent electrode 3 covers the insulating medium layer 4 to form a second contact surface, and the p-type electrode 2 partially covers the transparent electrode 3 to form a third contact surface. The insulating medium layer partially covering the p-GaN layer is a current blocking layer, and the current blocking layer completely blocks current diffusion of the p-type electrode 2, the transparent electrode 3 and the p-GaN layer in the vertical direction in space due to the fact that the area of the first contact surface is larger than that of the third contact surface and the longitudinal length of the first contact surface is larger than that of the third contact surface.
In some preferred embodiments, the first contact surface area is 20 microns by 20 microns, and the first contact surface longitudinal length is 20 microns; the second contact surface area is 15 microns by 15 microns, and the longitudinal length of the second contact surface is 15 microns; the third contact surface area is 10 microns by 10 microns and the third contact surface longitudinal length is 10 microns.
In other preferred embodiments, the first contact surface area is 10 microns by 10 microns and the first contact surface longitudinal length is 10 microns; the area of the second contact surface is 8 micrometers multiplied by 8 micrometers, and the longitudinal length of the second contact surface is 8 micrometers; the third contact surface area is 5 microns by 5 microns and the third contact surface longitudinal length is 5 microns.
Example 2
The present embodiment provides a forward integrated unit diode chip, as shown in fig. 4, including: a first-conductivity-type electrode 1, a first-conductivity-type pad 11, a second-conductivity-type pad 12, a first-conductivity-type electrode line 13, a second-conductivity-type electrode line 14, a diode mesa structure 15, a diode cell 16, and a trench 17. The diode mesa structure includes a total of 6 rows of 102 equally sized uniformly distributed triangular diode cells 16 having a length of 80 microns along the Y-axis. The diode mesa structure is arranged in a triangle, and the size of the mesa structure is smaller than the diffusion length of current injection. The diode units are triangular and are distributed according to uniform symmetrical arrangement.
In some preferred embodiments, the diode cells are 100 microns long in the Y-axis direction; in other preferred embodiments, the diode cells are 10 microns long along the Y-axis; in other preferred embodiments, the diode cell has a length of 1 micron along the Y-axis.
The first conductive type electrode wires 13 and the second conductive type electrode wires 14 are line type electrode wires, the width of the line type electrode wires is 0.001-20 micrometers, the thickness of the line type electrode wires is 0.001-10 micrometers, the electrode wires are made of indium tin oxide materials, and the line type electrode wires are designed in a straight line layout mode. The first conductive type bonding pad 11 and the second conductive type bonding pad 12 are in the shape of an arc-shaped irregular polygon, the number of the bonding pads is 1, and the bonding pads are located on the edge of the mesa structure. The grooves 17 are cross-shaped, have a rectangular cross section and are uniformly distributed in the horizontal direction. As shown in fig. 4, each diode unit is additionally provided with a pore structure, the pore structure comprises 1 pore unit, and the diameter of each pore unit is 1 nm-20 microns. The hole units are arranged symmetrically, asymmetrically, periodically, non-periodically or randomly. The cell shape may also be triangular, square, rectangular, pentagonal, hexagonal, circular, and any other arbitrarily defined shape, and is not limited to the shape shown in fig. 4.
As shown in fig. 6, the n diode units in the diode mesa structure include a first conductive type pad 11, a second conductive type electrode 2, a transparent electrode 3, an insulating dielectric layer 4, a first conductive type layer 7, a second conductive type layer 5, and a quantum well active region 6. The second conductive type electrode 2 and the quantum well active region 6 are positioned on the first conductive type layer 7, the second conductive type layer 5 is positioned on the quantum well active region 6, the insulating medium layer 4 is positioned on the first conductive type layer 7 and partially covers the second conductive type layer 5, the transparent electrode 3 is positioned on the second conductive type layer 5 and partially covers the insulating medium layer 4, and the second conductive type electrode 2 is positioned on the insulating medium layer 4 and partially covers the transparent electrode 3. The first conduction type layer is an n-GaN layer, the second conduction type layer is a p-GaN layer, and the depth of a groove of the diode unit is from the n-GaN layer to the n-GaN layer. The insulating medium layer 4 partially covers the second conduction type layer 5 to form a first contact surface, the transparent electrode 3 covers the insulating medium layer 4 to form a second contact surface, and the second conduction type electrode 2 partially covers the transparent electrode 3 to form a third contact surface. The first contact surface area is 0.006 microns by 0.006 microns, the second contact surface area is 0.004 microns by 0.004 microns, and the third contact surface area is 0.002 microns by 0.002 microns. The first contact surface has a longitudinal length of 0.006 microns, the second contact surface has a longitudinal length of 0.004 microns, and the third contact surface has a longitudinal length of 0.002 microns.
In some preferred embodiments, the first contact surface area is 0.1 microns by 0.1 microns, and the first contact surface longitudinal length is 0.1 microns; the second contact surface area is 0.08 micrometers by 0.08 micrometers, and the second contact surface longitudinal length is 0.08 micrometers; the third contact surface area is 0.05 microns by 0.05 microns and the third contact surface longitudinal length is 0.05 microns.
In other preferred embodiments, the first contact surface area is 1 micron by 1 micron and the first contact surface longitudinal length is 1 micron; the second contact surface area is 0.8 microns by 0.8 microns, and the second contact surface longitudinal length is 0.8 microns; the third contact surface area is 0.5 microns by 0.5 microns and the third contact surface longitudinal length is 0.5 microns.
Example 3
The present embodiment provides a forward integrated unit diode chip, as shown in fig. 5, including: a first-conductivity-type electrode 1, a first-conductivity-type pad 11, a second-conductivity-type pad 12, a first-conductivity-type electrode line 13, a second-conductivity-type electrode line 14, a diode mesa structure 15, a diode cell 16, and a trench 17. The diode mesa structure includes 6 rows of a total of 52 equally sized and evenly distributed square diode cells 16 having a length of 40 microns along the Y-axis. The diode mesa structure is arranged in a square shape, and the size of the mesa structure is smaller than the diffusion length of current injection. The diode units are in a shape of a positive rectangle and are distributed according to uniform symmetrical arrangement. Each diode unit is additionally provided with a hole structure, the hole structure comprises two hole units, and the diameter of each hole unit is 1 nm-20 microns. The hole units are arranged symmetrically, asymmetrically, periodically, non-periodically or randomly. The cell shape may also be triangular, square, rectangular, pentagonal, hexagonal, circular, and any other arbitrarily defined shape, and is not limited to the shape shown in fig. 5.
The first conductive type electrode wires 13 and the second conductive type electrode wires 14 are line type electrode wires, the width of the line type electrode wires is 0.001-20 micrometers, the thickness of the line type electrode wires is 0.001-10 micrometers, the electrode wires are made of indium tin oxide materials, and the line type electrode wires are designed in a straight line layout mode. The first conductive type bonding pad 11 and the second conductive type bonding pad 12 are in the shape of an arc-shaped irregular polygon, the number of the bonding pads is 1, and the bonding pads are located on the edge of the mesa structure. The grooves 17 are cross-shaped, have a rectangular cross section and are uniformly distributed in the horizontal direction.
As shown in fig. 6, the n diode units in the diode mesa structure include a first conductive type pad 11, a second conductive type electrode 2, a transparent electrode 3, an insulating dielectric layer 4, a first conductive type layer 7, a second conductive type layer 5, and a quantum well active region 6. The second conductive type electrode 2 and the quantum well active region 6 are positioned on the first conductive type layer 7, the second conductive type layer 5 is positioned on the quantum well active region 6, the insulating medium layer 4 is positioned on the first conductive type layer 7 and partially covers the second conductive type layer 5, the transparent electrode 3 is positioned on the second conductive type layer 5 and partially covers the insulating medium layer 4, and the second conductive type electrode 2 is positioned on the insulating medium layer 4 and partially covers the transparent electrode 3. The first conduction type layer is an n-GaN layer, the second conduction type layer is a p-GaN layer, and the depth of a groove of the diode unit is from the n-GaN layer to the n-GaN layer.
The insulating medium layer 4 partially covers the second conduction type layer 5 to form a first contact surface, the transparent electrode 3 covers the insulating medium layer 4 to form a second contact surface, and the second conduction type electrode 2 partially covers the transparent electrode 3 to form a third contact surface. The first contact surface area is 0.03 microns by 0.03 microns, the second contact surface area is 0.02 microns by 0.02 microns, and the third contact surface area is 0.01 microns by 0.01 microns. The first contact surface has a longitudinal length of 0.03 microns, the second contact surface has a longitudinal length of 0.02 microns, and the third contact surface has a longitudinal length of 0.01 microns.
In some preferred embodiments, the first contact surface area is 0.06 micrometers by 0.06 micrometers, the first contact surface longitudinal length is 0.06 micrometers, and the second contact surface area is 0.04 micrometers by 0.04 micrometers; the second contact surface has a longitudinal length of 0.04 microns; the third contact surface area is 0.02 microns by 0.02 microns and the third contact surface longitudinal length is 0.02 microns.
In other preferred embodiments, the first contact surface area is 0.8 microns by 0.8 microns, the first contact surface longitudinal length is 0.8 microns, and the second contact surface area is 0.5 microns by 0.5 microns; the second contact surface has a longitudinal length of 0.5 microns; the third contact surface area is 0.3 microns by 0.3 microns and the third contact surface longitudinal length is 0.3 microns.
The conventional forward-mounted integrated unit light-emitting diode product of 0.5W has the driving current of 150mA and the driving current density of 70A/cm2Left and right. In the invention, because the size of each unit is smaller than the diffusion length of current, and the ultra-uniform current distribution design is adopted, the driving current of the normally-installed integrated unit light-emitting diode of 0.5W can be 150A/cm2In the above, each led unit can bear a current density more than 2 times that of a conventional front-mounted led product. For example, when the driving current exceeds 150mA, the voltage VF of the normally-mounted LED chip rises sharply due to the non-uniform current diffusion, and the thermal effect is very significant, so that the chip cannot bear the driving of a large current; and the driving current of the corresponding integrated unit light emitting diode chip can be increased to more than 600mA, and meanwhile, the increase of the comparison voltage VF is smaller. The integrated unit LEDs can therefore withstand current densities several times higher than the forward mounted LEDs, bringing the advantages of enormous lumen density and lumen cost.
Here exemplified with a 0.5W LED chip, the advantages of the huge lumen density and lumen cost of the integrated unit LED chip are illustrated. In addition, the point to be emphasized is that the normally installed LED chip can only be used for 0.5W output products due to the difficulty of current diffusion and heat dissipation. However, the integrated unit light emitting diode product with the same size can drive the current of more than 600mA, and actually reaches the driving power of 2W, so the lumen output of the chip can be more than 4 times of that of a forward-mounted product, and the ultrahigh lumen density output which is not possessed by the forward-mounted medium-small power LED product is realized.
The upright integrated unit diode chip provided by the embodiment of the invention has the following beneficial effects:
(1) the length design of the diode unit is controlled within the current diffusion length, the optimized geometric design with certain degree of freedom can further improve the light emitting efficiency, and the problem of uneven current diffusion of an n-type electrode and a p-type electrode which troubles the design of an LED unit diode chip can be solved, so that higher photoelectric conversion efficiency/lumen efficiency is obtained.
(2) The length of the diode unit can be far less than the current diffusion length, so that the thickness of the transparent electrode can be greatly reduced, the absorption of the transparent electrode to light is greatly reduced, and the light extraction efficiency of the chip is improved.
(3) The design of the current blocking layer structure can reduce the current aggregation and light absorption effect and improve the light emitting efficiency of the chip.
(4) The micro-nano structure of each diode unit increases the light emitting area of the side wall, so that the light extraction efficiency is improved.
(5) The size of the integrated unit diode chip is optimized, so that a larger side wall heat dissipation area is brought, the integrated unit diode chip has better heat dissipation performance, injection of super-large current density is allowed without influencing the stability of the integrated unit diode chip, the lumen output of the unit diode chip in unit area is greatly improved, and the lumen cost is reduced.
(6) The design of the integrated unit diode chip can realize ultra-uniform current injection, thereby obtaining higher efficiency, better wavelength uniformity, narrower half-height width of a light-emitting spectrum, better heat dissipation uniformity and better device stability, and the current injection uniformity is far more than about 50 percent of the current injection uniformity of the normal device.
(7) The integrated unit diode chip is suitable for LED products of various color systems such as UVC, UVA, UVB, purple light, blue light, green light, yellow light, red light, infrared light and the like, and can be used in the application fields of LED illumination, backlight, display, plant illumination, medical treatment and other semiconductor light-emitting devices.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (13)
1. A forward mounted integrated cell diode chip, comprising:
a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure between the first conductivity type electrode and the second conductivity type electrode; the diode mesa structure comprises n diode units, wherein the n diode units are arranged in a geometric shape, n is more than or equal to 2, and the mesa structure area is determined according to the current diffusion length;
the n diode units comprise an insulating medium layer, a transparent electrode, a first conduction type layer, a first conduction type electrode, a second conduction type layer and a second conduction type electrode, wherein the second conduction type electrode and the quantum well active region are positioned on the first conduction type layer;
the diode mesa structure comprises trench structures, the trench structures being located between the diode cells;
the second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the vertical direction; the insulating medium layer partially covering the second conductive type layer is a current blocking layer;
the thickness of the transparent electrode is 60-120 nm, or 1-60 nm;
the diode mesa structure comprises a first conduction type bonding pad and a second conduction type bonding pad, wherein a first conduction type electrode is connected with the first conduction type bonding pad, and a second conduction type electrode is connected with the second conduction type bonding pad; the insulating medium layer partially covers the second conductive type layer to form a first contact surface; the transparent electrode partially covers the insulating medium layer to form a second contact surface; the second conductive type electrode partially covers the transparent electrode to form a third contact surface;
the area of the first contact surface is larger than that of the third contact surface;
the area of the first contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer; the area of the second contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer; the area of the third contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer;
the first contact surface longitudinal length is greater than the third contact surface longitudinal length;
the first contact longitudinal length is between 0.001 and 200 microns; the longitudinal length of the second contact surface is 0.001-200 microns; the longitudinal length of the third contact surface is 0.001-200 microns;
the diode mesa structure comprises a line-type electrode line; the line-type electrode wires comprise a first conductive type electrode wire and a second conductive type electrode wire;
the width of the linear electrode wire is 0.001-20 microns, and the thickness of the linear electrode wire is 0.001-10 microns;
the first conductive type electrode is connected with the first conductive type bonding pad and the first conductive type electrode wire, and the second conductive type electrode is connected with the second conductive type bonding pad through the second conductive type electrode wire;
the line-type electrode wire is an electrode connecting wire between diode units.
2. The forward-mounted integrated cell diode chip of claim 1, wherein the insulating dielectric layer is made of silicon dioxide, aluminum oxide, or silicon nitride.
3. A forward mounted integrated cell diode chip as claimed in claim 1, wherein said diode cells are connected in a manner such that: parallel connection, series connection or series-parallel connection mixing with set proportion.
4. The forward integrated cell diode chip of claim 1, wherein the diode cell is shaped as: triangle, square, rectangle, pentagon, hexagon, circle.
5. A forward mounted integrated cell diode chip as claimed in claim 1, wherein said diode cells are 2 to 1000 hundred million in number.
6. The forward integrated cell diode chip of claim 1, wherein the diode cell has a length along the Y-axis of 0.001 microns to 200 microns.
7. The forward-mounted integrated cell diode chip of claim 1, wherein the line-type electrode lines are arranged in a manner that: more than 1 first conductive type electrode wires surround the layout of the table top; or more than 1 second conductive type electrode wires surround the mesa layout; or the first conductive type electrode wires and the second conductive type electrode wires are distributed in equal quantity; or the first type electrode wires and the second type electrode wires are parallel and are in insulated overlapping layout in a vertical space, and insulating medium materials are arranged between the overlapping parts of the electrode wires with different conductive types; or the first conductive type electrode wires and the second conductive type electrode wires are in insulated vertical crossing layout, and insulating medium materials are arranged between crossing parts of the different conductive type electrode wires; or the first conductive type electrode wires and the second conductive type electrode wires are partially or completely designed in a non-linear layout.
8. The forward-mounted integrated cell diode chip of claim 7, wherein the non-linear layout comprises a meander-line layout, a curved layout.
9. The forward-mounted integrated cell diode chip of claim 1, wherein the linear electrode wires are made of linear metal and/or indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.
10. The forward-mounted integrated cell diode chip of claim 1, wherein the diode mesa structure comprises a hole structure.
11. The forward-mounted integrated cell diode chip of claim 1, wherein the diode mesa and the substrate have an intrinsic gallium nitride layer therebetween.
12. A face-mounted integrated cell diode chip as claimed in claim 10 wherein the substrate is located on the mirror.
13. The forward integrated cell diode chip of claim 12, wherein the mirror material is silver, aluminum, or a distributed bragg mirror.
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| CN201911252644.9A CN110931610B (en) | 2019-05-08 | 2019-05-08 | Front-mounted integrated unit diode chip |
| CN201910379235.9A CN111916539B (en) | 2019-05-08 | 2019-05-08 | Front-mounted integrated unit diode chip |
| PCT/CN2020/089212 WO2020224643A1 (en) | 2019-05-08 | 2020-05-08 | Formal integrated unit diode chip |
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| CN111916539A (en) | 2020-11-10 |
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