CN111913038A - Multi-channel clock signal frequency detection device and method - Google Patents
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Abstract
The invention discloses a multi-channel clock signal frequency detection device, which comprises a control module, a clock switching module and a frequency detection module, wherein the control module is used for controlling the frequency of a clock signal; the control module is set to sequentially instruct the clock switching module to switch one path of the plurality of paths of clock signals into a clock signal to be detected according to preset detection configuration parameters, and store a received detection result as a detection result of the path of clock signal; the clock switching module is set to determine a path of clock signal to be detected from the accessed multiple paths of clock signals according to the indication of the control module and output the path of clock signal to the frequency detection module; the frequency detection module is configured to perform frequency detection on the input one-path clock signal and output a detection result to the control module. The invention also discloses a method for detecting the frequency of the multipath clock signals.
Description
Technical Field
The present invention relates to the field of computer technology, and more particularly, to a multi-channel clock signal frequency detection apparatus and method.
Background
The normality and stability of the chip clock source play a vital role in the chip work. The abnormal of the chip clock source may cause the performance of the chip to be degraded, and even may cause the chip not to work normally. Meanwhile, in the technical field of chip security, the attack on the chip is realized by a method for measuring and calculating the characteristics of chip power consumption and the like through the attack on a clock source. And is therefore very important for frequency detection of the clock source. In modern chip design, there are often many clock sources according to different power consumption and applications, so that frequency detection needs to be performed on the multiple clock sources.
The existing frequency detection method is generally used for detecting only one clock source, and when detecting multiple clock sources, a plurality of frequency detection modules are used.
How to effectively reduce the chip area and reduce the cost also becomes the problem to be solved in the field of multi-path clock signal detection.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention provide a device and a method for detecting a frequency of a multi-channel clock signal, where dynamic polling detection of the multi-channel clock is completed by a frequency detection module, and the device and the method have the advantages of small circuit number, small circuit area, and low cost.
The embodiment of the invention provides a multi-channel clock signal frequency detection device, which comprises,
the device comprises a control module, a clock switching module and a frequency detection module;
the control module is set to sequentially instruct the clock switching module to switch one path of the plurality of paths of clock signals into a clock signal to be detected according to preset detection configuration parameters, and store a received detection result as a detection result of the path of clock signal;
the clock switching module is set to determine a path of clock signal to be detected from the accessed multiple paths of clock signals according to the indication of the control module and output the path of clock signal to the frequency detection module;
the frequency detection module is configured to perform frequency detection on the input one-path clock signal and output a detection result to the control module.
The embodiment of the invention also provides a method for detecting the frequency of the multipath clock signals, which comprises the following steps,
according to preset detection configuration parameters, sequentially instructing a clock switching module to switch one of a plurality of paths of clock signals into a clock signal to be detected;
according to the instruction of the control module, determining one path of clock signal to be detected from the accessed multiple paths of clock signals, and outputting the clock signal to a frequency detection module;
and the frequency detection module performs frequency detection on the input one path of clock signal and outputs a detection result.
It can be seen that, in the embodiments of the present invention, one frequency detection module is shared, and clock signals of a plurality of clock sources are respectively detected in turn according to configuration, so that miniaturization and low cost of the multi-path clock detection apparatus are realized.
Drawings
Fig. 1 is a structural diagram of a multi-channel clock signal frequency detection apparatus according to an embodiment;
FIG. 2 is a flowchart illustrating operation of a control module according to an embodiment;
FIG. 3 is a flow chart of a-way clock signal detection according to one embodiment;
FIGS. 4a-4f are simulation diagrams of detection waveforms in accordance with one embodiment;
fig. 5 is a structural diagram of a multi-channel clock signal frequency detection apparatus provided in the second embodiment;
fig. 6 is a flowchart of a method for detecting frequencies of multiple clock signals according to a third embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Example one
The present embodiment takes the clock signal detection of the a-d four-way clock source shown in fig. 1 as an example.
An embodiment of the present invention provides a multi-channel clock signal frequency detection apparatus 10, which is shown in fig. 1 and includes:
the system mainly comprises a control module 101, a clock switching module 102 and a frequency detection module 103.
The control module 101 is configured to implement a control function for the clock switching module 102 and the frequency detection module 103 and a processing and storing function for the detection result.
The clock switching module 102 is configured to implement a function of selectively switching clock signals of each clock source.
The frequency detection module 103 is configured to perform frequency detection on the input clock and provide an output detection result. The control module 102 and the clock switching module complete the selective switching of the detected clock source to realize the dynamic polling detection function of the multi-channel clock source by using one frequency detection module 103.
The control module 101 is configured to control the clock switching module 102 and the frequency detection module 103 according to preset detection configuration parameters; the detecting the configuration parameters at least comprises: detection sequence and detection time. For example, in this embodiment, polling detection is performed in the order of a, b, c, and d, and the detection interval time is 25 μ sec. Those skilled in the art can preset other parameters according to the above, for example, only part of the clock signals are detected, the detection sequence or the detection time is adjusted, and the like, and the method is not limited to the exemplary embodiment.
Optionally, the apparatus for detecting a frequency of multiple clock signals further includes a self-test function, where the standard clock signal clk _ self-check is also connected to the clock switching module 102, and when the clock switching module 102 switches the standard clock signal and inputs the standard clock signal to the frequency detection module 103, the self-test of the apparatus for detecting a frequency of multiple clock signals is performed.
As shown in fig. 2, when normal detection or self-inspection is started, all clock states are closed first, and each control signal is cleared, and this step is to ensure that when the detection state is entered again soon after abnormal exit detection, the last detected clock can be completely closed and then a new detection clock path is opened, so as to prevent the detected clock from not being completely closed when abnormal exit occurs, and the new detected path is opened and overlapped. After closing, starting CLKA clock channel detection, if the CLKA clock channel detection is passed, jumping to a detection normal state, then closing the CLKA channel clock, then carrying out frequency detection on the CLKB channel according to similar steps, and carrying out polling detection on four channels of clocks in sequence. If the frequency alarm of the A-path clock signal is detected, the corresponding abnormal detection state is entered, as shown in fig. 3. If the other paths of clock signals are abnormal, the similar flow of the figure 3 is also adopted.
The self-test procedure is used to detect whether the frequency detection module 103 is normal, and input the standard detected clock signal clk _ self check, and the detection process is similar to the normal detection procedure for detecting other clock signals.
The control module 101 can realize the combined detection of each clock path, can detect the inequality of 1-path to 4-path clocks, and can be expanded. The number of the clock paths is flexible and configurable, and the combination of the clock paths is flexible and configurable. Meanwhile, the system has a self-checking function, and normal detection and self-checking can be freely switched according to preset detection configuration parameters. And the abnormal exit processing is carried out, so that the normal operation can be ensured even if the detection is carried out again after the abnormal exit. After the alarm occurs, the locking state is always kept under the condition that the system does not process the alarm, so that the safety of the chip is ensured. That is, after the alarm occurs, if the detection device does not reset the chip, the lock-up state is always maintained.
The control module 101 latches the detection result at the same time, when any path of clock frequency is abnormal, the control module stops at the abnormal state of the path, latches the detection result, and indicates the path to alarm, high-frequency alarm or low-frequency alarm, to the system through the module output path of the device. After latching, no polling detection is carried out, the chip is always kept in an alarm state, and the chip CPU stops running. Namely, the chip can not perform any operation under the abnormal condition, so that the chip information can be prevented from being obtained by attack detection. Even if the chip is in an abnormal state due to non-artificial attack, the chip should not continue to work. This function is a self-protection function after an attack.
And after the system is reset, the detection device is turned on again, so that normal detection can be started again, and if no abnormality exists, normal polling detection is started again.
The clock switching module 102 implements glitch-free switching of each clock, and since each clock has different frequencies and is a different clock domain signal, the control signal provided by the control module 101 is a system clock domain signal, and the control signal is synchronized to the clock domain of each clock path during switching and then gated, thereby implementing glitch-free switching. The control signal sent by the control module 101 to the clock switching module 102 includes a signal indicating that the clock switching module 102 closes the output of the currently detected clock signal, or a signal indicating that the clock switching module 102 opens the output of the switched new clock signal.
When the clock switch 102 receives the signal for closing the output of the clock signal currently being detected, the clock switch closes the output of the clock signal of the path after synchronizing with the clock signal currently being detected, so as to realize the integrity of the waveform of the path;
and when the clock switch 102 receives the signal for starting the new clock signal output after switching, the clock switch synchronizes with the new clock signal after switching, and then starts the output of the clock signal of the path, so as to realize the integrity of the waveform of the path.
Optionally, since the clock frequencies are different and the synchronization time and the turn-on and turn-off time are different, the turn-on and turn-off of each clock is counted. After the selected (switched) clock path is started, starting detection, that is, after the control module 101 instructs the clock switching module 102 to start a signal output by a switched new clock signal, delaying the signal according to a preset start delay count, and then starting a detection enable signal of the frequency detection module 103 to start detection; after one clock is completely turned off, the other clock is turned on, that is, after the control module 101 instructs the switching module 102 to turn off the output of the currently detected clock signal, the switching module 102 is instructed to turn on the switched new clock signal output only after the control module delays according to the preset turn-off delay count, so that the switching module starts to output the new clock signal. Therefore, the clock can be ensured to have no burr, and the clocks are not overlapped, so that the accuracy of frequency detection is ensured.
The frequency detection module 103 performs reference timing by the standard count clock clk _ reference. And counting the detected clock signal clk _ test within the standard counting time, and comparing the counting result with a standard value, wherein the standard value is divided into a maximum value and a minimum value. The frequency is considered to be lower when the frequency is smaller than the minimum standard value, the frequency is considered to be higher when the frequency is larger than the maximum standard value, and the frequency is normal when the frequency is between the minimum standard value and the maximum standard value. The result is output to the control module 101 for registration processing.
The control module 101 instructs, through the clock switching control signal shown in fig. 1, the clock switching module 102 to select one of the multiple clock signals as a clock signal to be detected, that is, a new clock signal after switching; the frequency detection module is instructed to perform frequency detection by an enable control signal shown in fig. 1. The enable control signal is the detection enable signal, when the detection enable signal is turned on, the frequency detection module 103 performs frequency detection, and when the detection enable signal is turned off, the frequency detection module 103 does not perform frequency detection.
The clock switching module 102 accesses a plurality of clock signals to be detected, and optionally, also accesses a standard clock signal for self-test, and when one of the plurality of accessed clock signals is switched as a clock signal to be detected according to an instruction of the control module 101, firstly, the output of the clock signal currently being detected is turned off, and then, a new clock signal is turned on and input to the frequency detection module as clk _ test.
In this embodiment, the simulation of the detection result is as shown in fig. 4a, and a simulation oscillogram of the frequency of the 4-way clock source is detected. Wherein fd _ en is a frequency detection module enable signal that is enabled following the enabling of each detected clock path. The clk _ ref is a standard detection clock which exists all the time, and the clk _ flt clock is a self-detection clock clk _ osciv 8_ fd and clk _ trngaj _ fd, clk _ trngbj _ fd, clk _ trngcj _ fd and clk _ trngdj _ fd. trng _ fd _ pass is a pass-through signal, it can be seen that each pass is completed and set up after passing, trng _ fd _ err is an error indication signal, trng _ fd _ channel _ err [3:0] is used to indicate which alarm is to be issued, trng _ fd _ con [3:2] is used to indicate whether a high-frequency alarm or a low-frequency alarm (the set of signals is active low and the others are not illustrated as active high), and the detection shown in fig. 4a is normal without alarm.
In the present embodiment, the timing waveform of the self-test clock signal is shown in fig. 4 b; the detection timing waveform of the a-channel signal CLKA is shown in fig. 4 c; a. the allowable waveforms when the four clock signals of b, c and d are alternately detected are shown in fig. 4 d; detecting the timing waveform of the alarm occurring in the b-channel clock signal, as shown in fig. 4e, where trng _ fd _ con is register low and active, [3] represents low frequency alarm, and [2] represents high frequency alarm; and alternately detecting a B-channel clock signal CLKB alarm timing sequence wave form chart as shown in figure 4f, wherein after alarm, the B-channel alarm signal is always existed, and the CPU is reset until the chip system is reset.
Example two
An embodiment of the present invention provides a multi-clock signal frequency detection apparatus 50, as shown in fig. 5, including,
a control module 501, a clock switching module 502 and a frequency detection module 503;
the control module 501 is configured to sequentially instruct the clock switching module to switch one of the multiple clock signals as a clock signal to be detected according to preset detection configuration parameters, and store a received detection result as a detection result of the clock signal;
the clock switching module 502 is configured to determine a path of clock signal to be detected from the accessed multiple paths of clock signals according to the instruction of the control module, and output the path of clock signal to the frequency detection module;
the frequency detection module 503 is configured to perform frequency detection on the input one path of clock signal, and output a detection result to the control module 501.
Optionally, the control module 501 is further configured to instruct the clock switching module to close the clock signal output to the frequency detection module and instruct the frequency detection module to clear the detection result before sequentially instructing the clock switching module to switch one of the multiple clock signals as the clock signal to be detected.
Optionally, the instructing, by the control module 501, the clock switching module to switch one of the multiple clock signals to be a clock signal to be detected includes:
turning off a detection enable signal of the frequency detection module; instructing the clock switching module to turn off the output of the clock signal currently being detected;
instructing the clock switching module to start the output of the switched new clock signal; and starting a detection enabling signal of the frequency detection module.
Optionally, the clock switching module 502 is further configured to, according to the received indication of closing the output of the clock signal currently being detected, close the output of the clock signal currently being detected after synchronizing with the clock domain of the clock signal currently being detected;
alternatively, the first and second electrodes may be,
the clock switching module 502 is further configured to start the output of the new clock signal after synchronizing with the clock domain of the new clock signal according to the received indication to start the output of the switched new clock signal.
Optionally, the control module 501 instructs the clock switching module to start outputting the switched new clock signal; turning on a detection enable signal of the frequency detection module, comprising:
after instructing the clock switching module 502 to start the output of the switched new clock signal, after delaying according to the start delay count corresponding to the new clock signal, starting the detection enable signal of the frequency detection module;
alternatively, the first and second electrodes may be,
the control module 501 instructs the clock switching module 502 to turn off the output of the clock signal currently being detected; instructing the clock switching module 502 to start the output of the switched new clock signal, including:
after instructing the clock switching module 502 to close the output of the currently detected clock signal, the clock switching module 502 is instructed to start the output of the switched new clock signal after delaying according to the closing delay count corresponding to the current clock signal.
Optionally, the control module 501 is further configured to, after receiving the detection result and processing the detection result according to a preset rule, latch the detection result and output alarm information when the processing result indicates that there is an abnormality.
Optionally, the control module 501 is further configured to instruct the clock switching module to switch the standard clock signal input to the clock switching module as the clock signal to be detected.
Wherein the preset detection configuration parameters at least include: detection sequence and detection time.
EXAMPLE III
An embodiment of the present invention provides a method for detecting a frequency of a multi-channel clock signal, as shown in fig. 6, including,
step 601, sequentially instructing a clock switching module to switch one of a plurality of paths of clock signals into a clock signal to be detected according to preset detection configuration parameters;
step 602, according to the instruction of the control module, determining a path of clock signal to be detected from the accessed multiple paths of clock signals, and outputting the path of clock signal to the frequency detection module;
Optionally, before step 601, the method further includes step 600, before sequentially instructing to select one of the clock signals to be detected, instructing to close the clock signal output to the frequency detection module, and instructing the frequency detection module to clear the detection result.
Optionally, in step 602, determining a path of clock signal to be detected from the accessed multiple paths of clock signals, and outputting the path of clock signal to the frequency detection module, where the method includes:
and according to the received indication, determining one path of clock signal to be detected from the accessed multi-path clock signals, and starting the determined clock signal to output to the frequency detection module after the clock signal is synchronized with the clock domain of the determined clock signal.
Optionally, the instructing, in step 601, the switching, by the clock switching module, one of the multiple clock signals to be a clock signal to be detected includes:
turning off a detection enable signal of the frequency detection module; instructing the clock switching module to turn off the output of the clock signal currently being detected;
instructing the clock switching module to start the output of the switched new clock signal; and starting a detection enabling signal of the frequency detection module.
Optionally, the step 602 includes: according to the received indication of closing the output of the clock signal currently being detected, after the indication is synchronized with the clock domain of the clock signal currently being detected, closing the output of the clock signal currently being detected;
alternatively, the first and second electrodes may be,
the step 602 includes: and according to the received indication for starting the output of the switched new clock signal, after synchronizing with the clock domain of the new clock signal, starting the output of the new clock signal.
Optionally, in step 601, the clock switching module is instructed to start outputting a new clock signal after switching; turning on a detection enable signal of the frequency detection module, comprising:
after the clock switching module is instructed to start the output of the switched new clock signal, the detection enabling signal of the frequency detection module is started after the delay is carried out according to the start delay count corresponding to the new clock signal;
alternatively, the first and second electrodes may be,
in step 601, the clock switching module is instructed to close the output of the clock signal currently being detected; instructing the clock switching module to start outputting the switched new clock signal, comprising:
and after the clock switching module is instructed to close the output of the clock signal currently detected, the clock switching module is instructed to open the output of the switched new clock signal after delaying according to the closing delay count corresponding to the current clock signal.
Optionally, the method further includes, in step 604, after receiving the detection result and processing the detection result according to a preset rule, when the processing result indicates that there is an abnormality, latching the detection result, and outputting alarm information.
Optionally, the method further includes instructing the clock switching module to switch the standard clock signal input to the clock switching module as the clock signal to be detected.
Optionally, the preset detection configuration parameters at least include: detection sequence and detection time.
The scheme provided by the embodiment of the invention realizes the dynamic polling detection of the multi-channel clock by one frequency detection module, and has the advantages of less circuit quantity, small circuit area, low cost and low power consumption. Meanwhile, the number of the detectable clock sources is flexible and configurable, and the detectable clock source paths are flexible and configurable (which paths are detected). Whether the function of the frequency detection module is normal or not can be detected, namely the self-checking function of the frequency detection module is realized, and the normal detection and the self-checking can be freely switched. And due to the exception exit processing, normal operation can be still realized by detecting again after the exception exit. And after the alarm occurs, the alarm state is output to indicate which way of alarm, high-frequency alarm or low-frequency alarm, and the locking state is always kept under the condition that the system does not process the alarm, so that the safety of the chip is ensured.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (10)
1. A multi-channel clock signal frequency detection device is characterized by comprising,
the device comprises a control module, a clock switching module and a frequency detection module;
the control module is set to sequentially instruct the clock switching module to switch one path of the plurality of paths of clock signals into a clock signal to be detected according to preset detection configuration parameters, and store a received detection result as a detection result of the path of clock signal;
the clock switching module is set to determine a path of clock signal to be detected from the accessed multiple paths of clock signals according to the indication of the control module and output the path of clock signal to the frequency detection module;
the frequency detection module is configured to perform frequency detection on the input one-path clock signal and output a detection result to the control module.
2. The apparatus of claim 1,
the control module is further configured to instruct the clock switching module to close the clock signal output to the frequency detection module and instruct the frequency detection module to empty the detection result before sequentially instructing the clock switching module to switch one of the plurality of clock signals to be the clock signal to be detected.
3. The apparatus of claim 1,
the control module instructs the clock switching module to switch one of the multiple clock signals to be the clock signal to be detected, and the method comprises the following steps:
turning off a detection enable signal of the frequency detection module; instructing the clock switching module to turn off the output of the clock signal currently being detected;
instructing the clock switching module to start the output of the switched new clock signal; and starting a detection enabling signal of the frequency detection module.
4. The apparatus of claim 3,
the clock switching module is also configured to close the output of the clock signal currently being detected after synchronizing with the clock domain of the clock signal currently being detected according to the received indication for closing the output of the clock signal currently being detected;
alternatively, the first and second electrodes may be,
the clock switching module is further configured to start the output of the new clock signal after synchronizing with the clock domain of the new clock signal according to the received indication to start the output of the switched new clock signal.
5. The apparatus of claim 3,
the control module instructs the clock switching module to start the output of the switched new clock signal; turning on a detection enable signal of the frequency detection module, comprising:
after the clock switching module is instructed to start the output of the switched new clock signal, the detection enabling signal of the frequency detection module is started after the delay is carried out according to the start delay count corresponding to the new clock signal;
alternatively, the first and second electrodes may be,
the control module instructs the clock switching module to close the output of the clock signal currently being detected; instructing the clock switching module to start outputting the switched new clock signal, comprising:
and after the clock switching module is instructed to close the output of the clock signal currently detected, the clock switching module is instructed to open the output of the switched new clock signal after delaying according to the closing delay count corresponding to the current clock signal.
6. The apparatus according to any one of claims 1 to 5,
the control module is also configured to, after receiving the detection result and processing the detection result according to a preset rule, latch the detection result and output alarm information when the processing result indicates that there is an abnormality.
7. The apparatus according to any one of claims 1 to 5,
the control module is further configured to instruct the clock switching module to switch the standard clock signal input to the clock switching module as the clock signal to be detected.
8. The apparatus according to any one of claims 1 to 5,
the preset detection configuration parameters at least comprise: detection sequence and detection time.
9. A method for detecting the frequency of multiple clock signals includes,
according to preset detection configuration parameters, sequentially instructing a clock switching module to switch one of a plurality of paths of clock signals into a clock signal to be detected;
according to the instruction of the control module, determining one path of clock signal to be detected from the accessed multiple paths of clock signals, and outputting the clock signal to a frequency detection module;
and the frequency detection module performs frequency detection on the input one path of clock signal and outputs a detection result.
10. The method of claim 9,
the indicating clock switching module switches one of the multiple clock signals to be the clock signal to be detected, and comprises:
turning off a detection enable signal of the frequency detection module; instructing the clock switching module to turn off the output of the clock signal currently being detected;
instructing the clock switching module to start the output of the switched new clock signal; and starting a detection enabling signal of the frequency detection module.
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| CN112364597A (en) * | 2020-11-26 | 2021-02-12 | 北京百瑞互联技术有限公司 | Method and device for carrying out non-inductive frequency conversion of integrated circuit and storage medium |
| CN112858780A (en) * | 2020-12-31 | 2021-05-28 | 广东大普通信技术有限公司 | Method, device and system for measuring crystal oscillation frequency |
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| CN112858780A (en) * | 2020-12-31 | 2021-05-28 | 广东大普通信技术有限公司 | Method, device and system for measuring crystal oscillation frequency |
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| CN111913038B (en) | 2023-12-19 |
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