CN111902930A - Low-temperature polycrystalline semiconductor device and method for manufacturing the same - Google Patents

Low-temperature polycrystalline semiconductor device and method for manufacturing the same Download PDF

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CN111902930A
CN111902930A CN201980021419.6A CN201980021419A CN111902930A CN 111902930 A CN111902930 A CN 111902930A CN 201980021419 A CN201980021419 A CN 201980021419A CN 111902930 A CN111902930 A CN 111902930A
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silicon layer
layer
extrinsic
type
metal oxide
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洪瑛
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Priority claimed from PCT/KR2019/002511 external-priority patent/WO2019182263A1/en
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Abstract

The present invention relates to a method for manufacturing a semiconductor device, including: a step of forming a buffer layer made of an insulating material on a substrate; a seed layer forming step of forming a seed layer made of at least one material selected from the group consisting of: NiCx-Oy, NiNxOy, NiCxNyOz, NiCxOy: H, NiNxOy: H, NiCxNyOz: H, NixSiy, and NixGey; a silicon layer forming step of forming an amorphous silicon layer on the seed layer; and a crystallization step of heat-treating the amorphous silicon layer to crystallize the amorphous silicon layer by a catalytic action of nickel.

Description

Low-temperature polycrystalline semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates to a poly MOS device and a method of manufacturing the same, and more particularly, to a CMOS using LTPSTFTs.
Background
Low temperature polysilicon thin film transistor (LTPS TFT) having high mobility and high reliability is suitable as a pixel switching device of an active-matrix organic light-emitting diode (AM-OLED) display widely used in mobile devices such as smart phones.
Excimer Laser Annealing (ELA) is mainly used for crystallization of silicon to fabricate LTPSTFT. Such LTPS TFTs have high mobility and high reliability, but a certain level of grain uniformity (crystal grain uniformity) may not be maintained in a large-area display in which a large number of TFTs are arranged.
MIC and MILC techniques, which have been extensively studied in LTPS technology, cause contamination of Ni element and leakage current in devices, and thus are not used in actual products. The ELA technique is accompanied by expensive equipment and high process costs, and Metal Induced Crystallization (MIC) and Metal Induced Lateral Crystallization (MILC) methods using a Metal catalyst are inexpensive in terms of costs, but make the quality of the polycrystalline silicon thin film low.
Disclosure of Invention
Technical problem
A semiconductor device capable of forming a high-quality polycrystalline silicon thin film at a low process cost and a method of manufacturing the same are provided.
Also provided is an LTPS semiconductor device that can have a large area by efficiently forming LTPS and a method of manufacturing the same.
Technical solution to the problem
In a method of manufacturing an LTPS semiconductor device according to an aspect of the present disclosure, the LTPS is formed by using a thin film made of at least one selected from the group consisting of: NiCxOy, NiNxOy, NiCxNyOz, NiCxOy: H, NiNxOy: H, NiCxNyOz: H, NixSiy, and NixGey.
According to an aspect of the present disclosure, a method of manufacturing a semiconductor device includes:
forming a buffer layer of an insulating material on a substrate;
a seed layer forming operation of forming a seed layer selected from at least one of the group consisting of: NiCxOy, NiNxOy, NiCxNyOz, NiCxOy: H, NiNxOy: H, NiCxNyOz: H, NixSiy, and NixGey;
a silicon layer forming operation of forming an amorphous silicon layer on the seed layer; and
a crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of Ni by heat-treating the amorphous silicon layer.
The method may further include forming a catalytic reaction control layer between the seed layer formation operation and the silicon layer formation operation.
The silicon layer forming operation may include:
forming an amorphous intrinsic silicon layer for forming a channel on the buffer layer;
forming an extrinsic silicon layer for forming source/drain electrodes on the amorphous intrinsic silicon layer; and
a metal layer is formed on the extrinsic silicon layer.
The extrinsic silicon layer may be formed such that the first extrinsic silicon layer in contact with the amorphous silicon layer for forming the semiconductor channel has a lower doping concentration than the second extrinsic silicon layer.
The method may further include a patterning operation of forming source and drain electrodes corresponding to the intrinsic silicon layer by patterning the metal layer and the extrinsic silicon layer after the crystallization operation.
The patterning operation may include:
exposing the first extrinsic silicon layer in a channel region between the source electrode and the drain electrode by patterning the metal layer and the second extrinsic silicon layer;
a spacer forming operation of forming an insulating spacer on an inner side of the source electrode and the second extrinsic silicon layer thereunder and on an inner side of the drain electrode and the second extrinsic silicon layer thereunder, wherein a lower end of the spacer covers the first extrinsic silicon layer with a predetermined width; and
etching a portion of the first extrinsic silicon layer not covered by the spacers.
A P-type metal oxide semiconductor (PMOS) region and an N-type metal oxide semiconductor (NMOS) region may be divided on the extrinsic silicon layer, and
the silicon layer forming operation may include:
a p-type extrinsic silicon layer and a metal layer thereon are formed in the PMOS region, and an n-type extrinsic silicon layer and a metal layer thereon are formed in the NMOS region.
According to another aspect of the present disclosure, a semiconductor device may include:
substrate
A buffer layer formed on the substrate;
a channel layer formed of an intrinsic polycrystalline silicon layer on the buffer layer;
a polycrystalline source and drain formed of extrinsic silicon on both sides of the polycrystalline silicon layer;
a source electrode and a drain electrode formed on the polycrystalline source electrode and the drain electrode;
a gate electrode corresponding to the channel layer; and
NiSi2a contact layer between the source electrode and between the drain electrode and the drain electrode.
The extrinsic polycrystalline source and drain may include:
a first extrinsic silicon layer contacting both sides of the channel layer; and
a second extrinsic silicon layer disposed on the first extrinsic silicon layer, wherein
The first extrinsic silicon layer may extend further toward the gate than the second extrinsic silicon layer to form a Lightly Doped Drain (LDD).
A PMOS region and an NMOS region may be divided on the substrate, a p-type TFT including a source and a drain formed of a p-type extrinsic silicon layer may be formed in the PMOS region, and an n-type TFT including a source and a drain formed of an n-type extrinsic silicon layer may be formed in the NMOS region.
Advantageous effects of the disclosure
According to example embodiments, high quality predominantly oriented (111) LTPS may be obtained, and contamination by Ni may be negligibly reduced. When the crystallization of the a-Si thin film is induced by using an amorphous thin film seed layer made of at least one selected from the group consisting of NiCxOy, NiNxOy, NiCxNyOz, NiCxOy: H, NiNxOy: H, NiCxNyOz: H, NiCxNyOz: H, NixSiy, and NixGey, Ni precipitates to the surface of the thin film and thus does not remain in the TFT channel. LTPS has a crystallinity of 98% or more, a small surface RMS, high particle uniformity, a large area expansion, low manufacturing cost, and high productivity. Furthermore, the method according to example embodiments may reduce a photolithography (photolithographic) process by at least two stages, compared to the existing method of manufacturing an LTPS semiconductor device. Furthermore, with the existing source-drain doping process, when the silicon channel is crystallized without ion implantation (ion implantation), the activation of the source and drain is simultaneously performed, and in particular, the activation of the source and drain can serve as a mass production process of the a-Si TFT, thereby enabling the sharing of manufacturing facilities.
Drawings
Fig. 1a to 1j illustrate the operation of a process of manufacturing a semiconductor device according to the present disclosure.
Fig. 2a to 2k illustrate the operation of a process of fabricating a CMOS device according to the present disclosure.
Detailed Description
Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments of the present disclosure may be modified into various forms, and the scope of the present disclosure should not be construed as being limited to the embodiments described below. The embodiments of the present disclosure may be interpreted as provided to further thoroughly explain the spirit of the present disclosure to those skilled in the art. Like reference symbols in the various drawings indicate like elements. Various elements and regions in the drawings are schematically depicted. Accordingly, the spirit of the present disclosure is not limited to the relative sizes or spacings depicted in the figures.
Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, conversely, a second element could be termed a first element, without departing from the scope of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
While certain embodiments may be practiced in different ways, the particular order of processing may be different from that described. For example, two processes described in succession may be performed substantially concurrently or may be performed in an order reverse to that described.
Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The term "substrate" as used herein may mean the substrate itself or a stacked structure including the substrate and a predetermined layer or film formed on the surface thereof. As used herein, "the surface of the substrate" may mean an exposed surface of the substrate itself, or an outer surface of a predetermined layer or film formed on the substrate. What is described as "above … …" or "on … …" may include not only those that are in contact directly on … …, but also those that are not in contact over … ….
Hereinafter, a method of fabricating a MOS FET and a complementary metal-oxide semiconductor (CMOS) device to which the MOS FET is applied according to example embodiments will be described in detail with reference to the accompanying drawings. In the following description, silicon is referred to as the channel material of the transistor, but according to another example embodiment, other semiconductor materials than silicon (e.g., germanium) may be applied as an alternative material.
Fig. 1 schematically shows a main process in a process of manufacturing a metal oxide silicon field effect transistor (MOS FET) according to the present disclosure.
As illustrated in fig. 1a, a buffer layer (11) is formed from an insulating material on a substrate (10). The electronic device structure formed in the previous process may be present under the buffer layer (11). The substrate (10) may be a glass substrate or a plastic substrate. The buffer layer (11) may be formed of an insulating material used for manufacturing a semiconductor device, for example, may be formed of SiO2SiNx, SiONx, or AlOx.
As illustrated in fig. 1b, an amorphous seed layer (12) of several nanometers thickness is formed on the buffer layer (11). The seed layer (12) may be formed by using an Atomic Layer Deposition (ALD) method, and a constituent material of the seed layer (12) is one of NiCxOy, NiNxOy, and NiCxNyOz or one of NiCxOy: H, NiNxOy: H, NiCxNyOz: H containing hydrogen (hydrogen). In addition to the above materials, the material of the seed layer (12) may be NixSiy or NixGey.
As illustrated in fig. 1c, an intrinsic silicon layer (13) is formed by depositing intrinsic a-Si on the seed layer (12). Here, the thickness of the intrinsic silicon layer (13) may be adjusted in a range of about 50 nm to about 150 nm. As a selective element, between the seed layer (12) and the silicon layer (13), a catalytic reaction control layer (12a) may be formed to suppress or control a severe reaction between the Ni catalyst material and silicon due to direct contact between the seed layer (12) and the silicon layer (13). Prior to the formation of the silicon layer (13), a catalytic reaction control layer (12a) may be formed to a thickness of several angstroms to several nanometers through which the Ni catalyst material may permeate. The maximum thickness of the catalytic reaction control layer (12a) is limited to the thickness of the silicon layer (13) through which the Ni catalyst material can reach. The catalytic reaction control layer (12a) may be formed of a common insulating material, such as SiO2SiNx, SiONx or AlOx.
As illustrated in fig. 1d, a doped or extrinsic silicon layer (14) doped with a p-type dopant or an n-type dopant (dopant) and a metal layer (15) are sequentially stacked on the intrinsic silicon layer (13). Among the dopants, the p-type dopant includes at least one selected from the group consisting of B, Al, Ga, and In, and the n-type dopant includes at least one selected from the group consisting of P, Sb and As.
Here, the extrinsic silicon layer (14) may be formed as a single layer (single layer) doped with a p-type dopant or an n-type dopant at a predetermined concentration, and according to the present embodiment, may include first and second extrinsic silicon layers (14a,14b) having different doping concentrations. For example, a first extrinsic silicon layer in contact with the intrinsic silicon layer (13) has a lower doping concentration than a second extrinsic silicon layer (14b) thereon, and the first and second extrinsic silicon layers (14a,14b) are crystallized into polycrystalline silicon in a subsequent heat treatment process. The metal layer (15) may have a single-layer or multi-layer structure. According to the present embodiment, the metal layer (15) may have a sandwich structure having a stack structure of TiN/Al/TiN.
After the metal layer (15) is completed as described above, a-Si islands to be used as channels of TFTs are formed by patterning an intrinsic silicon layer formed in the transistor region, in particular, on the entire surface of the substrate (10).
As depicted in FIG. 1e, Metal Induced Crystallization (MIC) is performed by heat treatment. According to this heat treatment, a-Si of the amorphous silicon layer (13) on the seed layer (12) is crystallized, and thus, a silicon layer (13) formed of poly Si oriented in the (111) direction is obtained. In this process, Ni and Si of the seed layer (12) react with each other to produce NiSi2，NiSi2The uppermost extrinsic silicon layer (14) is reached after passing through the silicon layer (13) to form a contact layer (12') between the extrinsic silicon layer (14) and the metal layer (15), and nickel is precipitated outside the extrinsic silicon layer (14) after crystallization is completed. Furthermore, in the MIC process, the extrinsic silicon layers (13) are crystallized together and the dopants of the extrinsic silicon layers (14) are activated to form conductive regions.
According to the example embodiments described above, source/drain doping by existing ion implantation (iomplant) may be achieved through deposition of the extrinsic silicon layer (14) and MIC process without a separate ion implantation process. At the present stage, the source and drain are not yet isolated and the source (S) and drain (D) are obtained by a subsequent patterning process of the extrinsic silicon layer (14).
As illustrated in fig. 1f, the metal layer (15) and the second extrinsic silicon layer (14b) thereunder are patterned by using a photolithography method, thereby forming a source electrode (S) and a drain electrode (D) and a source electrode (15a) and a drain electrode (15b) corresponding thereto on both sides of the silicon semiconductor channel region (C). According to this patterning, a portion of the first extrinsic silicon layer (14a) overlying the intrinsic silicon layer (13) is exposed on the surface of the silicon semiconductor channel region (C).
Here, the extension region of the first extrinsic silicon layer (14a) not covered by the second extrinsic silicon layer (14b) corresponds to a Lightly Doped Drain (LDD) having a lower conductivity than the second extrinsic silicon layer (14 b).
As illustrated in fig. 1g, spacers (16) for covering an upper portion of the first extrinsic silicon layer (14a) are formed on opposite sides of the source electrode (15a) and the drain electrode (15b), which are formed over both sides of the intrinsic silicon layer (13) at a predetermined height.The spacers (16) are formed not only on the side surfaces of the source electrode (15a) and the drain electrode (15b), but also on the side surfaces of the second extrinsic silicon layer (14b) under the source electrode (15a) and the drain electrode (15b), and the lower end of the second extrinsic silicon layer (14b) covers the surface of the first extrinsic silicon layer (14 a). The spacers (16) may be made of an insulating material (e.g., SiO)2Or SiNx), and may be formed of SiO2Or SiNx, through a surface deposition and etch back (etch back) process to obtain spacers (16) covering the LDD regions.
As depicted in fig. 1h, a portion of the extrinsic silicon layer between the source electrode (15a) and the drain electrode (15b) not covered by the spacer (16) is removed. By this etch back process, the extension (14a') of the first extrinsic silicon layer (14a) corresponding to the LDD region is located under the spacer (16).
As illustrated in fig. 1i, a gate insulating layer (17) is formed on the entire surface of the source electrode (15a) and the drain electrode (15b) and the intrinsic silicon layer (13) exposed therebetween, and a gate electrode (18) is formed in the channel region between the source electrode (15a) and the drain electrode (15 b).
Here, the gate insulating layer (17) may be made of SiNx, SiO2One of AlOx or HfOx. The gate electrode (18) may be obtained by deposition and patterning of the entire surface of the MoW.
As illustrated in fig. 1j, an interlayer dielectric (19) having a contact hole (19a) is formed on the gate electrode (18), and electrode pads (Ps, Pg, Pd) electrically connected to the source electrode (15a), the drain electrode (15b), and the gate electrode (18) through the contact hole (19a) are formed on the ILD layer (19), respectively.
In the above processes, only the main part has been described without describing a method of manufacturing a complete MOS to help understanding example embodiments.
Hereinafter, an embodiment of a method of manufacturing a CMOS for a display will be described with reference to fig. 2a to 2 i.
As illustrated in fig. 2a, a buffer layer (21) and an amorphous seed layer (22) are sequentially formed on a substrate (20), defining (dividing) PMOS regions and NMOS regions in the substrate (20). The buffer layer (21) may be made of SiO2SiNx, SiONx or AlOxAnd (4) obtaining.
The seed layer (12) is formed to a thickness of several nanometers. The seed layer (12) may be formed using thermal atomic layer deposition (thermal ALD), plasma enhanced thermal atomic layer deposition (PE-ALD), pulsed Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. The constituent material of the seed layer is at least one selected from the group consisting of: NiCxOy, NiNxOy, NiCxNyOz, NiCxOy: H, NiNxOy: H, NiCxNyOz: H, NixSiy, and NixGey. The material of the seed layer material may comprise crystallization of silicon at a lower temperature than the existing NiOx, thereby obtaining high quality polysilicon.
As depicted in fig. 2b, the intrinsic silicon layer (23) to be used as the channel of the transistor is formed of amorphous silicon on the seed layer (22). Here, the thickness of the intrinsic silicon layer (23) is about 50 nm to about 150 nm. A catalytic reaction controlling layer (22a) as described above may be selectively formed. In other words, the catalytic reaction control layer (22a) is a selective element and may be formed before the formation of the intrinsic silicon layer (23). The catalytic reaction control layer may be formed of a common insulating material, such as SiOx, sion x, or AlOx.
As illustrated in fig. 2c, a p-type extrinsic silicon layer (24) containing p-type dopants and a first metal layer (25) are sequentially formed on the intrinsic silicon layer (23). Here, the p-type extrinsic silicon layer (24) may be formed of a plurality of layers having different doping concentrations.
In this embodiment, the p-type extrinsic silicon layer (24) includes a first extrinsic silicon layer (24a) and a second extrinsic silicon layer (24b) thereon. The second extrinsic silicon layer (24a) has a doping concentration that is relatively higher than the doping concentration of the first extrinsic silicon layer (24 a). The first metal layer (25) may have a multi-layer structure in which layers of the same or different types are stacked. According to the present embodiment, the first metal layer (25) may have a sandwich structure having a stack structure of TiN/Al/TiN.
As illustrated in fig. 2d, the p-type extrinsic silicon layer (24) is patterned from the first metal layer (25). Here, only the PMOS region remains, and the p-type extrinsic silicon layer (24) is removed by etching from the first metal layer (25) in the remaining region. To this end, for a detailed example, the PMOS region to be protected is covered by a mask layer, such as photoresist, and then etched, removing the p-type extrinsic silicon layer (24) and the portion of the first metal layer (25) outside the PMOS region, including the NMOS region.
After selective etching as described above, cleaning is performed and then a stack structure is formed on the intrinsic silicon layer (23) in the NMOS region, the stack structure including an n-type extrinsic silicon layer (26) in the NMOS region and a second metal layer (27) thereon.
As depicted in fig. 2e, an n-type extrinsic silicon layer (26) and a second metal layer (27) are formed in the NMOS region except the PMOS region. This process includes a process of depositing extrinsic silicon material and metal on the entire surface, and a process of removing n-type extrinsic silicon and metal thereon in a portion not including the NMOS region.
As depicted in fig. 2f, the stack structure for fabricating the p-type and n-type TFTs in the PMOS and NMOS regions, respectively, obtained by the process described above is patterned, forming silicon islands (23a,23b) from the amorphous extrinsic silicon layer (23) that will serve as the channels for the p-type and n-type TFTs.
As depicted in fig. 2g, MIC is performed by heat treatment to form poly-islands (23a ',24b') from silicon islands (23a,23b), which are (111) oriented. In this process, not only intrinsic silicon but also extrinsic silicon is crystallized. According to this crystallization, Ni and Si of the catalytic layer existing under the intrinsic silicon layer (23) are brought into contact with each other to form NiSi2And NiSi2Rises to the top of the silicon layer and contacts the first and second metal layers (25,26) to act as a contact layer between the silicon and the metal.
In the present embodiment, the heat treatment may be performed in a normal furnace (burn), and may also be performed in a furnace to which an electromagnetic field is applied.
As illustrated in fig. 2h, the first and second metal layers (25,27) are patterned to form source electrodes (25a,27a) and drain electrodes (25b,27b) in the PMOS and NMOS regions, and the first extrinsic silicon layers (24a,26a) are exposed under the channel region (C) therebetween.
Over both sides of the intrinsic silicon layer (23)And spacers (29) covering the first extrinsic silicon layers (24a,26a) are formed on opposite sides of the source electrodes (25a,27a) and the drain electrodes (25b,27b), the source electrodes (25a,27a) and the drain electrodes (25b,27b) being formed in the source region (S) and the drain region (D) at a predetermined height. Spacers (29) are formed not only on the side surfaces of the source electrodes (25a,27b) and the drain electrodes (25b,27b), but also on the side surfaces of the second extrinsic silicon layers (24b,26b) under the source electrodes (25a,27b) and the drain electrodes (25b,27b), and the lower ends thereof cover the surfaces of the first extrinsic silicon layers (24a,27a) providing LDD regions with a predetermined width. The spacers (29) may be made of an insulating material (e.g. SiO)2(or SiNx)) and may be formed of SiO2The full surface deposition and etch back (SiNx) process results in spacers (29) covering the LDD regions.
As illustrated in fig. 2i, the first extrinsic silicon layer (24a,26a) not covered by the spacers (29) is removed to expose the surface of the underlying polysilicon islands (23a ',23 b'). Here, the surfaces of the polysilicon islands (23a ',23b') are exposed by a Self-aligned (Self Align) etching method using the source electrodes (25a,27b), the drain electrodes (25b,27b), and the spacers (29) as masks.
As depicted in fig. 2j, a gate insulation layer (30) is formed over the PMOS region and the NMOS region, and each of the gate electrodes (31) is formed in a channel region of each of the PMOS region and the NMOS region.
Here, the gate insulating layer may be made of SiNx, SiO2One of AlOx or HfOx. The gate electrode can be obtained by deposition and patterning of the entire surface of the MoW.
As illustrated in fig. 2k, an ILD layer (32) having contact holes (32a) connected to the source, drain and gate electrodes is formed. Here, metal pads (33s,33g,33d) (34s,34g,34d)) are formed to complete a CMOS having PMOS TFTs and NMOS TFTs. Thereafter, processes for forming additional elements of the devices employing these CMOS may be performed.
In the above process, each of the intrinsic amorphous silicon layer and the extrinsic silicon layer containing n-type dopant or p-type dopant may be deposited in a separate cluster chamber (cluster chamber).
The materials of the source/drain electrodes and the gate electrode as described above are associated with control of the threshold voltage Vth of the device, and therefore need to be combined appropriately. Further, the LDD of the first extrinsic silicon layer is associated with control of the leakage current and control of the threshold voltage Vth, and thus, whether or not the LDD is to be formed can be determined by the control of the leakage current and the threshold voltage Vth. For example, LDDs may not be formed in PMOS.
The method of fabricating the LTPS TFT and the CMOS to which the LTPS TFT is applied according to the present disclosure as described above performs crystallization by substantially using amorphous Ni-based oxide as a catalyst. As the seed layer formed of the Ni-based oxide, one of NiCxOy, NiNxOy, and nicnyoz other than NiOx may be applied, or one of NiCxOy: H, NiNxOy: H and nicnyoz: H including hydrogen (H) may be applied. Further, the seed layer may be formed of NixSiy or NixGey.
By this process, LTPS TFTs oriented (111) on a glass substrate or a plastic substrate can be obtained, and CMOS can also be formed by using the LTPS TFTs.
In addition, when the polysilicon channel is formed, an intrinsic silicon layer for a silicon channel and intrinsic silicon for a source and a drain, i.e., silicon containing n-type dopants or p-type dopants, are formed. Therefore, crystallization of intrinsic silicon and crystallization and activation of extrinsic silicon to the source and drain are simultaneously achieved in the MIC process without an existing separate ion implantation process.
In addition, extrinsic silicon forming the source and drain is formed in the multilayer. Here, the dopant concentration of the first intrinsic silicon layer contacting the silicon channel may be lower than that of the second extrinsic silicon layer thereon, and the first extrinsic silicon layer may extend closer to the center of the channel than the second extrinsic silicon layer, thereby implementing LDD having low conductivity.
Methods of manufacturing semiconductor devices according to example embodiments have been described with reference to the embodiments depicted in the drawings to assist in understanding the present disclosure, but this is merely an example. It will be understood by those skilled in the art that various modifications and other equivalent embodiments from the described examples are possible. Therefore, the technical scope of the present disclosure should be defined by the appended claims.

Claims (15)

1. A method of fabricating a semiconductor device, the method comprising:
forming a buffer layer of an insulating material on a substrate;
a seed layer forming operation of forming a seed layer selected from at least one of the group consisting of: NiCxOy, NiNxOy, NiCxNyOz, NiCxOy: H, NiNxOy: H, NiCxNyOz: H, NixSiy, and NixGey;
a silicon layer forming operation of forming an amorphous silicon layer on the seed layer; and
a crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of nickel by heat-treating the amorphous silicon layer.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising:
a catalytic reaction control layer is formed between the seed layer formation operation and the silicon layer formation operation.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon layer forming operation comprises:
forming an amorphous intrinsic silicon layer for forming a channel on the buffer layer;
forming an extrinsic silicon layer for forming a source and/or a drain on the amorphous intrinsic silicon layer; and
a metal layer is formed on the extrinsic silicon layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the extrinsic silicon layer is formed such that a first extrinsic silicon layer in contact with an extrinsic silicon layer for forming a semiconductor channel has a lower doping concentration than a second extrinsic silicon layer.
5. The method for manufacturing a semiconductor device according to claim 4, further comprising:
a patterning operation of forming source and drain electrodes corresponding to the intrinsic silicon layer by patterning the metal layer and the extrinsic silicon layer after the crystallization operation.
6. The method of manufacturing a semiconductor device according to claim 4, wherein the patterning operation comprises:
exposing the first extrinsic silicon layer in a channel region between the source electrode and the drain electrode by patterning the metal layer and the second extrinsic silicon layer;
a spacer forming operation of forming an insulating spacer on an inner side of the source electrode and the second extrinsic silicon layer thereunder and on an inner side of the drain electrode and the second extrinsic silicon layer thereunder, wherein a lower end of the spacer covers the first extrinsic silicon layer with a predetermined width; and
etching a portion of the first extrinsic silicon layer not covered by the spacers.
7. The method for manufacturing a semiconductor device according to claim 2, wherein
A P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region are divided on the extrinsic silicon layer, and
the silicon layer forming operation includes:
a P-type extrinsic silicon layer and a metal layer thereon are formed in the P-type metal oxide semiconductor region, and an N-type extrinsic silicon layer and a metal layer thereon are formed in the N-type metal oxide semiconductor region.
8. The method for manufacturing a semiconductor device according to claim 3, wherein
A P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region are divided on the extrinsic silicon layer, and
the silicon layer forming operation includes:
a P-type extrinsic silicon layer and a metal layer thereon are formed in the P-type metal oxide semiconductor region, and an N-type extrinsic silicon layer and a metal layer thereon are formed in the N-type metal oxide semiconductor region.
9. The method for manufacturing a semiconductor device according to claim 4, wherein
A P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region are divided on the extrinsic silicon layer, and
the silicon layer forming operation includes:
a P-type extrinsic silicon layer and a metal layer thereon are formed in the P-type metal oxide semiconductor region, and an N-type extrinsic silicon layer and a metal layer thereon are formed in the N-type metal oxide semiconductor region.
10. The method for manufacturing a semiconductor device according to claim 5, wherein
A P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region are divided on the extrinsic silicon layer, and
the silicon layer forming operation includes:
a P-type extrinsic silicon layer and a metal layer thereon are formed in the P-type metal oxide semiconductor region, and an N-type extrinsic silicon layer and a metal layer thereon are formed in the N-type metal oxide semiconductor region.
11. The method for manufacturing a semiconductor device according to claim 6, wherein
A P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region are divided on the extrinsic silicon layer, and
the silicon layer forming operation includes:
a P-type extrinsic silicon layer and a metal layer thereon are formed in the P-type metal oxide semiconductor region, and an N-type extrinsic silicon layer and a metal layer thereon are formed in the N-type metal oxide semiconductor region.
12. A semiconductor device manufactured by the method according to claim 1 to claim 11, the semiconductor device comprising:
a substrate;
a buffer layer formed on the substrate;
a channel layer formed of an intrinsic polycrystalline silicon layer on the buffer layer;
a polycrystalline source and drain formed of extrinsic silicon on both sides of the polycrystalline silicon layer;
a source electrode and a drain electrode formed on the polycrystalline source electrode and the drain electrode;
a gate electrode corresponding to the channel layer; and
NiSi2a contact layer between the source electrode and between the drain electrode and the drain electrode.
13. The semiconductor device of claim 12, wherein the extrinsic poly source and drain comprise:
a first extrinsic silicon layer contacting both sides of the channel layer; and
a second extrinsic silicon layer disposed on the first extrinsic silicon layer, wherein
The first extrinsic silicon layer extends further toward the gate than the second extrinsic silicon layer to form a Lightly Doped Drain (LDD).
14. The semiconductor device according to claim 12, wherein
Dividing a P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region on the substrate, and
a P-type thin film transistor including a source and a drain formed of a P-type extrinsic silicon layer is formed in the P-type metal oxide semiconductor region, and an N-type thin film transistor including a source and a drain formed of an N-type extrinsic silicon layer is formed in the N-type metal oxide semiconductor region.
15. The semiconductor device according to claim 13, wherein
Dividing a P-type metal oxide semiconductor region and an N-type metal oxide semiconductor region on the substrate,
a P-type thin film transistor including a source and a drain formed of a P-type extrinsic silicon layer is formed in the P-type metal oxide semiconductor region, and an N-type thin film transistor including a source and a drain formed of an N-type extrinsic silicon layer is formed in the N-type metal oxide semiconductor region.
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