CN111884650B - Low-stray analog phase-locked loop linearization circuit - Google Patents
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Abstract
The invention relates to a low-stray analog phase-locked loop linearization circuit, and belongs to the technical field of analog integrated circuit design. The invention is composed of a phase frequency detector, a charge pump, a pulse current source, a pulse generator, a voltage-controlled oscillator, a frequency divider and an error accumulation modulator. The pulse generator controls the pulse current source to generate current with a certain pulse width, and moves a locking point in a stable state to a linear working area of the charge pump, so that the quantization noise folding effect and the instant ripple of the input voltage of the voltage-controlled oscillator are reduced. The low-spurious analog phase-locked loop linearization circuit achieves the effect that the PLL can work in a CP linear region and does not cause a circuit structure of obvious reference spurious.
Description
Technical Field
The invention relates to a low-stray analog phase-locked loop linearization circuit, and belongs to the technical field of analog integrated circuit design.
Background
Phase-locked loops (hereinafter referred to as PLLs) are core circuits in various communication and clock chips, and indexes such as spectral noise, jitter, spurious and the like of output signals of the phase-locked loops are very critical and directly relate to system performance. A charge pump (hereinafter referred to as CP) is an important module in the PLL, and its output current passes through a loop filter to generate a control voltage of a voltage controlled oscillator. The noise performance of the CP output signal is critical and determines the in-band noise floor of the entire PLL and the jitter of the PLL output clock.
The charge pump converts the phase signal output by the phase frequency detector into a current signal, the ideal CP input/output function is a linear relationship with a fixed slope, as shown in fig. 8(a), the ordinate is the output charge of the charge pump, and the abscissa is the phase difference, but in an actual circuit, due to various non-ideal factors of device operation, a non-linear effect occurs near zero phase difference. Especially in the fractional-N PLL, the nonlinear characteristic of the CP can fold and move the fractional modulator noise outside the PLL bandwidth to the PLL bandwidth, and the in-band noise of the PLL is deteriorated; but also degrades the spur performance at the PLL reference spur frequency.
Solutions to the problem of CP nonlinearity that degrades PLL in-band noise have been documented. For example, in the article "Hung-Ming Chien and Tsung-Hsien Lin, etc." published in 2004, "A4 GHz Fractional-N Synthesizer for IEEE 802.11a," in IEEE Symposium On VLSI Circuits Digest of Technical papers ", the constant current offset method shown in FIG. 1 is used to change the steady-state input phase difference of the PLL so that it moves to the linear operating region, as shown in FIG. 8(b), thereby avoiding the in-band noise degradation problem caused by the nonlinearity of the PLL. However, the cost of operating the PLL in the CP linear region is high reference spurs in the above documents, and it is necessary to invent a circuit structure that can operate the PLL in the CP linear region without causing significant reference spurs.
Disclosure of Invention
The invention aims to provide a low-spurious analog phase-locked loop linearization circuit, so that a PLL can work in a CP linear region, and a circuit structure of a significant reference spurious is not caused.
The low-spurious analog phase-locked loop linearizer provided by the invention comprises a pulse current source 207, a pulse generator 200, a phase frequency detector 201, a charge pump 202, a filter 203, a voltage-controlled oscillator 204, a frequency divider 205 and an error accumulation modulator 206. Wherein, the pulse generator 200 is connected with and controls the pulse current source 207 through the pulse signal; the phase frequency detector 201 is connected with the pulse generator 200; the charge pump 202 is connected with the phase frequency detector 201; the filter 203 is connected with the charge pump 202 and the pulse current source 207 at the same point; the voltage-controlled oscillator 204 is connected with the filter 203; the frequency divider 205 is connected to the voltage controlled oscillator 204; the error accumulation modulator 206 is connected to the frequency divider 205. Wherein, the pulse generator comprises: a first flip-flop 510, a second flip-flop 510, a third flip-flop 512, a fourth flip-flop 513, a fifth flip-flop 514, an and gate 515, a first inverter 516, a second inverter 517, a third inverter 518, a fourth inverter 518, a fifth inverter 521, a sixth inverter 522, a seventh inverter 523, an eighth inverter 524, and a nor gate 520; the data pole D of the first flip-flop 510 is connected to the output of the second inverter 517 and to the input of the third inverter 518; the input of the second inverter 517 is connected to the output of the first inverter 516; the input of the first inverter 516 is connected to the reference clock signal 2; the positive output pole of the first flip-flop 510 is connected to the data pole of the second flip-flop 510; the inverted output pole of the first flip-flop 510 is connected to one input terminal of the nor gate (520); the reset pole R of the first flip-flop 510 is connected with the reset pole R of the second flip-flop 510, the reset pole R of the third flip-flop 512, and the output end of the fifth inverter 521; the clock pole of the first flip-flop 510 is connected to the output of the and gate 515; the input ends of the and gate 515 are respectively connected to the high-speed clock signal 2 and the inverted output pole of the fourth flip-flop 513; the positive output pole of the second flip-flop 510 is connected to the data pole D of the third flip-flop 512; the clock pole of the second flip-flop 510 is connected to the output of the and gate 515; the positive output pole of the third flip-flop 512 is connected with the clock pole of the fourth flip-flop 513 and the input end of the sixth inverter 522; the output terminal of the sixth inverter 522 is connected to the input terminal of the fifth inverter 521; the clock pole of the third flip-flop 512 is connected to the output of the and gate 515; the data pole D of the fourth flip-flop 513 is tied high; the data pole D of the fourth flip-flop 513 is connected to the input of the nor gate 520; the reset pole R of the fourth flip-flop 513 is connected to the positive output pole of the fifth flip-flop 514 and the eighth inverter 524; the data electrode D of the fifth flip-flop 514 is connected to high level; the reset pole R of the fifth flip-flop 514 is connected to the positive output pole of the fifth flip-flop 514; the clock electrode of the fifth trigger is connected with the reference clock signal 2; the reset pole of the fifth flip-flop is connected to the output pole of the seventh inverter 523; the input pole of the seventh inverter 523 is connected to the eighth inverter 524.
The low-stray analog phase-locked loop linearization circuit provided by the invention has the advantages that:
the low-stray analog phase-locked loop linearization circuit provided by the invention is characterized in that a pulse generator is added on the existing phase-locked loop circuit to control a pulse current source to generate current with a certain pulse width, and a locking point in a stable state is moved to a linear working area of a charge pump, so that the quantization noise folding effect is reduced, and the instantaneous ripple of the input voltage of a voltage-controlled oscillator is reduced. The low-spurious analog phase-locked loop linearization circuit can enable the PLL to work in a CP linear region and does not cause obvious reference spurious.
Drawings
Fig. 1 is a schematic diagram of a conventional pll circuit.
Fig. 2 is a waveform diagram of a conventional pll circuit.
FIG. 3 is a schematic diagram of a low spurious analog PLL linearization circuit of the present invention.
FIG. 4 is a waveform diagram of a high linearity low spurious phase-locked loop according to the present invention.
FIG. 5 is a schematic diagram of a pulse generator in the analog PLL linearizer of the present invention.
Fig. 6 is a waveform diagram of the operation of the pulse generator.
Fig. 7 is a graph of beneficial effects.
Fig. 8(a) is a graph showing input/output characteristics of a general charge pump.
Fig. 8(b) is a graph showing input/output characteristics of the charge pump operating in the linear region.
In fig. 5, 510 is a first flip-flop, 511 is a second flip-flop, 512 is a third flip-flop, 513 is a fourth flip-flop, 514 is a fifth flip-flop, 515 is an and gate, 516 is a first inverter, 517 is a second inverter, 518 is a third inverter, 519 is a fourth inverter, 521 is a fifth inverter, 522 is a sixth inverter, 523 is a seventh inverter, 524 is an eighth inverter, and 520 is a nor gate.
Detailed Description
The structure of the low-spurious analog phase-locked loop linearizer provided by the invention is shown in fig. 3, and comprises:
a pulse current source 207, a pulse generator 200, a phase frequency detector 201, a charge pump 202, a filter 203, a voltage controlled oscillator 204, a frequency divider 205, and an error accumulation modulator 206;
the pulse generator 200 is connected with and controls the pulse current source 207 through a pulse signal; the phase frequency detector 201 is connected with the pulse generator 200; the charge pump 202 is connected with the phase frequency detector 201; the filter 203 is connected with the charge pump 202 and the pulse current source 207 at the same point; the voltage-controlled oscillator 204 is connected with the filter 203; the frequency divider 205 is connected to the voltage-controlled oscillator 204; the error accumulation modulator 206 is connected to the frequency divider 205.
The structure of the pulse generator 200 in the analog pll linearizer with low spurious emission as described above is shown in fig. 5, and includes:
a first flip-flop 510, a second flip-flop 511, a third flip-flop 512, a fourth flip-flop 513, a fifth flip-flop 514, an and gate 515, a first inverter 516, a second inverter 517, a third inverter 518, a fourth inverter 518, a fifth inverter 521, a sixth inverter 522, a seventh inverter 523, an eighth inverter 524, and a nor gate 52);
the data pole D of the first flip-flop 510 is connected to the output of the second inverter 517 and the input of the third inverter 518; the input of the second inverter 517 is connected to the output of the first inverter 516; the input of the first inverter 516 is connected to the reference clock signal 2; the positive output pole of the first flip-flop 510 is connected with the data pole of the second flip-flop 511; the inverted output pole of the first flip-flop 510 is connected to one input terminal of the nor gate 52); the reset pole R of the first flip-flop 510 is connected to the reset pole R of the second flip-flop 511, the reset pole R of the third flip-flop 512, and the output end of the fifth inverter 521; the clock pole of the first flip-flop 510 is connected to the output terminal of the and gate 515; the input ends of the and gate 515 are respectively connected to a high-speed clock signal 2 and the inverted output electrode of the fourth flip-flop 513; the positive output pole of the second flip-flop 511 is connected to the data pole D of the third flip-flop 512; the clock pole of the second flip-flop 511 is connected to the output terminal of the and gate 515; the positive output pole of the third flip-flop 512 is connected with the clock pole of the fourth flip-flop 513 and the input end of the sixth inverter 522; the output end of the sixth inverter 522 is connected to the input end of the fifth inverter 521; the clock pole of the third flip-flop 512 is connected to the output end of the and gate 515; the data electrode D of the fourth flip-flop 513 is connected with high level; the data electrode D of the fourth flip-flop 513 is connected to the input terminal of the nor gate 520; the reset pole R of the fourth flip-flop 513 is connected to the positive output pole of the fifth flip-flop 514 and the eighth inverter 524; the data electrode D of the fifth flip-flop 514 is connected to a high level; the reset pole R of the fifth flip-flop 514 is connected to the positive output pole of the fifth flip-flop 514; the clock electrode of the fifth trigger is connected with a reference clock signal 2; the reset pole of the fifth flip-flop is connected with the output pole of the seventh inverter 523; the input pole of the seventh inverter 523 is connected to the eighth inverter 524.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 3, 4, 5 and 6, it should be noted that the drawings provided in this embodiment are only schematic illustrations of the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, number and ratio of the components in actual implementation can be changed freely, and the layout of the components may be more complicated.
The low spurious analog pll linearizer of the present invention comprises at least the pulse current source 207 and the pulse generator 200 shown in fig. 2, and other pll basic blocks such as the phase frequency detector 201, the charge pump 202, the filter 203, the vco 204, the frequency divider 205, and the error accumulation modulator 206, which work in conjunction with them. Wherein, the phase frequency detector 201 is connected with the pulse generator 200; the charge pump 202 is connected with the phase frequency detector 201; the filter 203 is connected with the charge pump 202 and the pulse current source 207 at the same point; the voltage-controlled oscillator 204 is connected with the filter 203; the frequency divider 205 is connected to the voltage-controlled oscillator 204; the error accumulation modulator 206 is connected to the frequency divider 205.
As a preferable solution of this embodiment, although the structures in fig. 3 and fig. 1 can shift the operating point of the phase-locked loop to the linear region of CP, the structure in fig. 3 is improved compared with the conventional solution in fig. 1 in that: the current source 207 in fig. 3 is controlled by the pulse signal output by the pulse generator 200 to be turned on in a short time, and at this time, the pulse current 207 and the charge pump charging current 208 cancel each other out, so that no fluctuation is generated on the voltage controlled oscillator control voltage 210, and the purpose of shifting the operating point of the phase locked loop is achieved, as shown in fig. 4; while the current source 107 of fig. 1 is normally on, this causes the voltage controlled oscillator control voltage 110 of fig. 1 to ramp up as shown in fig. 3.
Further preferably, the specific structure of the pulse generator 200 is as shown in fig. 5, and includes: a first flip-flop 510, a second flip-flop 511, a third flip-flop 512, a fourth flip-flop 513, a fifth flip-flop 514, an and gate 515, a first inverter 516, a second inverter 517, a third inverter 518, a fourth inverter 518, a fifth inverter 521, a sixth inverter 522, a seventh inverter 523, an eighth inverter 524, and a nor gate 52); the data pole D of the first flip-flop 510 is connected to the output of the second inverter 517 and to the input of the third inverter 518; the input of the second inverter 517 is connected to the output of the first inverter 516; the input of the first inverter 516 is connected to the reference clock signal 2; the positive output pole of the first flip-flop 510 is connected to the data pole of the second flip-flop 511; the inverted output pole of the first flip-flop 510 is connected to one input terminal of the nor gate 520; the reset pole R of the first flip-flop 510 is connected with the reset pole R of the second flip-flop 511, the reset pole R of the third flip-flop 512, and the output end of the fifth inverter 521; the clock pole of the first flip-flop 510 is connected to the output of the and gate 515; the input ends of the and gate 515 are respectively connected to the high-speed clock signal 2 and the inverted output pole of the fourth flip-flop 513; the positive output pole of the second flip-flop 511 is connected to the data pole D of the third flip-flop 512; the clock pole of the second flip-flop 510 is connected to the output of the and gate 515; the positive output pole of the third flip-flop 512 is connected with the clock pole of the fourth flip-flop 513 and the input end of the sixth inverter 522; the output terminal of the sixth inverter 522 is connected to the input terminal of the fifth inverter 521; the clock pole of the third flip-flop 512 is connected to the output of the and gate 515; the data pole D of the fourth flip-flop 513 is tied high; the data pole D of the fourth flip-flop 513 is connected to the input of the nor gate (520); the reset pole R of the fourth flip-flop 513 is connected to the positive output pole of the fifth flip-flop 514 and the eighth inverter 524; the data electrode D of the fifth flip-flop 514 is connected to high level; the reset pole R of the fifth flip-flop 514 is connected to the positive output pole of the fifth flip-flop 514; the clock electrode of the fifth trigger is connected with the reference clock signal 2; the reset pole of the fifth flip-flop is connected to the output pole of the seventh inverter 523; the input pole of the seventh inverter 523 is connected to the eighth inverter 524. The waveforms for the operation of the pulse generator 200 are illustrated in fig. 6. As shown in fig. 6, the pulse generator outputs a synchronous pulse signal following the input high-speed clock signal 2 after the reference clock signal 2 goes high, and in the preferred embodiment of fig. 5 and 6, the high level of the pulse signal lasts for 2 cycles of the high-speed clock signal 2 and then is pulled low, so that the pulse signal controls the pulse current source 207 to perform a discharge operation with a fixed pulse width on the filter 203. When the next reference clock signal 2 goes high, the operation is repeated again, so that the current with the fixed pulse width can be injected into the loop, the phase-locked loop works in the linear region of the CP, and the instant matching of the charge pump charging current 208 and the pulse current 207 is not damaged, so that the invention aims to enable the PLL to work in the linear region of the CP without causing significant reference spurs.
The advantageous effects of the preferred version of the above embodiment are shown in fig. 7, which shows that the embodiment of fig. 2 has avoided the existing 40MHz reference spur of fig. 1, while suppressing the quantization noise fold-back in-band at low frequencies.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (1)
1. A low spurious analog PLL linearizer comprising at least:
the device comprises a pulse current source, a pulse generator, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a frequency divider and an error accumulation modulator; the pulse generator is connected with and controls the pulse current source through a pulse signal; the phase frequency detector is connected with the pulse generator; the charge pump is connected with the phase frequency detector; the filter is connected with the charge pump and the pulse current source at the same point; the voltage-controlled oscillator is connected with the filter; the frequency divider is connected with the voltage-controlled oscillator; the error accumulation modulator is connected with the frequency divider;
wherein the pulse generator comprises:
the circuit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, an AND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter and a NOR gate; the data electrode D of the first trigger is connected with the output of the second inverter and the input of the third inverter; the input of the second inverter is connected with the output of the first inverter; the input of the first inverter is connected with a reference clock signal 2; the output of the third inverter is connected with the input of the fourth inverter; the output of the fourth inverter is connected with a reference clock signal of the phase frequency detector; the positive output pole of the first trigger is connected with the data pole of the second trigger; the inverted output pole of the first trigger is connected with one input end of the NOR gate; the reset pole R of the first trigger is connected with the reset pole R of the second trigger, the reset pole R of the third trigger and the output end of the fifth inverter; the clock pole of the first trigger is connected with the output end of the AND gate; the input end of the AND gate is respectively connected with a high-speed clock signal 2 and the inverted output electrode of the fourth trigger; the positive output pole of the second flip-flop is connected with the data pole D of the third flip-flop; the clock pole of the second trigger is connected with the output end of the AND gate; the positive output pole of the third trigger is connected with the clock pole of the fourth trigger and the input end of the sixth inverter; the output end of the sixth inverter is connected with the input end of the fifth inverter; the clock pole of the third trigger is connected with the output end of the AND gate; the data electrode D of the fourth trigger is connected with a high level; the positive output pole of the fourth flip-flop is connected with the other input end of the NOR gate; the reset pole R of the fourth trigger is connected with the positive output pole of the fifth trigger and the input end of the eighth inverter; the data electrode D of the fifth trigger is connected with a high level; the reset pole R of the fifth flip-flop is connected with the positive output pole of the fifth flip-flop; the clock electrode of the fifth trigger is connected with a reference clock signal 2; the reset electrode of the fifth trigger is connected with the output electrode of the seventh inverter; and the input pole of the seventh inverter is connected with the output end of the eighth inverter.
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| CN101064510A (en) * | 2007-04-19 | 2007-10-31 | 电子科技大学 | Low phase spurious frequency synthesis method |
| CN102931981A (en) * | 2012-11-13 | 2013-02-13 | 苏州磐启微电子有限公司 | Ultra-low power consumption phase locked loop circuit |
| CN105634481A (en) * | 2015-12-25 | 2016-06-01 | 中国科学技术大学先进技术研究院 | Low stray linear circuit structure applied to fraction frequency division phase-locked loop |
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| TW589799B (en) * | 2002-07-17 | 2004-06-01 | Via Tech Inc | Charge-pump phase-locked loop circuit with charge calibration |
| EP1458099B1 (en) * | 2003-03-14 | 2005-12-21 | STMicroelectronics S.r.l. | A phase-locked loop circuit with switched-capacitor conditioning of the control current |
| DE102004031913A1 (en) * | 2004-06-21 | 2006-01-05 | Atmel Germany Gmbh | Charge pump of a phase-locked loop with switchable system bandwidth and method for controlling such a charge pump |
| CN1741389B (en) * | 2004-08-26 | 2014-06-11 | 瑞昱半导体股份有限公司 | Phase-locked loop with nonlinear phase error response characteristics |
| US9270288B2 (en) * | 2013-11-27 | 2016-02-23 | Silicon Laboratories Inc. | Time-to-digital converter based on a voltage controlled oscillator |
| CN204031123U (en) * | 2014-07-24 | 2014-12-17 | 江苏星宇芯联电子科技有限公司 | A kind ofly be applied to the phase discriminator based on Sampling techniques in phase-locked loop and charge pump circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101064510A (en) * | 2007-04-19 | 2007-10-31 | 电子科技大学 | Low phase spurious frequency synthesis method |
| CN102931981A (en) * | 2012-11-13 | 2013-02-13 | 苏州磐启微电子有限公司 | Ultra-low power consumption phase locked loop circuit |
| CN105634481A (en) * | 2015-12-25 | 2016-06-01 | 中国科学技术大学先进技术研究院 | Low stray linear circuit structure applied to fraction frequency division phase-locked loop |
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