CN111883436A - Chip packaging method and chip packaging device - Google Patents
Chip packaging method and chip packaging device Download PDFInfo
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- CN111883436A CN111883436A CN202010677203.XA CN202010677203A CN111883436A CN 111883436 A CN111883436 A CN 111883436A CN 202010677203 A CN202010677203 A CN 202010677203A CN 111883436 A CN111883436 A CN 111883436A
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- 238000000034 method Methods 0.000 title claims abstract description 26
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- 238000005192 partition Methods 0.000 claims abstract description 43
- 239000000853 adhesive Substances 0.000 claims abstract description 42
- 230000001070 adhesive effect Effects 0.000 claims abstract description 42
- 229910000679 solder Inorganic materials 0.000 claims description 22
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- 230000005611 electricity Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Pressure Sensors (AREA)
Abstract
The application discloses a chip packaging method and a chip packaging device, wherein the method comprises the following steps: the method comprises the following steps that a functional surface of at least one control chip faces a substrate and is electrically connected with the substrate, wherein a reticular partition plate is arranged on the substrate, and one control chip is arranged in one grid of the reticular partition plate; arranging support pieces on the base plate on two sides of each control chip, wherein the support pieces and the corresponding control chips are positioned in the same grid, and one side of each support piece, which is far away from the base plate, is higher than the non-functional surface of each control chip; the sensing chip is arranged on the supporting pieces on the two sides of the control chip in a bridging manner, and the functional surface of the sensing chip is electrically connected with the conductive bump on the substrate in a routing manner; arranging an adhesive on one side of the reticular clapboard away from the substrate; arranging a cover plate on the adhesive; the pressure on the side of the cover plate close to the substrate and the side of the cover plate away from the substrate are kept close until the adhesive is cured. By means of the mode, the probability of deformation and deviation of the cover plate can be reduced, and the yield of chip packaging devices is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a chip packaging method and a chip packaging device.
Background
The sensing chip for imaging, positioning and detecting is widely used in intelligent equipment, and the sensing chip and the control chip are packaged in the same packaging device, so that the size of the chip packaging device can be further reduced.
In the packaging process, after the control chip and the sensing chip are arranged, a cover plate needs to be added to finish the manufacture of the chip packaging device.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a chip packaging method and a chip packaging device, which can balance the pressure on two sides of a cover plate and reduce the probability of deformation and deviation of the cover plate.
In order to solve the technical problem, the application adopts a technical scheme that: a chip packaging method is provided, which comprises the following steps: the method comprises the following steps that a functional surface of at least one control chip faces a substrate and is electrically connected with the substrate, wherein a reticular clapboard is arranged on the substrate, and one control chip is arranged in one grid of the reticular clapboard; arranging support pieces on the base plate on two sides of each control chip, wherein the support pieces and the corresponding control chips are positioned in the same grid, and one side, far away from the base plate, of each support piece is higher than a non-functional surface of each control chip; a sensing chip is arranged on the supporting pieces on the two sides of the control chip in a bridging manner, and the functional surface of the sensing chip is electrically connected with the conductive bump on the substrate in a routing manner; arranging an adhesive on one side of the reticular clapboard away from the substrate; disposing a cover sheet on the adhesive; maintaining the pressure of the cover plate close to the side of the substrate and close to the side of the cover plate facing away from the substrate until the adhesive is cured.
Wherein the maintaining of the cover plate in close proximity to the side of the base plate and the side facing away from the base plate until the adhesive is cured comprises: and pressing the cover plate to one side close to the substrate at a first speed, wherein the first speed is inversely proportional to the pressure in a cavity formed by the cover plate, the reticular partition plate and the substrate.
Wherein said maintaining the pressure of the cover plate proximate the side of the base plate and away from the side of the base plate in proximity until the adhesive cures comprises: and utilizing a pressure oven to enable the pressure in a cavity formed by the cover plate, the mesh partition plate and the base plate to be close to the pressure on one side of the cover plate, which is far away from the base plate, so as to reduce the extrusion of the gas in the cavity to the cover plate.
Wherein, will through the mode of routing the functional surface of sensing chip with electrically conductive lug electricity on the base plate is connected, includes: forming solder on the functional surface of the sensing chip; and moving the conductive bump on the substrate to the solder on the sensing chip by using a cleaver so that the bonding wire in the cleaver is bonded with the conductive bump first and then bonded with the solder.
Wherein, with the functional surface of at least one control chip towards the base plate and with the base plate electricity is connected, include: a plurality of control chips correspond to the grids of the mesh-shaped partition plate, and one control chip is arranged in each grid; the control chip is deviated to one side of the grid with longer side length; electrically connecting the control chip with the substrate through a solder ball on the functional surface of the control chip; the height of the solder ball is higher than that of the conductive bump on the substrate.
Wherein the maintaining of the pressure approximation of the cover plate on the side close to the base plate and the side facing away from the base plate until the adhesive is cured, thereafter comprises: and cutting each grid serving as a unit corresponding to the position of the grid side wall on the reticular partition plate, and cutting off part of the reticular partition plate and the substrate to obtain the chip packaging device containing the single control chip and the single sensing chip.
In order to solve the above technical problem, another technical solution adopted by the present application is: the chip packaging device is prepared by the chip packaging method.
The sensing chip and the control chip are rectangular, a first center of the sensing chip is not overlapped with a second center of the control chip, and a connecting line of the first center and the second center is overlapped with a symmetry axis perpendicular to a long edge of the sensing chip.
Wherein the height of the support is 490-540 μm; and/or the thickness of the sensing chip is 300-400 mu m.
Wherein, the distance between the inner wall of the reticular clapboard and the side wall of the sensing chip is 600-700 mu m; and/or the Brinell hardness of the reticular separator is more than or equal to 40N/mm2。
The beneficial effect of this application is: the control chip and the sensing chip are arranged in the grid of the mesh-shaped partition plate and are electrically connected with the substrate, the sensing chip is bridged on the support piece to improve the stability of the sensing chip, the sensing chip is electrically connected with the substrate in a routing mode, when the cover plate is arranged on the mesh-shaped partition plate, one side of the cover plate close to the substrate and the pressure of one side of the cover plate away from the substrate are kept close until the adhesive is solidified, the influence of the pressure in a cavity formed by the cover plate, the mesh-shaped partition plate and the substrate on the extrusion of the cover plate is reduced, the probability of deformation and deviation of the cover plate is reduced, and the yield of a chip packaging device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;
FIG. 2a is a schematic cross-sectional front view of an embodiment corresponding to step S101 in FIG. 1;
FIG. 2b is a schematic cross-sectional side view illustrating an embodiment corresponding to step S101 in FIG. 1;
FIG. 3 is a schematic cross-sectional front view of an embodiment corresponding to step S102 in FIG. 1;
FIG. 4a is a schematic cross-sectional front view of an embodiment corresponding to step S103 in FIG. 1;
FIG. 4b is a schematic cross-sectional side view illustrating an embodiment corresponding to step S103 in FIG. 1;
FIG. 5 is a schematic flow chart of an embodiment corresponding to step S103 in FIG. 1;
FIG. 6a is a schematic cross-sectional side view illustrating an embodiment corresponding to step S201 in FIG. 5;
FIG. 6b is a cross-sectional side view of an embodiment corresponding to step S202 in FIG. 5;
FIG. 6c is a schematic cross-sectional side view illustrating another embodiment corresponding to step S202 in FIG. 5;
FIG. 7 is a schematic cross-sectional front view illustrating an embodiment corresponding to step S105 in FIG. 1;
FIG. 8 is a schematic cross-sectional front view of one embodiment of a chip package device according to the present application;
fig. 9 is a schematic top view of a chip package device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application, the method including:
step S101: and the functional surface of at least one control chip faces the substrate and is electrically connected with the substrate, wherein the substrate is provided with a reticular clapboard, and one control chip is arranged in one grid of the reticular clapboard.
Specifically, please refer to fig. 2a and fig. 2b, wherein fig. 2a is a schematic cross-sectional front view illustrating an embodiment corresponding to step S101 in fig. 1, and fig. 2b is a schematic cross-sectional side view illustrating an embodiment corresponding to step S101 in fig. 1. Wherein the substrate 102 is provided with a mesh-shaped partition 104, fig. 2a and 2b only schematically show the structure of the mesh-shaped partition 104 in a single mesh, and in practical applications, the mesh-shaped partition 104 is connected to the substrate 102 and has a plurality of meshes, and each mesh divides the substrate 102 into one area. In the above cross-sectional views, the mesh-like partition 104 is only schematically shown in a plan view with one of the side walls being cut away.
Specifically, a plurality of control chips 100 are arranged in a grid corresponding to the grid of the mesh-like partition 104, and one control chip 100 is arranged in each grid. The control chip 100 is biased to one side of the grid with a longer side length, the control chip 100 is electrically connected to the substrate 102 through the solder balls 1000 on the functional surface of the control chip 100, and the height of the solder balls 1000 is higher than that of the conductive bumps 1002 on the substrate 102. Each grid is rectangular, two rows of conductive bumps 1002 are respectively arranged at positions on the substrate 102 corresponding to the two longer sides of the rectangular grid, the functional surface of the control chip 100 faces the surface of the substrate 102, the control chip 100 is biased towards the side wall of the rectangular grid at the side with the longer side length, because the control chip 100 is relatively biased, the height of the solder ball 1000 is higher than that of the conductive bumps 1002 on the substrate 102, part of the area of the control chip 100 is positioned above the conductive bumps 1002 linearly arranged on the substrate 102 and cannot be contacted with the conductive bumps 1002, and further, the control chip 100 and the conductive bumps 1002 cannot be touched by mistake. In addition, after the control chip 100 is biased, the partial projection of the control chip 100 in the vertical direction coincides with the conductive bumps 1002, and compared with the arrangement mode that the control chip 100 is located between two rows of conductive bumps 1002, the width of the rectangular grid can be further reduced, the space of the rectangular grid is saved, and the size after packaging is further reduced.
Step S102: and supporting pieces are arranged on the base plates on two sides of each control chip, the supporting pieces and the corresponding control chips are positioned in the same grid, and one side, far away from the base plate, of each supporting piece is higher than the non-functional surface of each control chip.
Specifically, referring to fig. 3, fig. 3 is a schematic cross-sectional view of the front view of an embodiment corresponding to step S102 in fig. 1, wherein two sides of the control chip 100 are provided with supporting members 106, a height of the supporting members 106 is higher than a non-functional surface of the control chip 100, and the supporting members 106 may be made of silicon wafers, wherein the supporting members 106 and the substrate 102 are connected and fixed by glue (not shown).
Step S103: the sensing chip is arranged on the supporting pieces on two sides of the control chip in a bridging mode, and the functional surface of the sensing chip is electrically connected with the conductive bumps on the substrate in a routing mode.
Specifically, please refer to fig. 4a and 4b, in which fig. 4a is a schematic front cross-sectional view of an embodiment corresponding to step S103 in fig. 1, and fig. 4b is a schematic side cross-sectional view of an embodiment corresponding to step S103 in fig. 1. The sensing chip 108 is bridged on the supporting member 106, the length of the sensing chip 108 is greater than that of the control chip 100, and then the supporting member 106 plays a supporting role at two ends of the sensing chip 108 to support the sensing chip 108, so that the stability of the sensing chip 108 is improved. The cross-sectional view of the side view of fig. 4b can be understood as the view from the position of the dotted line a in fig. 4a, in which the height of the functional surface of the sensor chip 108 is lower than the height of the mesh partition 104.
Further, referring to fig. 5, fig. 5 is a flowchart illustrating an embodiment corresponding to step S103 in fig. 1, wherein the step of electrically connecting the functional surface of the sensor chip 108 to the conductive bump 1002 on the substrate 102 by wire bonding specifically includes:
step S201: solder is formed on the functional surface of the sensor chip.
Specifically, referring to fig. 6a, fig. 6a is a schematic side cross-sectional view of an embodiment corresponding to step S201 in fig. 5, a solder 1080 is formed at a pad (not shown) position on a functional surface of the sensor chip 108 to increase an area of the sensor chip 108 that can be in contact with other electrical elements, and the solder 1080 is electrically connected to the sensor chip 108.
Step S202: the riving knife is used to move from the position of the conductive bump on the substrate to the position of the solder 1080 on the sensing chip, so that the bonding wire inside the riving knife is firstly bonded with the conductive bump and then bonded with the solder 1080.
Specifically, please refer to fig. 6 b-6 c, wherein fig. 6b is a schematic side cross-sectional view of an embodiment corresponding to step S202 in fig. 5, and fig. 6c is a schematic side cross-sectional view of another embodiment corresponding to step S202 in fig. 5. Since the side wall of the mesh-shaped spacer 104 is closer to the side surface of the sensor chip 108, the distance between the side wall of the mesh-shaped spacer 104 and the sensor chip 108 is smaller, and the distance between the side wall of the mesh-shaped spacer 104 and the sensor chip 108 is about 600 μm, it is necessary to try a plurality of cleavers 120 with different sizes to avoid the contact between the cleaver 120 and the functional surface of the sensor chip 108 from damaging the sensor chip 108, wherein the width of the cleaver 120 is smaller than half of the distance between the side wall of the mesh-shaped spacer 104 and the sensor chip 108 when the cleaver 120 is located between the side wall of the mesh-shaped spacer 104 and the sensor chip 108, and the height of the cleaver 1200 is larger than the height of the functional surface of the.
Further, the bonding wire 109 is bonded to the conductive bump 1002 on the substrate 102 and then bonded to the solder 1080 on the sensor chip 108, which is different from the bonding wire 109 and the solder 1080 after the solder 1080 is formed, and then the bonding wire 109 is introduced into the deep cavity between the sidewall of the mesh partition 104 and the sensor chip 108, the bonding wire 109 is bent before being introduced into the deep cavity, the riving knife 120 is also located in the deep cavity, and the riving knife 120 is easily contacted with the bonding wire 109 on the side of the sensor chip 108 in the narrow deep cavity. After the bonding wire 109 is bonded with the conductive bump 1002, the chopper 120 moves to a side away from the substrate 102, the width of the knife tip 1200 of the chopper 120 is gradually reduced relative to the distance between the side wall of the mesh-shaped partition plate 104 and the sensor chip 108, and when the bonding wire 109 is bent and bonded with the solder 1080 after leading out the deep cavity between the side wall of the mesh-shaped partition plate 104 and the sensor chip 108, the side wall of the chopper 120 is not easy to touch the bonding wire 109 because the chopper 120 is not inside the deep cavity, and the bonding wire 109 is not damaged.
Optionally, in order to reduce the influence of the cleaver 120 on the bonding wires 109 in the deep cavity between the sidewall of the mesh-shaped spacer 104 and the sensor chip 108, the distance between the sidewall of the mesh-shaped spacer 104 and the sensor chip 108 is increased to 700 μm, the height of the support 106 is reduced, and the sensor chip 108 with the thickness of 300 μm is selected, so as to increase the height difference between the functional surface of the sensor chip 108 and the sidewall of the mesh-shaped spacer 104, and reduce the height of the deep cavity.
Step S104: and arranging an adhesive on one side of the reticular clapboard away from the substrate.
Step S105: the cover plate is arranged on the adhesive.
Specifically, referring to fig. 7, fig. 7 is a schematic cross-sectional front view of an embodiment corresponding to step S105 in fig. 1, in which an adhesive 112 is coated on a side of the mesh-shaped spacer 104 away from the substrate 102, and a glue with high adhesive strength and strong fluidity is selected to enable the adhesive 112 to sufficiently flow on the mesh-shaped spacer 104 and sufficiently fix the cover plate 114, wherein the adhesive 112 is only schematic, and the thickness of the adhesive 112 in practical applications is about 25 μm, and the adhesive 112 is illustrated in fig. 7 as an enlarged view of the adhesive 112.
Further, when the cover plate 114 is disposed on the mesh-type spacer 104, the cover plate 114, the mesh-type spacer 104 and the substrate 102 form a cavity, and the cured adhesive 112 forms a seal-like effect. In order to sufficiently bond the cover plate 114 and the adhesive 112, the cover plate 114 needs to be pressed by a dispensing head to flow the adhesive 112 under the cover plate 114. Therefore, before step S106, the method further includes: the cover plate 114 is pressed against the side adjacent the substrate 102 at a first rate that is inversely proportional to the pressure within the cavity formed by the cover plate 114, the mesh membrane 104, and the substrate 102.
Specifically, since the cover plate 114, the mesh-like partition 104 and the substrate 102 form a cavity, when the cover plate 114 is pressed downward, the gas in the cavity is compressed, the pressure in the cavity is gradually increased, and the gas in the cavity is diffused from the gap at the position of the uncured adhesive 112 to the outside of the cavity after being compressed before the adhesive 112 is not fully cured. The gas diffusion process becomes slower as the binder 112 flows and the binder 112 gradually solidifies.
Specifically, the first rate of pressing the cover plate 114 toward the side close to the substrate 102 is varied, the cover plate 114 is pressed so that the adhesive 112 can flow, the cavity is closed more as the adhesive 112 flows between the cover plate 114 and the mesh-type partition 104, the pressure in the cavity is increased by pressing the cover plate 114, initially, when the adhesive 112 is not sufficiently flowing, gas can flow out from the position of the adhesive 112 to release the pressure in the cavity, and as the cover plate 114 is further pressed, the gas in the cavity is more difficult to exhaust, and at this time, the pressure in the cavity is increased, and the first rate of pressing the cover plate 114 is reduced accordingly, and the first rate is inversely proportional to the pressure in the cavity. When the pressure in the cavity increases, the first rate of pressing the cover plate 114 is reduced to give time for the gas in the cavity to be able to escape from the location of the adhesive 112, so as to reduce the squeezing of the cover plate 114 by the gas in the cavity.
Step S106: the pressure on the side of the cover plate close to the substrate and the side of the cover plate away from the substrate are kept close until the adhesive is cured.
Specifically, the adhesive 112 needs to be heated to fully cure the adhesive 112, and since the gas inside the cavity formed by the cover plate 114, the mesh partition 104 and the substrate 102 expands due to the heat, the pressure inside the cavity formed by the cover plate 114, the mesh partition 104 and the substrate 102 is close to the pressure on the side of the cover plate 114 away from the substrate 102 by using the pressure oven, so as to reduce the pressure of the gas inside the cavity on the cover plate 114. The substrate 102, the cover plate 114 and the like are arranged in a pressure oven, and the pressure oven is used for pressurizing the outer side of the cavity to balance the air pressure inside the cavity after being heated, so that the extrusion of the air pressure inside the cavity to the cover plate 114 is reduced. After the adhesive 112 is completely cured, the heating of the adhesive 112 is stopped, and the cooling of the air inside the cavity is waited in the pressure oven, and the pressure of the pressure oven on the outside of the cavity is reduced to balance the pressure inside and outside the cavity until the adhesive 112 is cooled after curing, and the whole substrate 102, the cover plate 114 and the like are taken out of the pressure oven.
Further, referring to fig. 8, fig. 8 is a schematic cross-sectional front view illustrating a chip package device 10 according to an embodiment of the present application, and after step S106, the method further includes: cutting is performed on each grid unit corresponding to the position of the grid side wall on the mesh partition 104, and a part of the mesh partition 104 and the substrate 102 is cut off, so as to obtain the chip package device 10 including the single control chip 100 and the single sensing chip 108. The mesh partition 104 includes a plurality of meshes, in each of which a control chip 100, a support 106 and a sensor chip 108 are disposed, the sensor chip 108 and the substrate 102 are wire-bonded, and a cover plate 114 is integrally covered on the mesh partition 104. In order to obtain the chip package device 10 including the single control chip 100 and the single sensor chip 108, since the mesh-shaped spacer 104 is disposed on the substrate 102, a cutting blade having a blade edge length greater than the thickness of the mesh-shaped spacer 104 is selected to cut off a portion of the mesh-shaped spacer 104 and the cover plate 114 in units of each mesh to obtain the chip package device 10.
Specifically, the chip package device 10 is prepared by the above chip packaging method, and the chip package device 10 includes a substrate 102, a control chip 100, a support 106, a sensing chip 108, a single mesh of mesh spacers 104, and a cover plate 114. The functional surface of the control chip 100 is electrically connected to the substrate 102, the supporting members 106 are located on two sides of the control chip 100, the height of the supporting members 106 is higher than the non-functional surface of the control chip 100, the sensor chip 108 is bridged on the supporting members 106, the height of the side wall of the mesh partition 104 is higher than the side of the sensor chip 108 away from the substrate 102, and the cover plate 114 is disposed on the mesh partition 104.
Specifically, referring to fig. 9 in combination, fig. 9 is a schematic top view structure diagram of an embodiment of the chip package device 10 of the present application, and referring to fig. 8 in combination, wherein the cover plate 114 covers a structure thereunder, so that the cover plate 114 is not shown in fig. 9, and in addition, since the conductive bumps 1002 are densely and arrayed on the substrate 102, they are illustrated as elongated rectangles in fig. 9. In practical applications, the cover plate 114 may be made of glass, so that the structure below the cover plate is visible. The sensing chip 108 and the control chip 100 are rectangular, a first center of the sensing chip 108 is not overlapped with a second center of the control chip 100, and a connecting line of the first center and the second center is overlapped with a symmetry axis perpendicular to a long side of the sensing chip 108. That is, a connection line between the sensor chip 108 and the center point of the control chip 100 and a middle line between the long sides of the substrate 102 are overlapped, and both are broken lines B in fig. 9. The projection of the control chip 100 in the top view shields a part of the conductive bumps 1002, and the control chip 100 is biased to one side of one long side of the substrate 102, so that the width of the grid can be further reduced, the space of the grid can be saved, and the size of the chip package device 10 can be further reduced compared with the arrangement mode that the control chip 100 is located between two rows of the conductive bumps 1002.
Further, the height of the supporting member 106 is 490-540 μm, and/or the thickness of the sensing chip 108 is 300-400 μm. The sensor chip 108 is bridged over the support 106, and the sidewalls of both sides of the sensor chip 108 are flush with the sidewalls of the support 106 away from the control chip 100. Since the sidewalls of the two sides of the sensor chip 108 are flush with the sidewalls of the support 106 away from the control chip 100, only the sensor chip 108 can be seen from the top view.
In a specific application scenario, the height of the side wall of the mesh partition 104 is 1170 μm, the height of the supporting member 106 is 490 μm, the thickness of the sensor chip 108 is 300 μm, the height of the functional surface of the sensor chip 108 from the substrate 102 is 790 μm, and if considering that the glue used for fixing between the supporting member 106 and the substrate 102 and the glue used for fixing between the sensor chip 108 and the supporting member 106 are each 25 μm, the height of the functional surface of the sensor chip 108 from the substrate 102 is 840 μm, and the height difference between the functional surface of the sensor chip 108 and the side wall of the mesh partition 104 is 330 μm, therefore, when the height of the side wall of the mesh partition 104 is fixed, the sensor chip 108 with a thinner thickness is selected on the premise that the process conditions allow and the structural strength is ensured, and the height of the supporting member 106 is reduced on the premise that the non-functional surface of the control chip 100 is lower than the supporting member 106, the height difference between the functional surface of the sensor chip 108 and the side wall of the mesh partition 104 is increased, so that the routing is more convenient.
Further, the distance between the inner wall of the mesh-shaped partition 104 and the side wall of the sensor chip 108 is 600-700 μm, and/or the Brinell hardness of the mesh-shaped partition 104 is greater than or equal to 40N/mm2. When the distance between the inner wall of the mesh-shaped spacer 104 and the side wall of the sensor chip 108 is 700 μm, wire bonding between the sensor chip 108 and the conductive bump 1002 on the substrate 102 is easier, but the thickness of the inner wall of the mesh-shaped spacer 104 can only be reduced without changing the width of the chip package device 10, so that when the mesh-shaped spacer 104 is cut, the mesh-shaped spacer 104 is easily broken when the inner wall of the mesh-shaped spacer 104 is too thin, and therefore, the brinell hardness of the mesh-shaped spacer 104 is at least 40N/mm2The material is an alloy made of one or more metals of copper, iron, nickel and tungsten, the thickness of the inner wall of the reticular baffle plate 104 is set to be equal to the hardness of the reticular baffle plate 104And inversely proportional. As the hardness of the mesh-like spacer 104 is higher, the thickness of the inner wall of the mesh-like spacer 104 can be set thinner, and thus the cutting is not easily broken, and the yield of the chip package device 10 is improved.
In summary, the present application arranges the control chip 100 and the sensor chip 108 in the grid of the mesh partition 104 and electrically connected to the substrate 102, wherein the sensor chip 108 is bridged over the supporting member 106 to improve the stability of the sensor chip 108, the sensor chip 108 is electrically connected to the substrate 102 by wire bonding, when the cover plate 114 is arranged on the mesh partition 104, the pressure on the side of the cover plate 114 close to the substrate 102 and the pressure on the side of the cover plate 114 away from the substrate 102 are kept close to each other until the adhesive 112 is cured, thereby reducing the influence of the pressure in the cavity formed by the cover plate 114, the mesh partition 104 and the substrate 102 on the extrusion of the cover plate 114, reducing the probability of deformation and deviation of the cover plate 114, and improving the yield of the chip package device 10.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A chip packaging method is characterized by comprising the following steps:
the method comprises the following steps that a functional surface of at least one control chip faces a substrate and is electrically connected with the substrate, wherein a reticular clapboard is arranged on the substrate, and one control chip is arranged in one grid of the reticular clapboard;
arranging support pieces on the base plate on two sides of each control chip, wherein the support pieces and the corresponding control chips are positioned in the same grid, and one side, far away from the base plate, of each support piece is higher than a non-functional surface of each control chip;
a sensing chip is arranged on the supporting pieces on the two sides of the control chip in a bridging manner, and the functional surface of the sensing chip is electrically connected with the conductive bump on the substrate in a routing manner;
arranging an adhesive on one side of the reticular clapboard away from the substrate;
disposing a cover sheet on the adhesive;
maintaining the pressure of the cover plate close to the side of the substrate and close to the side of the cover plate facing away from the substrate until the adhesive is cured.
2. The method of claim 1, wherein the maintaining the pressure proximity of the cover sheet on the side adjacent to the substrate and the side facing away from the substrate until the adhesive cures comprises:
and pressing the cover plate to one side close to the substrate at a first speed, wherein the first speed is inversely proportional to the pressure in a cavity formed by the cover plate, the reticular partition plate and the substrate.
3. The method of claim 1, wherein maintaining the pressure approximation of the side of the cover sheet adjacent to the substrate and the side facing away from the substrate until the adhesive cures comprises:
and utilizing a pressure oven to enable the pressure in a cavity formed by the cover plate, the mesh partition plate and the base plate to be close to the pressure on one side of the cover plate, which is far away from the base plate, so as to reduce the extrusion of the gas in the cavity to the cover plate.
4. The packaging method according to claim 1, wherein the electrically connecting the functional surface of the sensor chip with the conductive bump on the substrate by wire bonding comprises:
forming solder on the functional surface of the sensing chip;
and moving the conductive bump on the substrate to the solder on the sensing chip by using a cleaver so that the bonding wire in the cleaver is bonded with the conductive bump first and then bonded with the solder.
5. The packaging method according to claim 1, wherein the step of facing the functional surface of the at least one control chip to a substrate and electrically connecting the functional surface to the substrate comprises:
a plurality of control chips correspond to the grids of the mesh-shaped partition plate, and one control chip is arranged in each grid; the control chip is deviated to one side of the grid with longer side length;
electrically connecting the control chip with the substrate through a solder ball on the functional surface of the control chip; the height of the solder ball is higher than that of the conductive bump on the substrate.
6. The method of claim 1, wherein the maintaining the pressure proximity of the cover plate on the side close to the substrate and the side away from the substrate until the adhesive is cured, thereafter comprises:
and cutting each grid serving as a unit corresponding to the position of the grid side wall on the reticular partition plate, and cutting off part of the reticular partition plate and the substrate to obtain the chip packaging device containing the single control chip and the single sensing chip.
7. A chip packaging device, characterized in that the chip packaging device is prepared by the packaging method of any one of claims 1 to 6.
8. The chip packaging device according to claim 7,
the sensing chip and the control chip are rectangular, a first center of the sensing chip is not overlapped with a second center of the control chip, and a connecting line of the first center and the second center is overlapped with a symmetry axis perpendicular to a long edge of the sensing chip.
9. The chip packaging device according to claim 7,
the height of the support is 490-540 μm; and/or the thickness of the sensing chip is 300-400 mu m.
10. The chip packaging device according to claim 7,
the distance between the inner wall of the reticular clapboard and the side wall of the sensing chip is 600-700 mu m; and/or the hardness of the mesh-shaped clapboard on the brinell hardness is more than or equal to 40N2。
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