CN111865304B - Dynamic phase-locked loop based on digital direct linear phase comparison - Google Patents
Dynamic phase-locked loop based on digital direct linear phase comparison Download PDFInfo
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Abstract
The invention discloses a dynamic phase-locked loop based on digital direct linear phase comparison.A frequency conversion circuit is connected with a voltage-controlled voltage oscillator (VCXO) after passing through an ADC module, an FPGA module and a low-pass filter in sequence, processes an input reference signal into a clock signal for controlling the conversion rate of the ADC module and sends the clock signal to the ADC module; the FPGA module receives the reference signal processed by the ADC module and outputs a PWM wave to the low-pass filter, the low-pass filter processes the PWM wave into corresponding direct-current voltage, and the voltage-controlled voltage output of the voltage-controlled voltage oscillator VCXO is changed; the voltage-controlled voltage oscillator VCXO is subjected to linear transformation by the amplitude preprocessing circuit and then is sent to the ADC module; a dynamic phase-locked loop based on digital direct linear phase comparison is realized, and the instantaneous phase difference between two different frequency signals is measured by using a linear digital phase discrimination method. The invention has the advantages of low noise, high precision, convenient integration, convenient chip formation and the like.
Description
Technical Field
The invention belongs to the technical field of radio communication, and particularly relates to a dynamic phase-locked loop based on digital direct linear phase comparison.
Background
The frequency synthesis of high resolution, micro-frequency differences has very important use value in the frequency synthesis direction. The most important feature is that the frequency of the signal to be obtained or of the controlled signal and the frequency of the input reference signal often have only differences of the order Hz, mHz, μhz or even smaller (meaning of micro-frequency differences), and it is desirable to be able to change the frequency of the output signal with resolution of the order mHz, μhz or even higher (meaning of micro-frequency differences). The frequency control method is mainly used for fine adjustment of the frequency value of the frequency standard signal, remote control of the frequency in time service comparison and the like.
Typical frequency synthesis methods currently include direct frequency synthesis, phase-locked frequency synthesis, and direct digital frequency synthesis. A relatively wide frequency adjustment range can be generally obtained by adopting a direct frequency synthesis method or a phase-locked frequency synthesis method, but the resolution of the frequency adjustment method can only reach the Hz or the order of 0.1 Hz. Although a direct digital frequency synthesis method can obtain high resolution and a wide frequency adjustment range, the stability index, the phase noise index and the like of the obtained signal are often poor, and ultra-low noise frequency conversion cannot be realized. The development of new frequency conversion control techniques is therefore an important research content.
When designing a phase locked loop using conventional techniques, a frequency conversion circuit is most often necessary, which converts the frequency signals of the reference signal and the output signal to a same frequency value, and then performs phase discrimination at the same frequency.
When the phase-locked loop works, the phase discriminator in the loop can compare the phase difference of two same-frequency signals in real time and output a voltage signal proportional to the phase difference, the whole loop works in a negative feedback state, and the system realizes phase locking. When locked, the whole loop is in a dynamic stable state, the frequency difference of two common-frequency signals at the input end of the phase discriminator is about zero, and the phase difference is basically a certain value. It can be seen that, in the loop locked condition, the frequency of the loop output signal is determined by the frequency of the input reference signal and the frequency conversion coefficient of the frequency conversion circuit in the loop, and in order to adjust the output frequency of the phase-locked loop, only the frequency conversion coefficient of the frequency conversion circuit in the loop is generally changed. If the frequency conversion coefficient is to be adjusted with high resolution, the implementation is very complex, and when the resolution requirement is very high, the frequency conversion coefficient is sometimes even not realized, so that the phase-locked loop based on the traditional technology cannot meet the requirements of some special occasions.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art, and provides a dynamic phase-locked loop based on digital direct linear phase comparison, which is suitable for fine adjustment of frequency values of frequency standard signals, remote control of frequencies in time service comparison and the like.
The invention adopts the following technical scheme:
a dynamic phase-locked loop based on digital direct linear phase comparison comprises a frequency conversion circuit and a frequency conversion circuitThe frequency conversion circuit is connected with a voltage-controlled voltage oscillator VCXO after passing through an ADC module, an FPGA module and a low-pass filter in sequence, and the frequency conversion circuit inputs a reference signal f ref Processing the clock signal into a clock signal for controlling the conversion rate of the ADC module and sending the clock signal to the ADC module; the FPGA module receives the reference signal f processed by the ADC module ref Outputting PWM waves to a low-pass filter, wherein the low-pass filter processes the PWM waves into corresponding direct-current voltages, and the voltage-controlled voltage output of a voltage-controlled voltage oscillator VCXO is changed; the voltage-controlled voltage oscillator VCXO is subjected to linear transformation by the amplitude preprocessing circuit and then is sent to the ADC module; a dynamic phase-locked loop based on digital direct linear phase comparison is realized, and the instantaneous phase difference between two different frequency signals is measured by using a linear digital phase discrimination method.
Specifically, the FPGA module comprises an FPGA high-speed ADC interface circuit and an MCU controller, wherein the FPGA high-speed ADC interface circuit is used for controlling the ADC module to perform analog-to-digital conversion, collecting conversion results and storing the conversion results into an on-chip RAM; the MCU controller measures the phase difference between the input signal of the ADC module and the reference signal by using the data in the on-chip RAM, and generates a PWM wave corresponding to the voltage-controlled voltage.
Specifically, the voltage-controlled voltage of the voltage-controlled voltage oscillator VCXO adopts a method of coarse adjustment firstly and then fine adjustment, the duty ratio of the PWM1 is set to be 50%, the coarse adjustment is completed by controlling the duty ratio of the PWM2, when the variation range of the high-level parameter of the PWM2 is controlled to be less than or equal to 2, the coarse adjustment is finished, fine adjustment is started, only the duty ratio of the PWM1 is regulated in the fine adjustment process, the output voltage of the PWM1 is 0-3.3 mv, and when the frequency of an output signal is a fixed value, the coarse adjustment is finished; the loop is quickly locked by combining coarse tuning and fine tuning.
Specifically, in the ADC module, a signal obtained by multiplying the frequency of the reference signal 10 is used as a sampling trigger signal to control the ADC module to perform data acquisition, a sampling circuit is triggered at the zero crossing time of the rising edge of the reference signal to obtain a plurality of measured values, the position of each data on the sinusoidal curve is determined, and then the phase of the corresponding measured signal and the time difference u between the zero crossing points are calculated 0 (0)，u 0 (T ref )，u 0 (2T ref ) Selecting a time axis and distance on the rising edge of the sine curveThe data with zero crossing point is used as effective measurement value for the subsequent calculation to obtain 10 initial phase differences pi/5 and frequency f ref Is the actual reference signal.
Further, reference signal u is selected at zero time in_0 (t) is:
u in_0 (t)＝U in sin(2πf ref t)
wherein U is in For the voltage amplitude of the input signal, f ref And t is time, which is an input reference signal.
Specifically, the low-pass filter attenuates the DC component of the PWM wave to a voltage of 0-3.3 mV, and then adds the voltage to a fixed DC bias voltage to obtain a final voltage-controlled voltage.
Further, the fine adjustment range of the voltage-controlled voltage oscillator VCXO is adjusted to 0 to 3.3V, and the resolution of the adjustment is adjusted to 0.66uV.
Compared with the prior art, the invention has at least the following beneficial effects:
the dynamic phase-locked loop based on the digital direct linear phase comparison can realize the fine adjustment of the output frequency under the condition that the frequency conversion coefficient of the frequency conversion circuit in the loop is unchanged, and the noise, the interference and the like of the novel dynamic phase-locked loop based on the digital direct linear phase comparison are very small; not only realizing the direct locking between two frequencies with approximately equal frequency, but also realizing the direct locking between two frequencies with approximately integer multiple relation; a linear digital phase discrimination technology is realized through a signal acquisition circuit of a high-speed analog-to-digital converter and a digital signal processing circuit based on a programmable logic device, and the ADC plays a role of a linear phase detector, so that the problem of linear distortion of sinusoidal signal waveforms to phase processing can be solved.
Furthermore, the high-speed ADC interface circuit of the FPGA module can generate control signals and command words meeting the time sequence requirement of the ADC module, and control the ADC to perform analog-to-digital conversion according to a certain time sequence, acquire conversion results and store the conversion results into the on-chip RAM; the MCU controller can measure the phase difference between the input signal of the ADC and the reference signal in a high resolution way by utilizing the data in the RAM, and can generate a PWM wave corresponding to the control voltage to be generated by utilizing a certain algorithm according to the actually obtained phase difference change rate and the theoretical phase difference change rate of the two signals.
Furthermore, an equivalent DAC is realized by using a PWM wave and a low-pass filter circuit, a composite structure of two paths of equivalent DACs is adopted, the voltages of the two paths of equivalent DACs are remixed through a proportional resistor at an output position, coarse adjustment and fine adjustment are combined, and numerical control voltage can be generated in a larger voltage range in a high resolution mode. Meanwhile, the control mode of combining coarse tuning and fine tuning can realize high-resolution control of output frequency and simultaneously accelerate the locking speed of a loop.
Further, the ADC module converts the input clock signal and the analog quantity of the input measured signal into digital quantity.
Furthermore, an equivalent DAC can be realized by using the PWM wave and the low-pass filter circuit, and the resolution of the realized DAC is very high, so that the method is suitable for generating numerical control voltage at low speed and high resolution.
Further, by changing the duty ratio of the output PWM wave, it is possible to obtain a voltage of 0 to 3.3V with a resolution of 1/5000 of the voltage adjustment, obtain the dc component of the PWM wave by using a low-pass filter and attenuate it appropriately, and the attenuation factor set here is 1000 times, the resolution can theoretically reach 0.66 μv, which is superior to the conventional V, mV-order resolution.
In summary, the invention has the phase-locked frequency conversion with the characteristic that the reference frequency and the output frequency are approximately equal or approximately in integer multiple, and has the advantages of low noise, high precision, convenient integration, convenient chip formation and the like.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a schematic block diagram of a novel dynamic phase-locked loop based on digitized direct linear phase alignment;
FIG. 2 is a signal contrast diagram, wherein (a) the relationship between the data collected by the analog-to-digital converter and the time difference of zero crossing points between the two signals, (b) the relationship between the "baseline reference signal" and the "actual reference signal";
FIG. 3 is a schematic block diagram of a high resolution voltage controlled voltage generation circuit;
FIG. 4 is an open loop experimental block diagram;
FIG. 5 is a closed loop experimental block diagram;
FIG. 6 is a graph of the measurement results of frequency stability;
fig. 7 is a graph of the measurement result of phase noise.
Detailed Description
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Various structural schematic diagrams according to the disclosed embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and their relative sizes, positional relationships shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
The invention provides a dynamic phase-locked loop based on digital direct linear phase comparison, which realizes fine adjustment of output frequency under the condition that the frequency conversion coefficient of a frequency conversion circuit in a loop is unchanged, and realizes high-precision phase adjustment by optimizing the conversion relation between phase and control voltage and the high-precision numerical control voltage (generating a voltage signal by utilizing digital quantity) generation technology based on PWM waves; the phase-locked frequency conversion system has certain reference and practical values for realizing phase-locked frequency conversion with the characteristic that the reference frequency and the output frequency are approximately equal or approximately in integer multiples, and simultaneously has the advantages of low noise, high precision, convenience in integration, convenience in chip formation and the like.
Referring to fig. 1, the dynamic phase-locked loop based on digital direct linear phase comparison of the present invention includes a frequency conversion circuit, an ADC module, an FPGA module, a low pass filter, a voltage-controlled voltage oscillator VCXO, and an amplitude preprocessing circuit.
The frequency conversion circuit converts the input reference signal f ref Processing the clock signal into a clock signal for controlling the conversion rate of the ADC and sending the clock signal to the ADC module; the ADC module is connected with the FPGA module, the FPGA module is sequentially connected with the low-pass filter LPF and the voltage-controlled voltage oscillator VCXO, the low-pass filter processes PWM waves output by the FPGA module into corresponding direct-current voltages, and the voltage-controlled voltage oscillator VCXO outputs a signal f through changing out And outputs a signal f out The signal is subjected to linear transformation by an amplitude preprocessing circuit and then sent to an ADC module; voltage controlled voltage oscillator VCXO for controlling the output signal f out When the output loop is locked, the frequency of the output signal is a fixed value, the phase is not jumped, a dynamic phase-locked loop system based on digital direct linear phase comparison is realized, a linear digital phase discrimination method is utilized to realize high resolution, and the instantaneous phase difference between two different frequency signals is measured at high speed.
The FPGA module comprises an FPGA high-speed ADC interface circuit and an MCU controller, and the FPGA high-speed ADC interface circuit is used for controlling the ADC module to carry out analog-to-digital conversion, collecting conversion results and storing the conversion results into an on-chip RAM;
the MCU controller utilizes the data in the on-chip RAM to measure the phase difference between the input signal of the ADC module and the reference signal in a high resolution mode and generates a PWM wave corresponding to the voltage-controlled voltage.
The amplitude preprocessing circuit can be used for outputting a signal f out The amplitude preprocessing circuit uses the existing typical circuit and is not described here again.
The purpose of the voltage-controlled voltage oscillator VCXO is to control the output signalf out Is a frequency of (a) is a frequency of (b).
The invention relates to a dynamic phase-locked loop based on digital direct linear phase comparison, which realizes the measurement of the instantaneous phase difference between two different frequency signals with high resolution and high speed by utilizing a linear digital phase discrimination technology through a signal acquisition circuit based on a high-speed analog-to-digital converter and a digital signal processing circuit based on a programmable logic device.
The ADC module is used for a digital linear phase detector; for two signals f with small frequency differences ref And f ref The +Deltaf, the signal obtained by frequency multiplication of the reference signal 10 or higher is used as a sampling trigger signal of the analog-to-digital converter to control the ADC module to acquire data, and the sampling circuit of the ADC module is triggered at the zero crossing moment of the rising edge of the reference signal, so that a plurality of measured values can be obtained in one period of the measured signal; determining the approximate position of each datum on the sine curve by analyzing the relation between the two, and then calculating the phase of the corresponding measured signal and the time difference u between zero crossing points 0 (0)，u 0 (T ref )，u 0 (2T ref ) …, as shown in fig. 2 (a).
On the other hand, data located on the rising edge of the sinusoidal curve and closer to the zero point is selected as the effective measurement value for the subsequent stage calculation. Because the slope of the sinusoid is greater near the zero crossing, the greater the slope, the higher the resolution of the phase, given the resolution of the voltage. Fig. 2 (b) is a schematic diagram of the relationship between "base reference signal" and "actual reference signal". The sampling trigger signal corresponding to the first valid measurement value is the "base reference signal", and the sampling trigger signal corresponding to the obtained valid measurement value during the measurement is the "actual reference signal". 10 initial phase differences pi/5 and frequency f are obtained by a method of multiplying frequency of a reference signal 10 ref Is the actual reference signal.
The reference signals selected at the zero time are as follows:
u in_0 (t)＝U in sin(2πf ref t) (1)
the left reference signal is:
the right reference signal is
Wherein U is in For the voltage amplitude of the input signal, f ref And t is time, which is an input reference signal.
Let t be the effective measurement value obtained by the analog-to-digital converter 0 And (t) in which the reference signal is changed N times, whereby the time difference P (t) between the measured signal at that time and the zero point of the "reference signal" can be found.
Meanwhile, in a novel dynamic phase-locked loop system based on digital direct linear phase comparison, an equivalent DAC is realized by using a PWM wave and a low-pass filter circuit, the resolution of the realized DAC is very high, and the system is suitable for generating digital control voltage at low speed and high resolution. The composite structure of the two paths of equivalent DACs is adopted, and the voltages of the two paths of equivalent DACs are remixed through the proportional resistor at the output position, so that the numerical control voltage can be generated in a larger voltage range in a high resolution mode.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The working process of the invention is as follows:
1. for input reference signal f ref Processing the clock signals into clock signals for controlling the conversion rate of the ADC through a frequency conversion circuit;
2. amplitude preprocessing circuit outputs signal f out Is linearly transformed so that its amplitude is substantially equal to the full scale of the ADC;
3. the input clock signal is a pulse signal, and the tested input signal of the ADC module is a sine signal with the amplitude meeting the ADC amplitude requirement;
4. the signal acquisition circuit based on a high-speed analog-to-digital converter (ADC) and the digital signal processing circuit based on a programmable logic device (FPGA) realize the high-resolution high-speed measurement of the instantaneous phase difference between two different frequency signals by utilizing a linear digital phase discrimination technology, and the ADC plays the role of a digital linear phase detector;
5. the FPGA high-speed ADC interface circuit generates control signals and command words meeting the time sequence requirement of an ADC chip, controls the ADC to perform analog-to-digital conversion according to a certain time sequence, acquires conversion results and stores the conversion results into an on-chip RAM; the MCU controller is used for high-resolution calculation of the phase difference between the input signal of the ADC and the reference signal of the data in the RAM in the chip, and the timer and the PID algorithm of the singlechip module are used for generating a PWM wave corresponding to the control voltage to be generated according to the actually obtained phase difference change rate and the theoretical phase difference change rate of the two signals. If the clock frequency of the timer is set to be 10MHz and the data corresponding to the PWM wave period is 5000, the frequency of the PWM wave is 2KHz. Assuming that the amplitude of the output pulse is 3.3V, by changing the duty ratio of the output PWM wave, it is possible to obtain a voltage of 0 to 3.3V, and the resolution of the voltage adjustment is 1/5000.
6. The direct current component of the PWM wave is obtained by using a low-pass filter and is attenuated properly, the voltage range after attenuation is set to be 0-3.3 mV (attenuation is 1000 times), and then the direct current component is added with the fixed direct current bias voltage to obtain the final voltage-controlled voltage. Thus, the fine tuning range of the obtained voltage-controlled voltage oscillator VCXO is 0-3.3V, and the tuning resolution can reach 0.66uV theoretically.
7. When voltage-controlled voltage is generated, a control idea of combining coarse adjustment and fine adjustment is adopted. Setting the duty ratio of PWM1 to 50% before the coarse adjustment starts, so that the voltage output by the PWM1 path is about 1.65mv, and then completing the coarse adjustment by controlling the duty ratio of PWM 2; when the variation range of the high-level parameter controlling the PWM2 is less than or equal to 2, the rough adjustment is finished, and the fine adjustment is started; in the process of fine tuning the voltage-controlled voltage, only the duty ratio of the PWM1 is regulated, and because the initial duty ratio of the PWM1 is 50%, the output voltage of the obtained PWM1 circuit can theoretically change within the range of zero to 3.3mv by regulating the duty ratio of the PWM1, the changing resolution is better than 1 mu v, the frequency of the output signal is regulated to be a fixed value, the phase jump of the output signal can not occur, and the phase difference between the output signal and the reference signal can be continuously changed along with the time; since the initial duty cycle of PWM1 is 50% at this time, by adjusting its duty cycle, the output voltage of the PWM1 path obtained can theoretically vary in the range of zero to 3.3mv, and the resolution of the variation is better than 1uv, which is sufficient to achieve high resolution locking of the loop. The combination of coarse tuning and fine tuning achieves fast locking of the loop.
8. The voltage-controlled voltage output by the low-pass filter is applied to the voltage-controlled terminal of the voltage-controlled oscillator VCXO, the output signal f of the VCXO being controlled by the voltage out Realize a dynamic phase-locked loop based on digitized direct linear phase comparison.
Based on digital direct linear phase comparison, the phase-locked loop with fine-adjustable output frequency can be realized under the condition that the variable frequency coefficient of a frequency conversion circuit in a loop is unchanged by using a dynamic phase-locked loop technology, high-speed and high-precision measurement and high-precision phase adjustment of a phase difference between two different frequency signals along with time change can be realized, fine adjustment of the output frequency which is superior to mu Hz magnitude can be realized through 0.1ps of phase adjustment resolution, and the adjustment range can reach Hz magnitude.
Referring to fig. 3, a schematic block diagram of a high-resolution voltage-controlled voltage oscillator VCXO is disclosed, in which a dual-path equivalent DAC composite structure is adopted, a timer of a single-chip microcomputer module is utilized to generate two paths of PWM waves (PWM 1 and PWM 2), PWM1 generates 0-3.3V through a shaping circuit and a low-pass filter, the resolution is 1mV, and then a 1000-time attenuation circuit generates a voltage with a resolution better than 1 μv, and the voltage is used as a fine adjustment voltage; the PWM2 generates 0-3.3V through a shaping circuit and a low-pass filter, the resolution is 1mV, the voltage is used as coarse adjustment voltage, and finally the voltage of the two paths of equivalent DACs is remixed through a proportional resistor at the output position of the adder, so that the numerical control voltage can be generated in a larger voltage range in a high resolution mode.
Referring to fig. 4, the performance of the designed high-resolution voltage-controlled voltage generation circuit and digital phase difference measurement module, and the stability of the output signal, the phase noise index and the variation of the output frequency when the voltage-controlled voltage is varied at different step values and rates are detected in an open loop experiment. In the experiment, the frequency stability and the phase noise TSC5125A of the symmetry company are adopted to respectively measure the frequency stability and the phase noise of the reference signal and the output signal of the voltage-controlled voltage oscillator before and after the loop is locked, the high-precision frequency meter 53220A of the Agilent company is adopted to measure the frequency of the voltage-controlled crystal oscillator and monitor the working condition of the loop, and the six-digit half-digital voltmeter GDM8261A is adopted to measure the actual output value of the voltage-controlled voltage generating circuit. The second measurement resolution of TSC5125A is 10 -13 On the order of magnitude, 53220A with a second measurement resolution of 10 -12 The reference source of the test equipment is a 10MHz signal output by a hydrogen atomic clock, and the performance of the reference source is better than that of the tested signal (the tested signal refers to 10MHz output of a rubidium atomic clock and 10MHz output of a voltage-controlled crystal oscillator), so that the error introduced by the reference source is negligible. The frequency value measured under the open loop condition is 10.000-2058898 MHz.
Referring to fig. 5, the noise floor of the loop and the acquisition performance of the loop were detected during the closed loop experiment. In the experiment, a 10MHz signal output by a rubidium atomic clock is used for locking the VCXO and outputting the VCXO as 10.0002MHz. The rubidium clock is a rubidium clock which adopts a phase-locked loop technology to improve phase noise, and the phase noise is about-155 dBc in the frequency band of 10 KHz-1 MHz; the frequency of the loop after being closed for a few seconds is stabilized to 10.000-2000001 MHz, the phase-locked loop can be normally locked, and the capturing time of the loop is a few seconds.
To sum upThe digital direct linear phase comparison-based dynamic phase-locked loop provided by the invention has the advantages that the correctness of the related design in the loop, the background noise of the measuring loop and the capturing performance of the detecting loop are checked through the open loop experimental diagram 4 and the closed loop experimental diagram 5. Measuring VCXO output signal f under open loop conditions out Frequency stability and phase noise of (a) and VCO output signal f after loop locking out The measurement result of the obtained frequency stability is shown in fig. 6, the measurement result of the phase noise is shown in fig. 7, and as can be seen from fig. 6, the frequency stability after frequency locking is very close to the frequency stability of the reference signal, so that a better locking effect is achieved; f in FIG. 7 ref Phase noise curve of (2) and f before and after loop locking out As can be seen from comparison of the phase noise curves of the phase locked loop, the noise, the interference and the like of the designed phase locked loop are very small. The analysis of experimental results shows that the loop can be normally locked, and the correctness of the principle and related design of the invention is verified.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (4)
1. The dynamic phase-locked loop based on digital direct linear phase comparison is characterized by comprising a frequency conversion circuit, wherein the frequency conversion circuit is connected with a voltage-controlled voltage oscillator VCXO after passing through an ADC module, an FPGA module and a low-pass filter in sequence; the FPGA module receives the reference signal processed by the ADC module
And outputs the PWM wave to the low-pass filter; the voltage-controlled voltage oscillator VCXO is subjected to linear transformation by the amplitude preprocessing circuit and then is sent to the ADC module; a dynamic phase-locked loop based on digital direct linear phase comparison is realized, and the instantaneous phase difference between two different frequency signals is measured by utilizing a linear digital phase discrimination method;
the FPGA module comprises an FPGA high-speed ADC interface circuit and an MCU controller, and the FPGA high-speed ADC interface circuit is used for controlling the ADC module to carry out analog-to-digital conversion, collecting conversion results and storing the conversion results into an on-chip RAM; the MCU controller measures the phase difference between the input signal of the ADC module and the reference signal by using the data in the on-chip RAM, and generates a PWM wave corresponding to the voltage-controlled voltage;
the voltage-controlled voltage of the voltage-controlled voltage oscillator VCXO adopts a method of coarse adjustment firstly and then fine adjustment, the duty ratio of the PWM1 is set to be 50%, the coarse adjustment is completed by controlling the duty ratio of the PWM2, when the variation range of the high-level parameter of the PWM2 is controlled to be less than or equal to 2, the coarse adjustment is finished, fine adjustment is started, only the duty ratio of the PWM1 is regulated in the fine adjustment process, the output voltage of the PWM1 is 0-3.3 mv, and when the frequency of an output signal is a fixed value, the fine adjustment is finished; the loop is quickly locked by combining coarse adjustment and fine adjustment;
in the ADC module, a signal obtained by frequency multiplication of a reference signal 10 is used as a sampling trigger signal to control the ADC module to acquire data, a sampling circuit is triggered at the zero crossing time of the rising edge of the reference signal to obtain a plurality of measured values, the position of each data on a sine curve is determined, and then the phase of the corresponding measured signal and the time difference between the zero crossing points are calculated
，/>
，
The data which is positioned on the rising edge of the sine curve and has zero point of the intersection point of the distance and the time axis is selected as effective measurement values for the subsequent stage calculation to obtain 10 initial phase differences +.>
Frequency->
Is the actual reference signal.
2. According to claim 1The dynamic phase-locked loop based on the digital direct linear phase comparison is characterized in that the reference signal selected at zero time
The method comprises the following steps:
wherein,,
for the voltage amplitude of the input signal, < >>
For the input reference signal, +.>
Is time.
3. The dynamic phase-locked loop for digital direct linear phase comparison according to claim 1, wherein the low pass filter attenuates the dc component of the PWM wave to a voltage of 0-3.3 mv and adds to the fixed dc bias voltage to obtain the final voltage controlled voltage.
4. The dynamic phase-locked loop for digital direct linear phase comparison according to claim 3, wherein the fine tuning range of the VCXO is adjusted to 0-3.3 v and the resolution is adjusted to 0.66uV.
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