CN106656176A - Wide-frequency-band agile frequency synthesizer - Google Patents
Wide-frequency-band agile frequency synthesizer Download PDFInfo
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- CN106656176A CN106656176A CN201611253750.5A CN201611253750A CN106656176A CN 106656176 A CN106656176 A CN 106656176A CN 201611253750 A CN201611253750 A CN 201611253750A CN 106656176 A CN106656176 A CN 106656176A
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- 239000003990 capacitor Substances 0.000 abstract 1
- 230000000087 stabilizing effect Effects 0.000 abstract 1
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- 238000006243 chemical reaction Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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Abstract
The invention discloses a wide-frequency-band agile frequency synthesizer. A signal obtained after an output frequency of a voltage-controlled oscillator is regulated by a digital regulator and then is subjected to frequency division by a first frequency divider and a datum signal obtained after a reference signal is subjected to frequency division by a second frequency divider are sent into a phase discriminator together; the phase discriminator outputs one direct current impulse voltage by comparing a frequency difference of the two signals; a high-frequency component of the voltage is filtered out by a loop filter and a VCO control voltage is generated; by utilizing a digital capacitor array, according to a preset frequency, a voltage tuning point in a VCO charge pump phase locking loop is directly changed; by tuning a voltage acceleration frequency stabilizing process, an output of the voltage-controlled oscillator is gradually stabilized into an expected frequency to complete frequency agility; by a third frequency divider, 1 to 64 times of frequency division is implemented; a wider frequency is output; and rapidness and stability of the frequency in the frequency changing process are achieved.
Description
Technical field
The present invention relates to the comprehensive technical field of frequency agility, specially a kind of wide-band agile frequency synthesizer.
Background technology
At present, frequency agility track design is all based on PLL technology and DDS technologies, and this easily realizes frequency hopping control with two kinds of technologies
System is closely related.Based on the frequency agility track of PLL technology, have the advantages that high-frequency, broadband, Frequency spectrum quality are good, but due to
The presence of system feedback circuit, system signal stably exports the process for needing a tracking lock, it is difficult to realize frequency agility, typically
In hundreds of more than μ s even Microsecond grades.DDS has high frequency resolution, and frequency agility is fast, but current broadband is still
Can not realize, output bandwidth is generally 0-40%fc.Although the digital structure of DDS has many advantages, due to this structure
And using the reason such as phase truncation, DAC digits during addressing ROM, result in that DDS clutter recognitions are poor, the purity of frequency spectrum is not as PLL.
So at present frequency agility track scheme is all based on the hybrid frequency combining methods of DDS+PLL mostly, i.e. in DDS excitation PLL, PLL
Slotting DDS, PLL and DDS direct conversion.Frequency agility track design needs the difficulty realized in cost, volume, power consumption and technology
Easily carry out comprehensive analysis in degree.
(1) DDS excitations PLL frequency agility schemes
The program can improve resolution ratio, and frequency converting time is shortened to a certain extent.Reference signal generates height by DDS
The signal of resolution ratio, signal is exported again by phase-locked loop circuit.The DDS can regard a frequency divider as, and PLL is considered as one
Individual frequency multiplier, DDS determines the precision of signal resolution, and phaselocked loop determines signal frequency converting time.DDS signals are after PLL frequencys multiplication
Output, fall in the loop bandwidth of PLL it is spuious cannot suppress with mutually making an uproar, cause Frequency spectrum quality poor.
(2) PLL interpolations DDS frequency agility scheme
Phase discriminator will be sent into after the mixing of the output of DDS and PLL feedback branches, the characteristics of the program utilizes DDS high-resolution,
Overcome the spuious phase caused because of frequency multiplication to make an uproar deterioration, but, frequency frequency converting time is mainly determined by PLL.Band logical in the program
Wave filter design difficulty is larger, should filter the intermodulation component of frequency mixer generation, and loop parameter can not be affected again.If frequency mixer
Radio frequency, intermediate frequency and local oscillator interport isolation are poor, can introduce the carrier leak and intermodulation component of higher amplitude, deteriorate radio-frequency channel index.
Although the program can shorten certain frequency converting time, loop filtering design difficulty is larger, and spurious reduction index can not meet need
Ask.
(3) PLL and DDS direct conversion frequency agility schemes
The program effectively overcomes the shortcoming of first two method, will not both deteriorate the spuious and index of mutually making an uproar of DDS outputs,
Also the design difficulty of PLL loop filterings will not be increased.Due to DDS output frequencies it is relatively low, using PLL as local oscillation signal, by DDS frequencies
Rate is mixed with PLL frequencies, exports higher operating frequency, and the program takes full advantage of the high-resolution of DDS and agile is special
Point.Because DDS output frequencies are well below PLL output frequencies, the spuious amplitude of the DDS of frequency mixer introducing is larger, bandpass filtering
Device cannot filter the intermodulation component in band, so spurious reduction can not meet system requirements.Direct conversion scheme is by increasing by one
Individual PLL, DDS output frequencies are carried out half of frequency multiplication to system requirements bandwidth or so, with original PLL mixing, filter intermodulation
The bandpass filter of component is easily designed, but circuit is complicated, and high cost, volume are big, are unsuitable for Miniaturization Design demand.
At present, various countries experts and scholars have carried out substantial amounts of research with regard to the PLL of fast frequency switching, mainly by Digital Frequency Synthesize
Device, twin nuclei, VCO DC voltages are preset, become the method such as loop bandwidth and frequency and phase discrimination method realizes.
The content of the invention
For achieving the above object, the present invention provides following technical scheme：A kind of wide-band agile frequency synthesizer, will be voltage-controlled
The output frequency of oscillator is after digital governer regulation, then the signal and reference signal after the frequency dividing of the first frequency divider
Reference signal after the second frequency divider frequency dividing sends into phase discriminator jointly, and phase discriminator is by comparing the frequency of above-mentioned two signal
Difference one DC pulse voltage of output, through loop filter the high fdrequency component of the voltage is filtered, and produces a VCO control electricity
Pressure, and using digital capacitance battle array, according to predetermined frequency, directly change voltage tuning point in VCO charge pump phase lock loops, by tuning
Voltage accelerates frequency stable process, the output of voltage controlled oscillator is progressively stable at into expected frequency and completes frequency agility, and passes through
Tri-frequency divider realizes 1-64 times of frequency dividing, exports broader frequency.
Used as a kind of preferred scheme of the present invention, first frequency divider and the second frequency divider are fractional frequency division pattern.
Used as a kind of preferred scheme of the present invention, the phase discriminator adopts high-frequency phase discriminator, in combination with digital capacitance
Battle array, realizes the high-resolution rate-adaptive pacemaker precision of 3Hz.
Used as a kind of preferred scheme of the present invention, the voltage controlled oscillator adopts micropackaging compensation crystal oscillator, realize-
102dBc/Hz@1K phase noises, 80dBc spurious reductions, the technical indicator of 70dBc harmonics restraints.
Used as a kind of preferred scheme of the present invention, the loop filter is using micropackaging resistance and electric capacity.
Compared with prior art, the invention has the beneficial effects as follows：Present invention is generally directed to the miniaturization communication dress such as hand-held station
Meter is installed, using highly integrated, low-power consumption, Miniaturization Design scheme, realizes that fast frequency switching, wide-band (25MHz～3.1GHz) are defeated
Go out and high-resolution (3Hz), frequency switching time is arbitrarily changed in the range of wide-band and is not more than 5 μ s, support 10000 jumps/s；Pass through
Optimization Simulation is designed, and in the case where reference source compensation crystal phase noise is -130dBc/Hz@1KHz, obtains good phase place
Noise, surveys as -100dBc/Hz@1KHz.
Description of the drawings
Fig. 1 is schematic structural view of the invention；
Fig. 2 is phase noise analogous diagram of the present invention；
Fig. 3 is agile analogous diagram of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Embodiment：
Fig. 1 is referred to, the present invention provides a kind of technical scheme：A kind of wide-band agile frequency synthesizer, it is characterised in that：
By the output frequency of voltage controlled oscillator after digital governer regulation, then the signal after the frequency dividing of the first frequency divider and ginseng
Examine reference signal of the signal after the second frequency divider frequency dividing and send into phase discriminator jointly, phase discriminator is by comparing above-mentioned two signal
Difference on the frequency export a DC pulse voltage, filter the high fdrequency component of the voltage through loop filter, produce a VCO control
Voltage processed, and using digital capacitance battle array, according to predetermined frequency, directly change voltage tuning point in VCO charge pump phase lock loops, pass through
VT accelerates frequency stable process, the output of voltage controlled oscillator is progressively stable at into expected frequency and completes frequency agility, and
1-64 times of frequency dividing is realized by tri-frequency divider, broader frequency is exported.
First frequency divider and the second frequency divider are fractional frequency division pattern, and the phase discriminator adopts high-frequency phase discriminator,
In combination with digital capacitance battle array, the high-resolution rate-adaptive pacemaker precision of 3Hz is realized, the voltage controlled oscillator adopts micropackaging temperature compensation
Crystal oscillator, realizes -102dBc/Hz@1K phase noises, 80dBc spurious reductions, the technical indicator of 70dBc harmonics restraints, institute
Loop filter is stated using micropackaging resistance and electric capacity, is -130dBc/Hz@1K in reference source phase noise using simulation software
In the case of, the indexs such as phase noise are simulated, meet design object.
Its phase noise emulation is as shown in Figure 2；
Agile analogous diagram is as shown in Figure 3.
In sum, this programme is designed using fractional frequency division, the preset technology of VCO DC voltages.Increase in VCO circuits
Plus digital variable varactor array, according to predetermined frequency, varactor optimum capacitance is selected, quickly adjustment VCO is electric
VT in lotus pump phaselocked loop, fast and stable when realizing that frequency changes frequency.By emulation, it is contemplated that switching time is not more than 5 μ s,
Holding equipment frequency hopping rate request, Miniaturization Design can be widely applied to the various occasions high to volume and power consumption requirements.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of spirit or essential attributes without departing substantially from the present invention, the present invention can be in other specific forms realized.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit is required rather than described above is limited, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as and limit involved claim.
Claims (5)
1. a kind of wide-band agile frequency synthesizer, it is characterised in that：By the output frequency of voltage controlled oscillator through digital regulated
After device is adjusted, then benchmark letter of the signal after the frequency dividing of the first frequency divider with reference signal after the second frequency divider frequency dividing
Number common to send into phase discriminator, phase discriminator exports a DC pulse voltage, passes through by comparing the difference on the frequency of above-mentioned two signal
Loop filter filters the high fdrequency component of the voltage, produces a VCO control voltage, and using digital capacitance battle array, according to preset
Frequency, directly changes voltage tuning point in VCO charge pump phase lock loops, and by VT frequency stable process is accelerated, will be voltage-controlled
The output of oscillator is progressively stable at expected frequency and completes frequency agility, and realizes 1-64 times of frequency dividing by tri-frequency divider,
Export broader frequency.
2. a kind of wide-band agile frequency synthesizer according to claim 1, it is characterised in that：First frequency divider and
Second frequency divider is fractional frequency division pattern.
3. a kind of wide-band agile frequency synthesizer according to claim 1, it is characterised in that：The phase discriminator is using high
Frequency phase discriminator, in combination with digital capacitance battle array, realizes the high-resolution rate-adaptive pacemaker precision of 3Hz.
4. a kind of wide-band agile frequency synthesizer according to claim 1, it is characterised in that：The voltage controlled oscillator is adopted
Micropackaging compensation crystal oscillator is used, -102dBc/Hz@1K phase noises, 80dBc spurious reductions, 70dBc harmonics restraints is realized
Technical indicator.
5. a kind of wide-band agile frequency synthesizer according to claim 1, it is characterised in that：The loop filter is adopted
With micropackaging resistance and electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611253750.5A CN106656176A (en) | 2016-12-30 | 2016-12-30 | Wide-frequency-band agile frequency synthesizer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611253750.5A CN106656176A (en) | 2016-12-30 | 2016-12-30 | Wide-frequency-band agile frequency synthesizer |
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| CN106656176A true CN106656176A (en) | 2017-05-10 |
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| CN201611253750.5A Pending CN106656176A (en) | 2016-12-30 | 2016-12-30 | Wide-frequency-band agile frequency synthesizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106830A (en) * | 2019-12-31 | 2020-05-05 | 陕西烽火电子股份有限公司 | Fast and agile broadband frequency synthesizer |
| CN111769830A (en) * | 2020-08-06 | 2020-10-13 | 成都凌德科技有限公司 | Broadband local oscillation circuit and local oscillation signal generating method |
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| EP1211811A1 (en) * | 2000-11-28 | 2002-06-05 | Koninklijke Philips Electronics N.V. | Fast frequency comparing circuit |
| CN102340308A (en) * | 2011-10-13 | 2012-02-01 | 电子科技大学 | Fractional-N frequency synthesizer |
| CN103490777A (en) * | 2013-09-30 | 2014-01-01 | 四川九洲电器集团有限责任公司 | Low spurious frequency synthesizer |
| CN203434966U (en) * | 2013-09-29 | 2014-02-12 | 重庆华伟工业（集团）有限责任公司 | Wide frequency band low-noise high-resolution frequency comprehensive component |
| CN204272083U (en) * | 2014-12-18 | 2015-04-15 | 陕西烽火实业有限公司 | A kind of ultrashort wave frequency hopping station frequency synthesizer |
-
2016
- 2016-12-30 CN CN201611253750.5A patent/CN106656176A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1211811A1 (en) * | 2000-11-28 | 2002-06-05 | Koninklijke Philips Electronics N.V. | Fast frequency comparing circuit |
| CN102340308A (en) * | 2011-10-13 | 2012-02-01 | 电子科技大学 | Fractional-N frequency synthesizer |
| CN203434966U (en) * | 2013-09-29 | 2014-02-12 | 重庆华伟工业（集团）有限责任公司 | Wide frequency band low-noise high-resolution frequency comprehensive component |
| CN103490777A (en) * | 2013-09-30 | 2014-01-01 | 四川九洲电器集团有限责任公司 | Low spurious frequency synthesizer |
| CN204272083U (en) * | 2014-12-18 | 2015-04-15 | 陕西烽火实业有限公司 | A kind of ultrashort wave frequency hopping station frequency synthesizer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106830A (en) * | 2019-12-31 | 2020-05-05 | 陕西烽火电子股份有限公司 | Fast and agile broadband frequency synthesizer |
| CN111106830B (en) * | 2019-12-31 | 2022-12-23 | 陕西烽火电子股份有限公司 | Fast and agile broadband frequency synthesizer |
| CN111769830A (en) * | 2020-08-06 | 2020-10-13 | 成都凌德科技有限公司 | Broadband local oscillation circuit and local oscillation signal generating method |
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