CN111863700A - Tray of semiconductor processing equipment and semiconductor processing equipment - Google Patents
Tray of semiconductor processing equipment and semiconductor processing equipment Download PDFInfo
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- CN111863700A CN111863700A CN202010704561.5A CN202010704561A CN111863700A CN 111863700 A CN111863700 A CN 111863700A CN 202010704561 A CN202010704561 A CN 202010704561A CN 111863700 A CN111863700 A CN 111863700A
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- arc surface
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- accommodating groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides a tray of semiconductor processing equipment and the semiconductor processing equipment, wherein the tray of the semiconductor processing equipment comprises a tray body and a supporting part, wherein a containing groove for containing a wafer is arranged on the tray body, the containing groove comprises a convex part positioned on the bottom surface of the containing groove, the upper surface of the convex part is an arc surface, the distance between a point on the arc surface and the bottom surface of the containing groove is gradually reduced from the center to the edge of the arc surface, so that the temperature difference between the center of the tray and the edge of the tray is reduced; the supporting component is arranged on the tray body and surrounds the periphery of the arc surface, and the supporting component is used for supporting the wafer and enabling a gap to be reserved between the wafer and the arc surface so as to reduce the heat conduction efficiency of the tray towards the edge of the wafer. The tray of the semiconductor processing equipment and the semiconductor processing equipment can improve the temperature uniformity of a wafer in the semiconductor process, thereby improving the resistivity uniformity of an epitaxial layer.
Description
Technical Field
The invention relates to the technical field of semiconductor equipment, in particular to a tray of semiconductor processing equipment and the semiconductor processing equipment.
Background
In the semiconductor epitaxial process, since the reaction rate of the doping gas (such as phosphine) is very sensitive to temperature, the temperature distribution on the substrate to be processed (Wafer) during the process has a great influence on the resistivity distribution of the epitaxial layer.
In the epitaxial process, a tray is usually adopted to bear the substrate, and heating devices arranged on the upper side and the lower side of the tray are adopted to heat the substrate, wherein the tray is made of a heat conduction material and is provided with a containing groove (Pocket) for containing the substrate, a step structure integrated with the containing groove is arranged in the containing groove, and each heating device comprises a reflecting screen and a heating lamp. In the epitaxial process, the step structure in the accommodating groove supports the edge part of the substrate, a gap is reserved between the other part of the substrate except the edge part and the groove bottom surface of the accommodating groove, the reflecting screen positioned above the tray directly reflects infrared rays emitted by the heating lamp to the upper surface of the substrate to heat the substrate, and the reflecting screen positioned below the tray reflects infrared rays emitted by the heating lamp to the tray to conduct heat to the substrate through the tray to heat the substrate. Therefore, in the epitaxial process, the area of the upper surface of the substrate, which is reflected by the reflecting screen, and the heat conducted and radiated by the tray onto the substrate all affect the temperature distribution on the substrate during the process, and further affect the resistivity distribution of the epitaxial layer.
Due to the defects of the existing reflecting screen in the processing technology, the conditions that the central temperature of the substrate is low and the edge temperature of the substrate is high always occur in the technological process, and finally the resistivity uniformity of the epitaxial layer is poor.
Disclosure of Invention
The invention aims to at least solve one technical problem in the prior art, and provides a tray of semiconductor processing equipment and the semiconductor processing equipment, which can improve the temperature uniformity of a wafer in the semiconductor process so as to improve the resistivity uniformity of an epitaxial layer.
To achieve the object of the present invention, there is provided a tray for a semiconductor processing apparatus, including a tray body and a support member,
the tray body is provided with an accommodating groove for accommodating a wafer, the accommodating groove comprises a convex part positioned on the bottom surface of the accommodating groove, the upper surface of the convex part is an arc surface, and the distance between a point on the arc surface and the bottom surface of the accommodating groove is gradually reduced from the center of the arc surface to the edge so as to reduce the temperature difference between the center of the tray and the edge of the tray;
the supporting component is arranged on the tray body and surrounds the periphery of the arc surface, and the supporting component is used for supporting the wafer and enabling a gap to be reserved between the wafer and the arc surface so as to reduce the heat conduction efficiency of the tray to the edge of the wafer.
Preferably, the support member is detachably connected to the tray body.
Preferably, a plurality of plug connectors are arranged on the tray body, and the lower surface of the supporting part is provided with a plug-in slot for accommodating the plug connectors, wherein the plug-in slot corresponds to the plug connectors.
Preferably, the supporting member is disposed on the bottom surface of the receiving groove and includes a plurality of sector-shaped supporting blocks spaced apart from each other in the circumferential direction of the protruding portion; the height of each fan-shaped supporting block is larger than the distance from the central point of the arc surface to the bottom surface of the accommodating groove, and the upper surface of each fan-shaped supporting block is positioned below the end surface of the notch of the accommodating groove.
Preferably, a plurality of thimble holes for the thimble to pass through are formed in the bottom surface of the accommodating groove, and the thimble holes are distributed at intervals along the circumferential direction of the arc surface;
the fan-shaped supporting blocks are correspondingly arranged with the thimble holes, and the fan-shaped supporting blocks are arranged between two adjacent thimble holes.
Preferably, the supporting member is disposed on the bottom surface of the receiving groove, and includes an annular supporting block, and the annular supporting block is disposed around the protrusion; and the height of the annular supporting block is greater than the distance from the central point of the arc surface to the bottom surface of the accommodating groove, and the upper surface of the annular supporting block is positioned below the end surface of the notch of the accommodating groove.
Preferably, a plurality of thimble holes for the thimble to pass through are formed in the bottom surface of the accommodating groove, and the thimble holes are distributed at intervals along the circumferential direction of the arc surface;
the annular supporting block is provided with a plurality of through holes for the ejector pins to pass through, and the through holes are arranged corresponding to the ejector pin holes.
Preferably, the distance between the central point of the arc surface and the upper surface of the fan-shaped support block or the annular support block is in the range of 0.45mm-0.55 mm.
Preferably, a preset gap is formed between the outer side wall of the supporting part and the inner peripheral wall of the accommodating groove.
The invention also provides semiconductor processing equipment which comprises the tray provided by the invention.
The invention has the following beneficial effects:
the tray body of the semiconductor processing equipment is provided with a supporting part and an accommodating groove for accommodating the wafer, wherein the accommodating groove comprises a convex part positioned on the bottom surface of the accommodating groove, the upper surface of the convex part is an arc surface, and the supporting part surrounds the arc surface and is used for supporting the wafer and enabling a gap to be formed between the wafer and the arc surface. Because the distance between the point on the arc surface and the bottom surface of the accommodating groove is gradually reduced from the center to the edge of the arc surface, the distance between the wafer and the arc surface is gradually increased from the center to the edge of the wafer in the semiconductor process, so that the heat radiated by the wafer from the arc surface is gradually reduced from the center to the edge of the wafer in the semiconductor process, and the temperature difference between the temperature of the center of the wafer and the temperature of the edge of the wafer is reduced. In addition, the supporting component can reduce the heat conduction efficiency of the tray towards the edge of the wafer, so that the heat quantity received by the edge of the wafer is lower than that received by the center of the wafer in the semiconductor process, the temperature difference between the temperature of the center of the wafer and the temperature of the edge of the wafer is reduced, the temperature uniformity of the wafer in the semiconductor process can be improved, and the resistivity uniformity of the epitaxial layer is improved.
According to the semiconductor processing equipment provided by the invention, the tray of the semiconductor processing equipment provided by the invention is used for bearing the wafer, so that the temperature uniformity of the wafer in the semiconductor process can be improved, and the resistivity uniformity of the epitaxial layer is further improved.
Drawings
Fig. 1 is a schematic front view of a tray of a semiconductor processing apparatus according to an embodiment of the present invention;
fig. 2 is a schematic front view of a tray body and a receiving groove of a tray of a semiconductor processing apparatus according to an embodiment of the present invention;
fig. 3 is a schematic top view of a tray of a semiconductor processing apparatus according to a first embodiment of the present invention;
fig. 4 is a schematic top view of a fan-shaped support block of a tray of a semiconductor processing apparatus according to a first embodiment of the present invention;
fig. 5 is a schematic structural view of a section of a sector-shaped support block of a tray of a semiconductor processing apparatus according to a first embodiment of the present invention;
fig. 6 is a schematic structural view of a bottom surface of a tray body of a tray of a semiconductor processing apparatus according to an embodiment of the present invention;
description of reference numerals:
10-a wafer; 11-a tray body; 12-accommodating grooves; 13-a convex part; 14-arc surface; 15-a support member; 16-sector shaped support blocks; 17-plug connector; 18-a plug groove; 19-upper surface; 20-lower surface; 21-thimble hole; 22-a limiting groove; 23-notch end face; 24-the bottom surface of the tray body; 25-preset gap.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the tray of the semiconductor processing apparatus and the semiconductor processing apparatus provided by the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1 to 6, the present embodiment provides a tray of a semiconductor processing apparatus, including a tray body 11 and a supporting member 15, wherein an accommodating groove 12 for accommodating a wafer 10 is provided on the tray body 11, the accommodating groove 12 includes a convex portion 13 located on a bottom surface of the accommodating groove 12, an upper surface of the convex portion 13 is an arc surface 14, and a distance between a point on the arc surface 14 and the bottom surface of the accommodating groove 12 is gradually decreased from a center to an edge of the arc surface 14, so as to reduce a temperature difference between the center of the tray and the edge of the tray; the supporting member 15 is disposed on the tray body 11 and surrounds the circular arc surface 14, and the supporting member 15 is used for supporting the wafer 10 and providing a gap between the wafer 10 and the circular arc surface 14 to reduce the heat conduction efficiency of the tray to the edge of the wafer 10.
The tray of the semiconductor processing equipment provided by the embodiment is provided with a supporting part 15 and a containing groove 12 for containing a wafer on a tray body 11, wherein the containing groove 12 comprises a convex part 13 positioned on the bottom surface of the containing groove 12, the upper surface of the convex part 13 is a circular arc surface 14, and the supporting part 15 surrounds the circular arc surface 14 and is used for supporting the wafer 10, and a gap is formed between the wafer 10 and the circular arc surface 14. Since the distance between the point on the arc surface 14 and the bottom surface of the accommodating groove 12 gradually decreases from the center to the edge of the arc surface 14, the distance between the wafer 10 and the arc surface 14 and the heat radiated from the arc surface 14 to the wafer 10 gradually decrease from the center to the edge of the wafer 10 during the semiconductor process, so that the temperature difference between the temperature of the center of the wafer 10 and the temperature of the edge is reduced. Moreover, since the supporting member 15 can reduce the efficiency of heat conduction from the tray to the edge of the wafer 10, the heat received by the edge of the wafer 10 is lower than the heat received by the center of the wafer during the semiconductor process, which also reduces the temperature difference between the temperature of the center of the wafer 10 and the temperature of the edge, thereby improving the temperature uniformity of the wafer 10 during the semiconductor process and further improving the resistivity uniformity of the epitaxial layer.
In this embodiment, the support member 15 is detachably connected to the tray body 11. That is, the supporting member 15 may be installed on the tray body 11 or removed from the tray body 11, so that a gas layer is formed between the supporting member 15 and the tray body 11, so that the tray body 11 and the wafer 10 are indirectly contacted through the supporting member 15 and the gas layer during the semiconductor process, and the heat exchange between the tray body 11 and the wafer 10 is indirectly performed through the supporting member 15 and the gas layer. That is, in the semiconductor process, the heat of the tray body 11 is first conducted to the gas layer, then conducted to the support member 15 through the gas layer, and then conducted to the wafer 10 through the support member 15, and since the thermal conductivity of the gas is much smaller than the thermal conductivities of the solid tray body 11 and the support member 15, the thermal conduction efficiency of the tray to the edge of the wafer 10 can be reduced.
Preferably, the material for manufacturing the supporting member 15 may be a material, such as quartz, which has a lower thermal conductivity than graphite, is resistant to high temperature, and is not prone to metal contamination in the semiconductor processing process, so that the heat conduction efficiency of the tray body 11 to the edge of the wafer 10 during the semiconductor processing process can be further reduced, the temperature uniformity of the wafer 10 during the semiconductor processing process can be further improved, and the resistivity uniformity of the epitaxial layer can be further improved.
Optionally, a plurality of plug connectors 17 are arranged on the tray body 11, an insertion groove 18 for accommodating the plug connectors 17 is formed in a lower surface 20 of the supporting component 15, and the insertion groove 18 corresponds to the plug connectors 17. The plurality of plug connectors on the tray body 11 are correspondingly plugged with the plurality of plugging grooves 18 formed on the lower surface 20 of the supporting part 15, so that the supporting part 15 is stably arranged on the tray body 11, and the supporting part 15 can stably support the edge of the wafer 10 in the semiconductor process.
As shown in fig. 6, in the present embodiment, a plurality of thimble holes 21 for thimble (not shown) to pass through are provided on the bottom surface of the receiving groove 12, the number of the thimble holes 21 is the same as that of the thimbles, and the thimble holes 21 are arranged in a one-to-one correspondence, and the plurality of thimble holes 21 are distributed around the arc surface 14 at intervals along the circumferential direction of the arc surface 14; the bottom surface 24 of tray body is provided with a plurality of spacing grooves 22, the quantity of spacing groove 22 is the same with the quantity of thimble hole 21, and the one-to-one sets up, every spacing groove 22 is located the same straight line of tray body 11 footpath with the thimble hole 21 that corresponds rather than, and the center of every spacing groove 22 is the same at tray body 11 footpath ascending interval with the centre of the thimble hole 21 that corresponds rather than, a plurality of spacing grooves 22 all are used for supplying to be used for supporting and lifting and falling inserting of a plurality of tray support piece (not shown in the figure) of tray body 11 in the semiconductor processing equipment, the quantity of spacing groove 22 is the same with tray support piece's quantity, and the one-to-one sets up.
Specifically, as shown in fig. 1 and 6, the bottom surface 24 of the tray body refers to a side surface of the tray body 11 away from the bottom surface of the accommodating groove 12, and a plurality of limiting grooves 22 are formed in the bottom surface 24 of the tray body, so that each limiting groove 22 can be used for inserting a tray support for supporting and lifting the tray body 11 in the semiconductor processing equipment, and the tray body 11 can be supported by a plurality of tray supports in the semiconductor processing equipment. During a semiconductor process, each pin can be raised and lowered relative to the pin hole 21 in the pin hole 21 corresponding to each pin to lift the wafer 10 from the robot or the support member 15 or to place the wafer 10 on the support member 15 to realize the transfer of the wafer 10.
The number of the limiting grooves 22 is the same as that of the thimble holes 21, the limiting grooves are arranged in a one-to-one correspondence manner, each limiting groove 22 and the thimble hole 21 corresponding to the limiting groove 22 are located on the same straight line in the radial direction of the tray body 11, the distance between the center of each limiting groove 22 and the center of the thimble hole 21 corresponding to the limiting groove 22 in the radial direction of the tray body 11 is the same, so that the circumference where the limiting grooves 22 are located and the circumference where the thimble holes 21 are located are concentric, the center of the circumference where the tray supporting pieces are located and the center of the circumference where the thimbles are located are concentric, the situation that the tray supporting pieces are lifted up and lowered down on the tray body 11 and the thimbles are lifted up and lowered down in the thimble holes 21 corresponding to each other is avoided, the tray supporting pieces are interfered with the thimbles, and the use stability of the tray of the semiconductor.
As shown in fig. 3 to 5, in the first embodiment of the present invention, the support member 15 is provided on the bottom surface of the receiving groove 12, and includes a plurality of sector-shaped support blocks 16 spaced apart in the circumferential direction of the convex portion 13; the height of each sector-shaped support block 16 is greater than the distance from the center point of the arc surface to the bottom surface of the receiving groove 12, and the upper surface 19 of each sector-shaped support block 16 is located below the notch end surface 23 of the receiving groove 12.
Specifically, the manner in which the plurality of fan-shaped support blocks 16 are disposed on the bottom surface of the accommodating groove 12 may be that a plurality of plug connectors 17 are disposed on the bottom surface of the accommodating groove 12, and the plurality of plug connectors 17 are circumferentially spaced around the convex portion 13 along the convex portion 13, an insertion groove 18 is disposed on a lower surface 20 of each fan-shaped support block 16, the number of the plug connectors 17 is the same as the number of all the insertion grooves 18 on the plurality of fan-shaped support blocks 16, and all the insertion grooves 18 on the plurality of fan-shaped support blocks 16 are used for the one-to-one insertion of the plurality of plug connectors 17.
Each of the sector-shaped support blocks 16 supports the edge of the wafer 10 during a semiconductor process to support the edge of the wafer 10 through the plurality of sector-shaped support blocks 16, and the height of each of the sector-shaped support blocks 16 is greater than the distance from the center point of the arc surface 14 to the bottom surface of the receiving groove 12, so that the plurality of sector-shaped support blocks 16 can have a gap between the wafer 10 and the arc surface 14 when supporting the wafer 10, and the upper surface 19 of each of the sector-shaped support blocks 16 is located below the notch end surface 23 of the receiving groove 12, so that the wafer 10 can be located in the receiving groove 12 during the semiconductor process.
In addition, the gas between the wafer 10 and the bottom surface of the accommodating groove 12 can be exhausted in the process of placing the wafer 10 on the plurality of fan-shaped support blocks 16 by the intervals between the plurality of fan-shaped support blocks 16, so that the position of the wafer 10 relative to the plurality of fan-shaped support blocks 16 is prevented from being moved when the wafer 10 is placed on the plurality of fan-shaped support blocks 16, the uniformity of the placing position of the wafer 10 is improved, and the stability of the semiconductor processing technology is improved.
Alternatively, in the first embodiment, the distance between the center point of the arc surface 14 and the upper surface 19 of the sector-shaped support block 16 is in the range of 0.45mm to 0.55 mm.
Alternatively, in the first embodiment, the distance in the vertical direction between the upper surface 19 of the sector support block 16 and the notch end surface 23 is in the range of 0.6mm to 1 mm.
Optionally, in the first embodiment, the length of the upper surface 19 of each of the sector support blocks 16 in the radial direction of the arc surface 14 is within a range from 3mm to 6mm, so that when each sector support block 16 supports the edge of the wafer 10, the contact range between the upper surface 19 of the wafer 10 and the edge of the wafer 10 in the radial direction is within a range from 3mm to 6mm, which can ensure that there is sufficient friction between the wafer 10 and the sector support blocks 16, so as to reduce the risk of the wafer 10 shifting on the sector support blocks 16 during the semiconductor process, and ensure that the temperature of the edge of the wafer 10 is effectively reduced, so as to effectively improve the temperature uniformity of the wafer 10 during the semiconductor process.
Optionally, in the first embodiment, the thickness of the sector support block 16 is in the range of 1.5mm to 2 mm. In practical applications, the thickness of the tray body 11 is strictly required by the semiconductor processing equipment, so that the greater the thickness of the sector-shaped support block 16, the greater the depth of the receiving groove 12, the smaller the thickness of the portion of the tray body 11 below the receiving groove 12, the strength of the sector-shaped support block 16 decreases as the thickness of the sector-shaped support block 16 decreases, and the strength of the tray body 11 decreases as the thickness of the portion of the tray body 11 below the receiving groove 12 decreases. By setting the thickness of the sector-shaped support block 16 within the range of 1.5mm to 2mm, it is possible not only to make the sector-shaped support block 16 have sufficient strength to support the wafer 10, but also to avoid the thickness of the portion of the tray body 11 located below the accommodation groove 12 from being excessively small, so that the tray body 11 has sufficient strength.
As shown in fig. 3, in the first embodiment, a plurality of thimble holes 21 for the thimble to pass through are provided on the bottom surface of the receiving groove 12, and the plurality of thimble holes 21 are distributed at intervals along the circumferential direction of the arc surface 14; the sector-shaped supporting blocks 16 are correspondingly arranged with the thimble holes 21, and the sector-shaped supporting blocks 16 are arranged between two adjacent thimble holes 21.
Specifically, in the semiconductor process, each thimble can be lifted in the corresponding thimble hole 21 so as to lift the wafer 10 from the manipulator or the plurality of fan-shaped support blocks 16, or the wafer 10 is placed on the plurality of fan-shaped support blocks 16, and the fan-shaped support blocks 16 are arranged between two adjacent thimble holes 21, so that interference of the fan-shaped support blocks 16 on the lifting of the thimble is avoided, and the use stability of the tray of the semiconductor processing equipment is improved.
In the first embodiment, a predetermined gap 25 is provided between the outer side wall of the support member 15 and the inner peripheral wall of the receiving groove 12. That is, a predetermined gap 25 is provided between the side of each sector-shaped support block 16 having the larger arc length and the inner circumferential wall of the receiving groove 12.
Therefore, the distance from the edge of the wafer 10 to the inner peripheral wall of the accommodating groove 12 can be increased, the heat radiated from the inner peripheral wall of the accommodating groove 12 is received by the edge of the wafer 10 in the semiconductor process, the temperature uniformity of the wafer 10 in the semiconductor process can be further improved, the resistivity uniformity of an epitaxial layer can be further improved, the interference between the wafer 10 and the inner peripheral wall of the accommodating groove 12 can be avoided when the wafer 10 is placed on the fan-shaped supporting block 16, and the placing position of the wafer 10 can be adjusted conveniently.
Optionally, the preset gap 25 is in the range of 1mm-2 mm.
In the second embodiment of the present invention, the supporting member 15 is disposed on the bottom surface of the receiving groove 12, and includes an annular supporting block (not shown), the annular supporting block is disposed around the protrusion 13, the height of the annular supporting block is greater than the distance from the center point of the arc surface 14 to the bottom surface of the receiving groove 12, and the upper surface of the annular supporting block is located below the notch end surface 23 of the receiving groove 12.
Specifically, the mode that the annular supporting block is arranged on the bottom surface of the accommodating groove 12 can be that a plurality of plug connectors 17 are arranged on the bottom surface of the accommodating groove 12, the plurality of plug connectors 17 are distributed around the convex part 13 along the circumferential interval of the convex part 13, a plurality of insertion grooves 18 are arranged on the lower surface of the annular supporting block along the circumferential interval of the annular supporting block, the number of the plug connectors 17 is the same as that of the insertion grooves 18 on the annular supporting block, and the plurality of insertion grooves 18 on the annular supporting block are used for allowing the plurality of plug connectors 17 to be inserted in a one-to-one correspondence manner.
In the semiconductor process, the annular supporting block supports the edge of the wafer 10, the height of the annular supporting block is larger than the distance from the central point of the arc surface 14 to the bottom surface of the accommodating groove 12, so that when the annular supporting block supports the wafer 10, a gap can be formed between the wafer 10 and the arc surface 14, and the upper surface of the annular supporting block is located below the notch end surface 23 of the accommodating groove 12, so that the wafer 10 can be located in the accommodating groove 12 in the semiconductor process.
Optionally, in the second embodiment, the distance between the central point of the arc surface 14 and the upper surface of the annular supporting block is in the range of 0.45mm to 0.55 mm.
Alternatively, in the second embodiment, the distance in the vertical direction between the upper surface of the annular support block and the notch end surface 23 is in the range of 0.6mm to 1 mm.
Optionally, in the second embodiment, the length of the upper surface of the annular supporting block in the radial direction of the arc surface 14 is within a range from 6mm to 12mm, so that when the annular supporting block supports the edge of the wafer 10, the contact range between the upper surface of the annular supporting block and the edge of the wafer 10 in the radial direction of the wafer 10 is within a range from 6mm to 12mm, which can ensure that sufficient friction force exists between the wafer 10 and the annular supporting block, so as to reduce the risk that the position of the wafer 10 on the annular supporting block is shifted during the semiconductor processing process, and can ensure that the temperature of the edge of the wafer 10 is effectively reduced, so that the temperature uniformity of the wafer 10 is effectively improved during the semiconductor processing process.
Optionally, in the second embodiment, the thickness of the annular support block is in the range of 1.5mm to 2 mm. In practical applications, the thickness of the tray body 11 is strictly required by the semiconductor processing equipment, and therefore, the greater the thickness of the annular supporting block, the greater the depth of the accommodating groove 12, the smaller the thickness of the portion of the tray body 11 located below the accommodating groove 12, and the strength of the annular supporting block is reduced by the reduction of the thickness of the annular supporting block, and the strength of the tray body 11 is reduced by the reduction of the thickness of the portion of the tray body 11 located below the accommodating groove 12. By setting the thickness of the annular support block within the range of 1.5mm to 2mm, not only the annular support block can have sufficient strength to support the wafer 10, but also the thickness of the portion of the tray body 11 located below the accommodation groove 12 can be prevented from being excessively small, so that the tray body 11 has sufficient strength.
In the second embodiment, a plurality of thimble holes 21 for the thimble to pass through are arranged on the bottom surface of the accommodating groove 12, and the plurality of thimble holes 21 are distributed at intervals along the circumferential direction of the arc surface 14; the annular supporting block is provided with a plurality of through holes for the ejector pins to pass through, and the through holes are arranged corresponding to the ejector pins.
Specifically, in the semiconductor process, each thimble can be lifted in the corresponding thimble hole 21 so as to lift the wafer 10 from the manipulator or the annular support block, or the wafer 10 is placed on the annular support block, and the thimble can pass through the through hole in the lifting process by arranging the through hole corresponding to the thimble hole 21 on the annular support block, so that the interference of the annular support block on the lifting of the thimble is avoided, and the stability of the semiconductor processing process is improved.
In the second embodiment, a predetermined gap 25 is provided between the outer side wall of the support member 15 and the inner peripheral wall of the receiving groove 12. That is, in the second embodiment, the outer circumferential wall of the annular support block and the inner circumferential wall of the receiving groove 12 have a predetermined gap 25 therebetween.
Therefore, the distance from the edge of the wafer 10 to the inner peripheral wall of the accommodating groove 12 can be increased, the edge of the wafer 10 is reduced in the semiconductor process and is subjected to heat radiated from the inner peripheral wall of the accommodating groove 12, the temperature uniformity of the wafer 10 in the semiconductor process can be further improved, the resistivity uniformity of an epitaxial layer is further improved, the interference between the wafer 10 and the inner peripheral wall of the accommodating groove 12 can be avoided when the wafer 10 is placed on an annular supporting block, and the placing position of the wafer 10 can be adjusted conveniently.
Optionally, the preset gap 25 is in the range of 1mm-2 mm.
As another technical solution, this embodiment further provides a semiconductor processing apparatus, which includes the tray provided in this embodiment.
According to the semiconductor processing equipment provided by the embodiment, the tray of the semiconductor processing equipment provided by the embodiment is used for bearing the wafer 10, so that the temperature uniformity of the wafer 10 in the semiconductor process in the process can be improved, and the resistivity uniformity of the epitaxial layer is further improved.
In summary, the tray of the semiconductor processing apparatus and the semiconductor processing apparatus provided in this embodiment can improve the temperature uniformity of the wafer 10 during the semiconductor process, thereby improving the resistivity uniformity of the epitaxial layer.
It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A tray of semiconductor processing equipment is characterized by comprising a tray body and a supporting component,
The tray body is provided with an accommodating groove for accommodating a wafer, the accommodating groove comprises a convex part positioned on the bottom surface of the accommodating groove, the upper surface of the convex part is an arc surface, and the distance between a point on the arc surface and the bottom surface of the accommodating groove is gradually reduced from the center of the arc surface to the edge so as to reduce the temperature difference between the center of the tray and the edge of the tray;
the supporting component is arranged on the tray body and surrounds the periphery of the arc surface, and the supporting component is used for supporting the wafer and enabling a gap to be reserved between the wafer and the arc surface so as to reduce the heat conduction efficiency of the tray to the edge of the wafer.
2. The tray of claim 1, wherein the support member is removably coupled to the tray body.
3. The tray of claim 2, wherein the tray body is provided with a plurality of connectors, and the lower surface of the support member is provided with insertion grooves for receiving the connectors, the insertion grooves corresponding to the connectors.
4. The tray of a semiconductor processing apparatus according to claim 1, wherein the supporting member is provided on a bottom surface of the receiving groove and includes a plurality of sector-shaped supporting blocks spaced apart in a circumferential direction of the convex portion; the height of each fan-shaped supporting block is larger than the distance from the central point of the arc surface to the bottom surface of the accommodating groove, and the upper surface of each fan-shaped supporting block is positioned below the end surface of the notch of the accommodating groove.
5. The tray of claim 4, wherein a plurality of pin holes for pins to pass through are formed in a bottom surface of the accommodating groove, and the plurality of pin holes are circumferentially spaced along the arc surface;
the fan-shaped supporting blocks are correspondingly arranged with the thimble holes, and the fan-shaped supporting blocks are arranged between two adjacent thimble holes.
6. The tray of claim 1, wherein the supporting member is disposed on a bottom surface of the receiving groove and includes an annular supporting block disposed around the protrusion; and the height of the annular supporting block is greater than the distance from the central point of the arc surface to the bottom surface of the accommodating groove, and the upper surface of the annular supporting block is positioned below the end surface of the notch of the accommodating groove.
7. The tray of claim 6, wherein a plurality of pin holes for pins to pass through are formed in a bottom surface of the accommodating groove, and the plurality of pin holes are circumferentially spaced along the arc surface;
the annular supporting block is provided with a plurality of through holes for the ejector pins to pass through, and the through holes are arranged corresponding to the ejector pin holes.
8. The tray of a semiconductor processing apparatus according to any one of claims 4 to 7, wherein a distance between a center point of the circular arc surface and an upper surface of the sector-shaped support block or the ring-shaped support block is in a range of 0.45mm to 0.55 mm.
9. The tray of a semiconductor processing apparatus according to any one of claims 1 to 7, wherein a predetermined gap is provided between an outer sidewall of the supporting member and an inner peripheral wall of the receiving groove.
10. A semiconductor processing apparatus, characterized in that it comprises a tray according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010704561.5A CN111863700A (en) | 2020-07-21 | 2020-07-21 | Tray of semiconductor processing equipment and semiconductor processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010704561.5A CN111863700A (en) | 2020-07-21 | 2020-07-21 | Tray of semiconductor processing equipment and semiconductor processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111863700A true CN111863700A (en) | 2020-10-30 |
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ID=73000733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010704561.5A Pending CN111863700A (en) | 2020-07-21 | 2020-07-21 | Tray of semiconductor processing equipment and semiconductor processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111863700A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113622020A (en) * | 2021-06-17 | 2021-11-09 | 华灿光电（浙江）有限公司 | Epitaxial tray for improving uniformity of epitaxial wafer and preparation method thereof |
| CN114188437A (en) * | 2021-10-26 | 2022-03-15 | 晋能清洁能源科技股份公司 | Plate type support plate structure for amorphous silicon deposition |
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| CN1618117A (en) * | 2001-11-30 | 2005-05-18 | 信越半导体株式会社 | Susceptor, vapor phase growth device, device and method of manufacturing epitaxial wafer, and epitaxial wafer |
| CN103730395A (en) * | 2012-10-11 | 2014-04-16 | 晶元光电股份有限公司 | Wafer carrier |
| US20170175262A1 (en) * | 2015-12-16 | 2017-06-22 | Fuji Electric Co., Ltd. | Epitaxial growth apparatus, epitaxial growth method, and manufacturing method of semiconductor element |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1618117A (en) * | 2001-11-30 | 2005-05-18 | 信越半导体株式会社 | Susceptor, vapor phase growth device, device and method of manufacturing epitaxial wafer, and epitaxial wafer |
| CN103730395A (en) * | 2012-10-11 | 2014-04-16 | 晶元光电股份有限公司 | Wafer carrier |
| US20170175262A1 (en) * | 2015-12-16 | 2017-06-22 | Fuji Electric Co., Ltd. | Epitaxial growth apparatus, epitaxial growth method, and manufacturing method of semiconductor element |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113622020A (en) * | 2021-06-17 | 2021-11-09 | 华灿光电（浙江）有限公司 | Epitaxial tray for improving uniformity of epitaxial wafer and preparation method thereof |
| CN114188437A (en) * | 2021-10-26 | 2022-03-15 | 晋能清洁能源科技股份公司 | Plate type support plate structure for amorphous silicon deposition |
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