CN111817562A

CN111817562A - Buck type DC-DC converter

Info

Publication number: CN111817562A
Application number: CN202010651806.2A
Authority: CN
Inventors: 谢凌寒; 巩令风; 黄星星; 王国鹏; 汪东
Original assignee: Wuxi Etek Microelectronics Co ltd
Current assignee: Wuxi Etek Microelectronics Co ltd
Priority date: 2020-07-08
Filing date: 2020-07-08
Publication date: 2020-10-23
Anticipated expiration: 2040-07-08
Also published as: WO2022007460A1; KR102641551B1; KR20220146489A; CN111817562B

Abstract

The invention provides a step-down dc-dc converter, further comprising: an output circuit for converting an input voltage into an output voltage, including a first power transistor and a second power transistor connected in series between an input terminal and a ground terminal; a voltage feedback circuit for obtaining a feedback voltage based on the output voltage; a ramp voltage generation circuit that generates a ramp voltage whose voltage gradually increases from an initial voltage when the first power transistor is switched from on to off, the ramp voltage being gradually decreased to the initial voltage when it is detected that a current of the inductor reaches a zero point; and a first comparison input end of the first comparator receives a first voltage sum obtained by adding the ramp voltage and a first reference voltage, and a second comparison input end of the first comparator receives a second voltage sum obtained by adding the ripple voltage and the feedback voltage. Therefore, the error caused by slope compensation can be eliminated, and the accuracy of the output voltage can be improved.

Description

Buck type DC-DC converter

Technical Field

The invention relates to the technical field of power conversion, in particular to a voltage reduction type direct current-direct current converter.

Background

Although a Constant on-time (COT) buck direct current-direct current (DC-DC) converter with a traditional structure has the advantages of good transient response, simple internal circuit, less required peripheral devices and the like, the converter also has the defect of low output voltage precision. One important reason for the accuracy of the output voltage is the error caused by the slope compensation.

Fig. 1 is a schematic circuit diagram of a conventional COT buck dc-dc converter. As shown in fig. 1, the compensation ramp voltage generated by the ramp voltage generating circuit is set to zero when the first power transistor (HSD _ FET, also sometimes referred to as a high power transistor) is turned on. As shown in fig. 2, during the very light load, after the first power transistor is turned on, the first power transistor remains off for a very long time, and the compensation ramp voltage Vslope is increased until the maximum voltage limit value Vslope _ max.

According to the principle of the conventional COT buck dc-dc converter, the first power transistor HSD _ FET is turned on when the following equation is satisfied.

VFB+Vrip＜VREF_1+Vslope

Obviously, the increase of the compensation ramp voltage Vslope will cause the feedback voltage VFB to increase, thereby causing the output voltage Vout to be higher than the set value during light load.

In addition, whether a voltage-mode direct current-direct current converter, a current-mode direct current-direct current converter or a COT direct current-direct current converter, when a current load is instantly jumped from a heavy load to a light load, the output voltage inevitably has a large overshoot voltage. Because the transient response performance of the COT DC-DC converter is superior to that of a voltage-mode DC-DC converter and a current-mode DC-DC converter, the output overshoot voltage of the COT DC-DC converter is lower than that of the voltage-mode DC-DC converter and the current-mode DC-DC converter. Even in the COT DC-DC converter, when the load is suddenly changed from heavy load to light load or even zero, the energy stored in the inductor is released to the output capacitor, so that the output voltage is far higher than the set value. To reduce the duration of the overshoot voltage, a lower value feedback resistor is used. The smaller the resistance value of the feedback resistor, the larger the current thereof. Therefore, the output voltage can be slowly reduced to the set value through the feedback resistor with lower resistance value. Even then, it takes a long time for the output voltage to return to the set value. Meanwhile, the static power consumption of the system is increased due to the use of the feedback resistor with a lower resistance value.

Therefore, there is a need for an improved solution to overcome the above problems.

Disclosure of Invention

The invention aims to provide a voltage reduction type direct current-direct current converter, which can solve errors caused by slope compensation and improve the accuracy of output voltage.

To achieve the object, according to one aspect of the present invention, there is provided a buck dc-dc converter, further comprising: an output circuit for converting an input voltage into an output voltage, including a first power transistor and a second power transistor connected in series between an input terminal and a ground terminal; a voltage feedback circuit for obtaining a feedback voltage based on the output voltage; a ripple generating circuit for generating a ripple voltage related to a current of the inductor; the current zero detection circuit is used for detecting the zero of the current of the inductor and generating a current zero signal; a ramp voltage generation circuit that generates a ramp voltage whose voltage gradually increases from an initial voltage when the first power transistor is switched from on to off, the ramp voltage being gradually decreased to the initial voltage when the current zero point detection circuit detects that the current of the inductor reaches a zero point; and the first comparator comprises a first comparison input end and a second comparison input end, the first comparison input end receives a first voltage sum obtained by adding the ramp voltage and a first reference voltage, the second comparison input end receives a second voltage sum obtained by adding the ripple voltage and the feedback voltage, the on and off of the first power transistor and the second power transistor are controlled based on a comparison result of the first comparator, the first power transistor and the second power transistor are not simultaneously turned on, and in addition, when the current zero point detection circuit detects that the current of the inductor reaches a zero point, the second power transistor is controlled to be turned off.

Compared with the prior art, the ramp voltage does not rise any more when the current of the inductor reaches zero, but gradually decreases to zero, so that under the condition of light load, when the first power transistor is conducted, the ramp voltage Vslope is already reduced to zero, the error caused by ramp compensation can be eliminated, and the accuracy of the output voltage can be improved.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional COT buck dc-dc converter;

FIG. 2 is a timing diagram of a portion of signals of the COT buck DC-DC converter of FIG. 1;

FIG. 3 is a schematic circuit diagram of a COT buck DC-DC converter of the present invention in one embodiment;

FIG. 4 is a circuit diagram of the ramp voltage generation circuit of FIG. 3 in one embodiment;

FIG. 5 is a timing diagram of signals of a portion of the COT buck DC-DC converter of FIG. 3 and the ramp voltage generating circuit of FIG. 4;

FIG. 6 shows the output voltage and load current waveforms of the COT buck DC-DC converter of the present invention;

FIG. 7 illustrates output voltage and load current waveforms of the conventional COT buck DC-DC converter of FIG. 1;

FIG. 8 is a circuit diagram of the discharge control logic circuit of FIG. 3 in one embodiment;

FIG. 9 shows the output voltage overshoot and recovery waveforms of the COT buck-type DC-DC converter of the present invention;

fig. 10 illustrates output voltage overshoot and recovery waveforms of the conventional COT buck-type dc-dc converter in fig. 1.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.

The invention provides a voltage reduction type direct current-direct current converter which can solve the problem that large current transient response overshoots are long in duration.

Fig. 3 is a circuit schematic diagram of a buck dc-dc converter 300 in accordance with an embodiment of the present invention. As shown in fig. 3, the buck dc-dc converter 300 includes an output circuit 310, a voltage feedback circuit 320, a discharge path 330, a discharge control circuit 340, a ripple generation circuit 350, a current zero detection circuit 360, a first comparator (or PWM comparator) 370, an on-time signal generation circuit 380, a logic circuit 390, a ramp voltage generation circuit 410, a first driving circuit 420, and a second driving circuit 430.

The output circuit 310 is used for converting an input voltage VIN into an output voltage Vout. In one embodiment, the output voltage Vout is lower than the input voltage VIN, and therefore may be referred to as a buck dc-dc converter. As shown in fig. 3, in one embodiment, the output circuit 310 includes a first power transistor HSD _ FET and a second power transistor LSD _ FET connected in series between an input terminal and a ground terminal, and a node between the first power transistor HSD _ FET and the second power transistor LSD _ FET is referred to as an intermediate node SW. The output circuit 310 includes an input terminal that receives an input voltage VIN and an output terminal that provides an output voltage Vout, the input terminal also being labeled VIN and the output terminal also being labeled Vout. The output circuit 310 may further include an inductor L and an output capacitor Co, the first power transistor HSD _ FET and the second power transistor LSD _ FET being controlled to be alternately turned on to implement voltage conversion. As a basic principle, the first power transistor HSD _ FET and the second power transistor LSD _ FET are not turned on simultaneously, that is, when the first power transistor HSD _ FET is turned on, the second power transistor LSD _ FET is turned off, and when the second power transistor LSD _ FET is turned on, the first power transistor HSD _ FET is turned off. Preferably, the inductor L may be disposed off-chip, and other circuit portions may be integrated on-chip.

The voltage feedback circuit 320 is used for obtaining a feedback voltage VFB based on the output voltage Vout. As shown in fig. 3, in one embodiment, the voltage feedback circuit 320 includes two voltage dividing resistors Rf1 and Rf2 connected in series between the output voltage Vout and ground, and the voltage at the middle node of the two voltage dividing resistors is the feedback voltage VFB. The feedback voltage VFB is capable of reflecting the magnitude of the output voltage Vout.

The discharge path 330 is coupled between the output circuit and the ground and can be controlled to discharge. As shown in fig. 3, in one embodiment, the discharge path 330 includes a first resistor R1 and a discharge switch S1 connected in series between the intermediate node SW of the output circuit and ground GND. In another embodiment, the discharge path 330 may also be coupled to the output terminal Vout to achieve the same effect. Since the inductor L1 is located off-chip, the discharge path 330 is typically coupled to the intermediate node, and it should be noted that the coupling includes direct and indirect connections.

The discharge control circuit 340 controls the discharge path 330 to discharge when the feedback voltage VFB obtained by the voltage feedback circuit 320 is greater than the second reference voltage VREF _2 and the first power transistor HSD _ FET is turned off, and controls the discharge path 330 to prohibit discharging when the feedback voltage VFB obtained by the voltage feedback circuit 320 is less than the second reference voltage VREF _2 or the first power transistor HSD _ FET is turned on. In one embodiment, the discharge control circuit 340 controls the discharge path 330 to discharge by controlling the discharge switch S1 to be turned on, and the discharge control circuit 340 controls the discharge path 330 to inhibit discharge by controlling the discharge switch S1 to be turned off. The second reference voltage VREF _2 is greater than the first reference voltage VREF _1, such as equal to VREF _1 × 104%, where VREF _1 is the first reference voltage, which will be described in detail later.

As shown in fig. 3, the discharge control circuit 340 includes a second comparator 341 and a discharge control logic circuit 342. The second comparator 341 is configured to compare the feedback voltage VFB with the second reference voltage VREF _2 and provide the comparison result to the discharge control logic circuit 342, and the discharge control logic circuit 342 controls the discharge path 330 based ON the control signal (signal PWM and signal HSD _ ON) of the first power transistor HSD _ FET and the comparison result of the second comparator 341.

The ripple generation circuit 350 is used for generating a current I reflecting the inductance L in the output circuit 310_LThe ripple voltage Vrip. The current of the intermediate node SW and the current I of the inductor L_LIs consistent, it is therefore preferable to characterize the current I of the inductor L by the current of the intermediate node SW_LIn this context, the current I of the inductor L is sometimes replaced by the current of the intermediate node SW_LFor explanation. Specifically, the ripple generation circuit 350 obtains the ripple voltage Vrip by detecting the current of the intermediate node SW. The waveform of the ripple voltage Vrip and the current I of the inductor L_LThe waveforms of (a) are consistent. The current ZERO point detection circuit 360 is configured to detect a ZERO point of the current of the intermediate node SW and generate a current ZERO point signal ZERO _ CURT.

The ramp voltage generating circuit 410 generates a ramp voltage vslope whose voltage gradually increases from an initial voltage when the first power transistor HSD _ FET is switched from on to off, and the ramp voltage vslope gradually decreases to the initial voltage when the current zero point detecting circuit 360 detects that the current of the intermediate node SW reaches the zero point. As shown in fig. 5, the ramp voltage vslope generated by the conventional ramp voltage generating circuit in fig. 1 will continue to gradually increase to the maximum value vslope _ max (as shown in the dotted line of fig. 5) when the current of the intermediate node SW reaches the zero point, whereas the ramp voltage vslope in the present invention will gradually decrease to the initial voltage when the current of the intermediate node SW reaches the zero point. Specifically, the initial voltage may be 0.

The first comparator (or PWM comparator) 370 includes a first comparison input terminal and a second comparison input terminal. The first comparison input end receives the ramp voltage Vslope and the first comparison input endThe second comparison input end receives a second voltage Vrip + VFB obtained by adding the ripple voltage Vrip and the feedback voltage VFB. The first power transistor HSD _ FET and the second power transistor LSD _ FET are controlled to be turned on and off based on a comparison result PWM (which may also be referred to as a PWM control signal) of the first comparator 370. In addition, the current I of the intermediate node SW is detected by the current zero point detection circuit 360_LWhen the current (or called as the inductor current) reaches zero, the second power transistor LSD _ FET is controlled to be turned off, and the second power transistor LSD _ FET is turned on again until the first power transistor on time of the next cycle is over.

The on-time signal generating circuit 380 generates a predetermined on-time control signal Ton according to the comparison result of the first comparator 370, wherein when the comparison result PWM of the first comparator 370 changes from inactive to active, the predetermined on-time control signal Ton changes to active, and changes to inactive after lasting for a predetermined on-time. The predetermined on-time may be timed by a timer. The on-time signal generation circuit 380 may also be referred to as an on-time one shot (T)_ONOne-Shot) circuit. Active and inactive here refer to two logic level states, typically an active logic level refers to a logic level that causes the first power transistor to turn on, and an inactive logic level refers to a logic level that causes the first power transistor to turn off.

The logic circuit 390 generates a first control signal HSD _ ON controlling the first power transistor and a second control signal LSD _ ON controlling the second power transistor according to the predetermined ON-period control signal Ton, the PWM control signal, and the current ZERO signal ZERO _ CURT of the ON-time signal generation circuit. When the preset ON-time control signal Ton is effective, a first control signal HSD _ ON is output to control the first power transistor HSD _ FET to be turned ON, and a second control signal is output to control the second power transistor LSD _ FET to be turned off. When the preset ON-time control signal Ton is invalid, outputting a first control signal HSD _ ON to control the first power transistor HSD _ FET to be cut off, when the preset ON-time control signal Ton is invalid and the current of the intermediate node SW is not zero, outputting a second control signal to control the second power transistor LSD _ FET to be switched ON, and when the preset ON-time control signal Ton is invalid and the current of the intermediate node SW is zero, outputting the second control signal to control the second power transistor LSD _ FET to be cut off.

The first driving circuit 420 drives the first power transistor HSD _ FET to be turned on and off based on the first control signal. The second driving circuit 430 drives the second power transistor LSD _ FET to be turned on and off based on the second control signal.

As shown in fig. 3, the discharge control logic circuit 342 controls the discharge path 330 based ON the comparison result PWM of the first comparator, the comparison result VFB _ H of the second comparator, and the first control signal HSD _ ON output from the logic circuit 390. Specifically, the discharge control logic circuit 342 determines whether the first power transistor starts to be turned ON based ON the inactive-to-active transition edge of the comparison result PWM of the first comparator, and determines whether the first power transistor starts to be turned off based ON the active-to-inactive transition edge of the first control signal HSD _ ON outputted from the logic circuit 390, so as to control the discharge switch S1 to be turned ON or off. In principle, the discharge switch S1 should be turned off before the first power transistor is turned on and turned on after the first power transistor is turned off.

Fig. 8 is a circuit diagram of the discharge control logic 342 of fig. 3 in one embodiment. The discharge control logic circuit 342 comprises NOT gates NOT1 AND NOT2, AND gates AND1 AND2, AND a D flip-flop, AND the connection relationship is as shown in fig. 8.

Fig. 4 is a circuit diagram of the ramp voltage generating circuit 410 in fig. 3 in one embodiment. As shown in fig. 4, the ramp voltage generating circuit 410 includes: capacitor C41 and charging current source I₁A ramp voltage output circuit 411, a release path 412 connected in parallel with the capacitor C41, and a charge control circuit 413.

The ramp voltage output circuit 411 obtains and outputs a ramp voltage vslope based on the energy storage voltage of the capacitor C41. The charging control circuit 413 is configured to switch the first power transistor HSD _ FET from ON to off (i.e., the first control signal HSD _ ON transitions from active to inactive, such as from highLevel jump to low level), the third switches S3 and S4 are controlled to be turned off, and the charging current source I₁The capacitor C41 is charged, and Vslope gradually increases from the time T1 as shown in FIG. 5, and the inductor current I is then obtained_LGradually decreasing, when the current zero point detection circuit 360 detects that the current of the intermediate node SW reaches zero point, i.e. at time T2, the release path 412 is conducted to discharge the capacitor C41 to gradually reach 0. The release path 412 includes a first release branch and a second release branch. The first release branch comprises a first discharge current source I connected in series₂And a first release switch S₄₁The second release branch circuit comprises a second discharge current source I connected in series₃And a second release switch S₂. First release switch S₄₁Controlled by a current ZERO signal ZERO _ CURT, a second release switch S₂And the current ZERO signal ZERO _ CURT passes through the delay unit and then is controlled. When the first power transistor HSD _ FET is switched from off to ON (i.e., the first control signal HSD _ ON transitions from inactive to active, such as from low to high), the charge control circuit 413 controls the third switches S3 and S4 to be turned ON, so as to completely release the voltage of the capacitor C41 to 0.

The ramp voltage output circuit 411 includes: NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and resistors R41 and R42. MN1 has its source connected to capacitor C41, its gate connected to MN2 gate and MN1 drain, MN1 drain connected to charging current source I₁Are connected. The source of MN2 is grounded through a resistor R41, the drain of MN2 is connected with the drain and the gate of MP1, the gate of MP1 is connected with the gate of MP2, the sources of MP1 and MP2 are connected with the power supply, the drain of MP2 is grounded through a resistor R42, and the non-grounded end of R42 is an output end.

Fig. 5 is a timing diagram of signals of a part of the COT buck dc-dc converter in fig. 3 and the ramp voltage generating circuit in fig. 4. As shown in fig. 5, when the first control signal HSD _ ON is at a high level, the first power transistor is turned ON, the second power transistor is turned off, the voltage at the intermediate node SW is high, and the current I of the inductor L is high_LI.e., the current of the intermediate node SW gradually increases, at which time the switches S3 and S4 in fig. 4 are turned on, Vslope is 0. First control signalWhen the HSD _ ON jumps to a low level, the first power transistor is turned off, the second power transistor is turned ON, the voltage of the intermediate node SW is 0, and the current I of the inductor L is_LDecreasing gradually until 0, at which time switches S3 and S4 in fig. 4 are open and Vslope gradually increases. Current I of inductor L_LWhen the current ZERO point signal ZERO _ CURT is changed to high level when reaching 0, the switches S41 and S2 are turned on successively, and the release path 412 is turned on to discharge the capacitor C41 to gradually reach 0.

In the present invention, when the current of the inductor L is reduced to zero in the phase in which the first power transistor is turned off, the ramp amount is kept substantially constant, and the ramp amount is slowly reduced to zero through about 0.5 us. In the present invention, the ramp voltage Vslope has dropped to zero when the first power transistor is turned on under light load conditions. So that when the following equation is satisfied,

VFB+Vrip＜VREF_1

namely, it is

VFB＜VREF_1-Vrip

Obviously, under light load, VFB is lower than the conventional scheme, that is, the output voltage is lower than the conventional scheme under light load, which can improve the accuracy of the output voltage.

Fig. 6 shows waveforms of the output voltage and the load current of the COT buck dc-dc converter according to the present invention, and it can be seen that the output voltage changes from about 1.02V to 1.01V when the load current changes from 0 to 3A.

Fig. 7 shows waveforms of an output voltage and a load current of the conventional COT buck-type dc-dc converter of fig. 1, and it can be seen that the output voltage changes approximately from 1.038V to 1.01V when the load current changes from 0 to 3A. Obviously, the invention obviously improves the load regulation rate of output and improves the precision of output voltage.

When the load large current suddenly drops to zero, the output voltage Vout will overshoot greatly, and there is no discharge path for the charge, so that the high voltage at the output terminal will be maintained for a long time.

In the present invention, after the output voltage Vout exceeds 4% of the rated voltage (the first reference voltage corresponds to the output voltage being the rated voltage), and the HSD _ ON signal is low, the discharging path of the output terminal Vout is opened, i.e. the switch S1 in fig. 3. When the PWM signal goes low, meaning that the first power transistor is to be turned on, switch S1 in figure 3 is turned off,

generally, the R1 resistor in fig. 3 can be set to a value as desired. The R1 in fig. 3 of the present invention can be about 110ohm, and when the overshoot is about 200mV, the output capacitor Co is 40uF, the bleed current is about 9.1mA, and the output recovers to the set value of 1V, the required time is:

if the invention is not used, the discharge can only be made through the feedback resistors Rf1 and Rf2 in fig. 3. In order to reduce the static power consumption of the system, the resistances Rf1 and Rf2 are not too small, and the current is usually controlled at 70uA or even lower.

Fig. 10 shows the overshoot and recovery waveforms of the output voltage of the conventional COT buck-type dc-dc converter in fig. 1, wherein the output voltage is maintained at 1.186V after about 8 ms.

The present invention has one or more of the following advantages:

1) aiming at the problem that the output voltage precision of the traditional COT buck-type direct current-direct current converter is poor, the reason is found, namely, the output voltage is higher due to overlarge ramp compensation during light load. When the low-order power tube (the second power transistor) is zero, the ramp compensation quantity is gradually reduced until the ramp compensation quantity is zero. Therefore, the influence of upward drift of the output voltage caused by the ramp compensation amount in light load is eliminated, and the load regulation rate of the system is improved.

2) Generally, when a load of a large-current step-down dc-dc converter jumps from a heavy load to a light load or no load instantaneously, the output voltage of the large-current step-down dc-dc converter has a large overshoot, and the overshoot lasts for a long time. In the present invention, when the output voltage exceeds the set value by 4% and the high-side power transistor (the first power transistor) is in an off state, the current leakage path (i.e., the discharge path 330) is opened. When the output voltage recovers to the set value and the high-order power tube is about to turn on, the current leakage path (i.e. the discharge path 330) is turned off. This greatly reduces the overshoot duration of the output voltage. This allows current to be bled off without relying on a small output feedback resistance. A larger output feedback resistance can be used to reduce the quiescent current of the system.

In the present invention, the terms "connect", "connecting", "coupling", etc. indicate electrical connection, and if not specifically stated, indicate direct or indirect electrical connection, and the indirect connection includes connection through electronic components or units such as resistors, capacitors, inductors, transistors, and filters.

The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.

Claims

1. A buck dc-dc converter, comprising:

an output circuit for converting an input voltage into an output voltage, including a first power transistor and a second power transistor connected in series between an input terminal and a ground terminal;

a voltage feedback circuit for obtaining a feedback voltage based on the output voltage;

a ripple generating circuit for generating a ripple voltage related to a current of the inductor;

the current zero detection circuit is used for detecting the zero of the current of the inductor and generating a current zero signal;

a ramp voltage generation circuit that generates a ramp voltage whose voltage gradually increases from an initial voltage when the first power transistor is switched from on to off, the ramp voltage being gradually decreased to the initial voltage when the current zero point detection circuit detects that the current of the inductor reaches a zero point;

a first comparator including a first comparison input terminal receiving a first voltage sum obtained by adding the ramp voltage and a first reference voltage, and a second comparison input terminal receiving a second voltage sum obtained by adding the ripple voltage and the feedback voltage,

and the first power transistor and the second power transistor are controlled to be switched on and off based on the comparison result of the first comparator, the first power transistor and the second power transistor are not switched on simultaneously, and the second power transistor is controlled to be switched off when the current zero point detection circuit detects that the current of the inductor reaches a zero point.

2. A buck dc-dc converter according to claim 1, further comprising:

a discharge controlled discharge path coupled between the output circuit and ground;

and the discharge control circuit controls the discharge path to discharge the output circuit when the feedback voltage obtained by the voltage feedback circuit is greater than a second reference voltage and the first power transistor is turned off, and controls the discharge path to prohibit discharge when the feedback voltage obtained by the voltage feedback circuit is less than the second reference voltage or the first power transistor is turned on.

3. Buck-type DC-DC converter according to claim 2,

the discharge path comprises a first resistor and a discharge switch which are connected in series between an output circuit and a ground terminal, the discharge control circuit controls the discharge path to discharge by controlling the discharge switch to be switched on, and the discharge control circuit controls the discharge path to inhibit discharge by controlling the discharge switch to be switched off.

4. A buck dc-dc converter according to claim 2, wherein the discharge control circuit includes a second comparator for comparing the feedback voltage with the second reference voltage and providing a comparison result to the discharge control logic circuit, and a discharge control logic circuit controlling the discharge path based on the control signal of the first power transistor and the comparison result of the second comparator.

5. A buck dc-dc converter according to claim 2, wherein a node between the first power transistor and the second power transistor is referred to as an intermediate node, and the discharge path is coupled between the intermediate node and ground.

6. A buck dc-dc converter according to claim 1, further comprising:

the on-time signal generating circuit generates a preset on-time control signal according to the comparison result of the first comparator and the preset on-time, wherein when the comparison result of the first comparator changes from invalid to valid, the preset on-time control signal jumps to be valid, and jumps to be invalid after the preset on-time is continued;

a logic circuit, which generates a first control signal for controlling the first power transistor and a second control signal for controlling the second power transistor according to a predetermined on-time control signal of the on-time signal generating circuit and the current zero point signal, wherein the first power transistor is controlled to be turned on when the predetermined on-time control signal is valid, the second power transistor is controlled to be turned off, the first power transistor is controlled to be turned off when the predetermined on-time control signal is invalid, the second power transistor is controlled to be turned on when the predetermined on-time control signal is invalid and the current of the inductor is not at zero point, and the second power transistor is controlled to be turned off when the predetermined on-time control signal is invalid and the current of the inductor reaches zero point;

a first drive circuit that drives on and off of the first power transistor based on a first control signal;

and a second driving circuit which drives the second power transistor to be turned on and off based on a second control signal.

7. A buck dc-dc converter according to claim 1, wherein the ramp voltage generating circuit comprises: a capacitor C41, a charging current source, a ramp voltage output circuit, a release path connected with the capacitor C41 in parallel and a charging control circuit,

a charge control circuit that causes the charge current source to charge the capacitor C41 when the first power transistor is switched from on to off, the discharge path being turned on to discharge the capacitor C41 when the current zero point detection circuit detects that the current of the inductor reaches a zero point,

the ramp voltage output circuit obtains and outputs a ramp voltage based on the energy storage voltage of the capacitor C41.

8. A buck dc-dc converter according to claim 7, wherein the release path comprises: a first release branch and a second release branch,

the first release branch comprises a first discharge current source and a first release switch which are connected in series,

the second release branch comprises a second discharge current source and a second release switch which are connected in series,

the first release switch is controlled by the current zero signal, and the first release switch is controlled by the current zero signal after passing through the delay unit.

9. A buck dc-dc converter according to claim 7, wherein the ramp voltage output circuit comprises: NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, resistors R41 and R42, a source of MN1 is connected with a capacitor C41, a gate of the capacitor is connected with a grid of MN2 and a drain of MN1, and a drain of the MN1 is connected with a charging current source I₁The source of the MN2 is grounded through a resistor R41, the drain of the MN2 is connected with the drain and the gate of the MP1, the gate of the MP1 is connected with the gate of the MP2, the source of the MP1 and the source of the MP2 are connected with the power supply, the drain of the MP2 is grounded through a resistor R42, and the non-grounded end of the R42 is an output end to output the ramp voltage.

10. A step-down dc-dc converter according to claim 1, wherein a node between the first power transistor and the second power transistor is referred to as an intermediate node SW, the output circuit further includes an inductor L connected between the intermediate node SW and the output terminal, and the current zero point detection circuit obtains a current of the inductor by detecting the current of the intermediate node SW, and further detects a zero point of the current of the inductor.