CN111816562B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111816562B
CN111816562B CN201910286474.XA CN201910286474A CN111816562B CN 111816562 B CN111816562 B CN 111816562B CN 201910286474 A CN201910286474 A CN 201910286474A CN 111816562 B CN111816562 B CN 111816562B
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layer
material layer
dielectric material
hard mask
forming
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CN111816562A (en
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蒋鑫
杨志勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a pseudo gate structure and a hard mask layer positioned on the top of the pseudo gate structure are formed on the substrate; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed by the pseudo gate structure; performing first planarization treatment on the dielectric material layer by taking the highest position at the top of the etching stop layer as a stop position; after the first planarization treatment is carried out, etching treatment is carried out on the etching stop layer and the dielectric material layer, and the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer are removed; and after etching treatment, carrying out second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo gate structure as a stop position, wherein the residual dielectric material layer is used as an interlayer dielectric layer. The embodiment of the invention is beneficial to improving the flatness of the top surface of the interlayer dielectric layer and reducing the probability of damaging the grid structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the development of high integration of semiconductor devices, the gate length of Metal Oxide Semiconductor (MOS) devices is being scaled down to smaller dimensions, and accordingly, the fabrication process of semiconductor devices is being continuously improved to meet the requirements of people on device performance.
Depending on the type and function of the semiconductor device, the number of wiring layers of the manufactured semiconductor device may be different. Semiconductor devices typically include a device layer on and within a semiconductor substrate, an interlayer dielectric layer (INTER LAYER DIELECTRIC, ILD) over the device layer, and a wiring structure within the interlayer dielectric layer for connecting active and passive devices within the device layer. The interlayer dielectric layer is generally made of an insulating material, so that short circuits between the active device or the passive device and the wiring forming the wiring structure can be avoided.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a pseudo gate structure is formed on the substrate, and a hard mask layer is formed on the top of the pseudo gate structure; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed by the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer; taking the highest position at the top of the etching stop layer as a stop position, and carrying out first planarization treatment on the dielectric material layer; after the first planarization treatment is carried out, etching treatment is carried out on the etching stop layer and the dielectric material layer, and the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer are removed; and after the etching treatment, taking the top of the pseudo gate structure as a stop position, carrying out second planarization treatment on the dielectric material layer and the hard mask layer, and taking the rest dielectric material layer as an interlayer dielectric layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a semiconductor structure formed by the foregoing method of forming.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the highest position of the top of the etching stop layer is taken as the stop position, and the dielectric material layer is subjected to first planarization, so that in the step of the first planarization, only the dielectric material layer is subjected to first planarization, and other film layer structures are not contacted, thereby being beneficial to preventing the problem of grinding difference caused by different pattern densities of all areas or different heights of the top surfaces of all film layer structures, reducing the probability of occurrence of a recess (dishing) problem on the top of the dielectric material layer, ensuring that the height consistency of the top of the dielectric material layer is better, reducing the thickness of the dielectric material layer required to be removed in the subsequent etching treatment, shortening the process time required by the etching treatment, easily removing different materials in the same step by adopting an anisotropic etching process, reducing the difference of etching amounts of the dielectric material layer in different pattern density areas, and further reducing the probability of occurrence of a side wall structure caused by the difference of the gate electrode structure after the etching treatment is completed, and further ensuring that the height consistency of the top of the remaining dielectric material layer is better and the dielectric material layer is also good, and the side wall structure is prevented from being lost due to the fact that the side wall structure is formed in the subsequent etching of the gate structure; in summary, the embodiment of the invention combines the first planarization treatment and the etching treatment, and can reduce the damage probability of the grid structure while improving the flatness of the top surface of the interlayer dielectric layer, thereby improving the performance of the semiconductor structure.
Drawings
Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIG. 8 is an electron microscope scan of a semiconductor structure;
Fig. 9 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
In the semiconductor field, the step of forming an interlayer dielectric layer generally includes: forming a dielectric material layer on the substrate with the exposed pseudo gate structure, wherein the dielectric material layer covers the top of the pseudo gate structure; and flattening the top of the dielectric material layer, wherein the residual dielectric material layer is used as an interlayer dielectric layer, and the interlayer dielectric layer exposes out of the top of the pseudo gate structure.
In the semiconductor field, the pattern density of different areas on the substrate is typically different, for example, according to the design requirements of the integrated circuit: the substrate generally comprises a pattern dense region and a pattern sparse region, compared with the pattern dense region, the number of the pseudo gate structures on the pattern sparse region is smaller, the distance between the adjacent pseudo gate structures is larger, and the size of an opening surrounded by the adjacent pseudo gate structures and the substrate is larger.
The larger the size of the opening, the faster the rate of planarization process, the more removed at the same time due to loading effects. Therefore, in the step of flattening the top of the dielectric material layer, the flattening rate of the dielectric material layer in the pattern sparse region is high, the height consistency of the top surface of the interlayer dielectric layer is poor, and the probability of occurrence of a dent problem on the top surface of the interlayer dielectric layer is high.
In order to solve the above-mentioned problems, a method for forming a semiconductor structure is proposed. Referring to fig. 1 to 7, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 1 is provided, a dummy gate structure 2 is formed on the substrate 1, a hard mask layer 3 is formed on top of the dummy gate structure 2, and a first etch stop layer 4 conformally covering the top and side walls of the hard mask layer 3, the side walls of the dummy gate structure 2, and the substrate 1 exposed by the dummy gate structure 2 is further formed on the substrate 1.
Referring to fig. 2, a bottom dielectric material layer 5 is formed on the substrate 1 where the dummy gate structure 2 is exposed, and the bottom dielectric material layer 5 covers the first etch stop layer 4 on the hard mask layer 3.
Referring to fig. 3, a portion of the bottom dielectric material layer 5 is etched, and a portion of the sidewall of the dummy gate structure 2 is exposed by the remaining bottom dielectric material layer 5.
Referring to fig. 4, a dummy gate structure 2 is formed to cover the remaining bottom dielectric material layer 5 and a second etch stop layer 6 is formed to cover the remaining bottom dielectric material layer 5.
Referring to fig. 5 and 6, a top dielectric material layer 7 is formed on the second etch stop layer 6; the top dielectric material layer 7 is planarized with the top of the second etch stop layer 6 on top of the dummy gate structure 2 as a stop position.
Referring to fig. 7, after the top dielectric material layer 7 is planarized, the top portion of the hard mask layer 3 is used as a stop position, and the top dielectric material layer 7, the second etching stop layer 6 and the first etching stop layer 4 higher than the hard mask layer 3 are polished and removed, and the remaining top dielectric material layer 7, the second etching stop layer 6 and the bottom dielectric material layer 5 between the adjacent dummy gate structures 2 are used as interlayer dielectric layers (not labeled).
In the forming method, by forming the second etching stop layer 6 on the remaining bottom dielectric material layer 5, the second etching stop layer 6 can define the position of the planarization treatment in the subsequent step of planarizing the top dielectric material layer 7, which is beneficial to reducing the problem of difference of planarization treatment rates caused by different pattern densities of each region, thereby improving the flatness and the height consistency of the top of the interlayer dielectric layer.
However, in the forming method, in the step of etching the bottom dielectric material layer 5 with a partial thickness, loss is easily generated on the first etching stop layer 4 located on the side wall of the pseudo gate structure 2, so that it is difficult to ensure that the first etching stop layer 4 protects the gate structure formed subsequently in the subsequent process, the probability of damaging the gate structure is high, and the performance of the formed semiconductor structure is poor.
Referring to fig. 8 in combination, there is shown an electron microscope scan of a semiconductor structure, and it is clear from the figure that the first etching stop layer4 is subject to a large loss, and is difficult to protect the side wall of the gate structure, and the formed semiconductor structure is not formed well.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a pseudo gate structure is formed on the substrate, and a hard mask layer is formed on the top of the pseudo gate structure; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed by the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer; taking the highest position at the top of the etching stop layer as a stop position, and carrying out first planarization treatment on the dielectric material layer; after the first planarization treatment is carried out, etching treatment is carried out on the etching stop layer and the dielectric material layer, and the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer are removed; and after the etching treatment, taking the top of the pseudo gate structure as a stop position, carrying out second planarization treatment on the dielectric material layer and the hard mask layer, and taking the rest dielectric material layer as an interlayer dielectric layer.
According to the embodiment of the invention, the highest position of the top of the etching stop layer is taken as a stop position, and the dielectric material layer is subjected to first planarization, so that in the step of the first planarization, only the dielectric material layer is subjected to first planarization, and other film layer structures are not contacted, so that the problem of grinding difference caused by different pattern densities of all areas or different heights of the top surfaces of all film layer structures is solved, the probability of occurrence of a recess problem on the top of the dielectric material layer is reduced, the consistency of the top of the dielectric material layer is better, the thickness of the dielectric material layer to be removed in the subsequent etching treatment can be reduced, the process time required by the etching treatment is shorter, and by adopting an anisotropic etching process, different materials are easy to remove in the same step, the difference of etching quantities of the dielectric material layers in areas with different pattern densities is reduced, therefore, after the etching treatment is finished, the consistency of the top of the residual dielectric material layer is also better, the probability of occurrence of a recess problem on the top of the dielectric material layer is reduced, the probability of the occurrence of a side wall of the gate structure is reduced, and the side wall of the gate structure is prevented from being lost due to the fact that the side wall of the gate structure is lost due to the fact that the difference of the gate structure is caused by the etching process difference on the top of the dielectric material layer is reduced; in summary, the embodiment of the invention combines the first planarization treatment and the etching treatment, and can reduce the damage probability of the grid structure while improving the flatness of the top surface of the interlayer dielectric layer, thereby improving the performance of the semiconductor structure.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 9 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 9, a substrate 100 is provided, a dummy gate structure 101 is formed on the substrate 100, and a hard mask layer 102 is formed on top of the dummy gate structure 101.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is used to form a planar transistor, and the substrate 100 includes only a substrate (not shown). In other embodiments, when the base is used to form a fin field effect transistor, the base includes a substrate and a fin protruding from the substrate, respectively.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
The dummy gate structure 101 is used to occupy a spatial position for a subsequent formation of a gate structure.
In this embodiment, the dummy gate structure 101 is a polysilicon gate structure, and the dummy gate structure 101 includes a dummy gate oxide layer 1011 on the substrate 100 and a dummy gate layer 1012 on the dummy gate oxide layer 1011.
The dummy gate layer 1012 may be made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. The material of the dummy gate oxide layer 1011 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy gate layer 1012 is polysilicon. The dummy gate oxide layer 1011 is made of silicon oxide.
In other embodiments, the dummy gate structure may also include only a dummy gate layer.
In this embodiment, a sidewall 103 is further formed on the sidewall of the dummy gate structure 101. The side wall 103 is used for protecting the side wall of the dummy gate structure 101, and the side wall 103 is also used for defining a formation region of the source-drain doped layer.
The material of the side wall 103 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride.
The side wall 103 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 103 has a stacked structure.
Specifically, the sidewall 103 is an ONO (Oxide Nitride Oxide, oxide-silicon nitride-oxide) structure, and the sidewall 103 includes a first sidewall (not shown) on the sidewall of the dummy gate structure 101, a second sidewall (not shown) on the sidewall of the first sidewall, and a third sidewall (not shown) on the sidewall of the second sidewall. Correspondingly, the material of the first side wall is silicon oxide, the material of the second side wall is silicon nitride, and the material of the third side wall is silicon oxide.
In the integrated circuit design, different film structures are formed on the sidewalls and the top surface of the dummy gate structure 101 of different devices according to design requirements. For example: in this embodiment, the substrate 100 includes an NMOS device region (not labeled) and a PMOS device region (not labeled), and the top surface and the sidewall of the dummy gate structure 101 on the substrate at the interface of the NMOS device region and the PMOS device region are further formed with a low dielectric constant layer 1051, and an N/P interface layer 1052 on the top surface and the sidewall of the low dielectric constant layer 1051. Wherein the low dielectric constant layer 1051 is used to reduce leakage current of the device, and the N/P interface layer 1052 is used to define boundaries of the NMOS device region and the PMOS device region.
The hard mask layer 102 is used as an etching mask for forming the dummy gate structure 101, and the hard mask layer 102 is also used for protecting the top of the dummy gate structure 101 in a subsequent process.
The subsequent process further comprises: forming an etching stop layer conformally covering the top and side walls of the hard mask layer 102, the side walls of the dummy gate structure 101, and the substrate 100 exposed by the dummy gate structure 101; forming a dielectric material layer on the substrate 100 exposed by the dummy gate structure 101, wherein the dielectric material layer covers the etching stop layer on the hard mask layer 102; taking the highest position at the top of the etching stop layer as a stop position, and carrying out first planarization treatment on the dielectric material layer; and after the first planarization treatment, etching the etching stop layer and the dielectric material layer by adopting an anisotropic etching process, and removing the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer 102.
The hard mask layer 102 is used for defining an etching stop position in the subsequent step of etching the etching stop layer and the dielectric material layer.
In this embodiment, the hard mask layer 102 includes a bottom hard mask layer 1021 and a top hard mask layer 1022 located on the bottom hard mask layer 1021, where the material of the bottom hard mask layer 1021 is silicon nitride, and the material of the top hard mask layer 1022 is silicon oxide.
The top surface of the top hard mask layer 1022 is used to define an etch stop location during subsequent steps of the etch stop and dielectric material layer 107. The material of the top hard mask layer 1022 is silicon oxide, which has good adhesion with other material film layers, so that the subsequent film layers can be formed conveniently.
The following step further includes a step of performing a third planarization process, where the bottom hard mask layer 1021 is used to define a stop position of the third planarization process, so as to improve the flatness of the top surface of the material layer to be polished after the third planarization process. The bottom hard mask layer 1021 is made of silicon nitride, and the density and hardness of the silicon nitride are high, so that the effect of defining the stop position of the third planarization process is remarkable.
In this embodiment, the source-drain doped layer 104 is further formed in the substrate 100 at two sides of the dummy gate structure 101. Specifically, the source-drain doped layer 104 is located in the substrate 100 at two sides of the dummy gate structure 101.
When forming an NMOS transistor, the source-drain doped layer 104 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming a PMOS transistor, the source-drain doped layer 104 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
Referring to fig. 10, an etch stop layer 106 is formed conformally covering the top and sidewalls of the hard mask layer 102, the sidewalls of the dummy gate structure 101, and the substrate 100 to which the dummy gate structure 101 is exposed. Specifically, the etch stop layer 106 conformally covers the top and sidewalls of the hard mask layer 102, the sidewalls of the dummy gate structure 101, and the source drain doped layer 104.
The etch stop layer 106 is a contact etch stop layer (Contact Etch Stop Layer, CESL). The etching stop layer 106 located on the top surface of the source-drain doped layer 104 is used for defining an etching stop position in a subsequent contact hole etching process, which is beneficial to reducing the damage of the contact hole etching process to the source-drain doped layer 104; the etch stop layer 106 on the sidewall of the dummy gate structure 101 is used for protecting the dummy gate structure 101 in a subsequent process, and the etch stop layer 106 is also used for protecting the gate structure in a subsequent process after the gate structure is formed at the dummy gate structure 101.
In this embodiment, the material of the etching stop layer 106 is silicon nitride. The silicon nitride material has a higher density and a higher hardness, so that the etching stop layer 106 is ensured to have the function of defining the etching stop position and the corresponding protection function.
In this embodiment, the etch stop layer 106 is formed using an atomic layer deposition (Atomic Layer Deposition, ALD) process. The atomic layer deposition process has better step coverage capability, which is beneficial to enabling the etching stop layer 106 to cover the top and the side wall of the hard mask layer 102, the side wall of the pseudo gate structure 101 and the substrate 100 exposed by the pseudo gate structure 101 in a conformal manner; moreover, the atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a thin film of a desired thickness, which is advantageous for improving thickness uniformity and compactness of the etch stop layer 106.
In this embodiment, the top surface and the side wall of the dummy gate structure 101 at the interface between the first device region and the second device region are formed with a low dielectric constant layer 1051 and an N/P interface layer 1052 on the top surface and the side wall of the low dielectric constant layer 1051, so that in the step of forming the etching stop layer 106, the etching stop layer 106 also conformally covers the N/P interface layer 1052. After the etching stop layer 106 is formed, the top surface of the etching stop layer 106 has a different height.
Referring to fig. 11, a dielectric material layer 107 is formed on the substrate 100 where the dummy gate structure 101 is exposed, and the dielectric material layer 107 covers the etch stop layer 106 on the hard mask layer 102.
The dielectric material layer 107 is used for forming an interlayer dielectric layer subsequently, so that isolation between adjacent devices is achieved.
Thus, the material of the dielectric material layer 107 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the dielectric material layer 107 has a single-layer structure, and the material of the dielectric material layer 107 is silicon oxide.
In this embodiment, the dielectric material layer 107 is formed by a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, is suitable for filling the openings with high depth-to-width ratio, is beneficial to reducing the probability of forming defects such as cavities in the dielectric material layer 107, and is correspondingly beneficial to improving the film quality of the subsequent interlayer dielectric layers.
Referring to fig. 12, a first planarization process is performed on the dielectric material layer 107 with the highest position on top of the etching stop layer 106 as a stop position.
It should be noted that, the top surfaces of the etching stop layers 106 have different heights, and the highest position of the top of the etching stop layers 106 refers to the farthest distance from the top surface of the etching stop layers 106 to the surface of the substrate 100 along the direction perpendicular to the surface of the substrate 100.
By taking the highest position of the top of the etching stop layer 106 as a stop position, the dielectric material layer 107 is subjected to the first planarization, so that in the step of the first planarization, only the dielectric material layer 107 is subjected to the first planarization, and other film structures are not contacted, thereby being beneficial to preventing the problem of grinding amount difference caused by different pattern densities of all areas or different heights of the top surfaces of all film structures, reducing the probability of occurrence of a recess problem on the top of the residual dielectric material layer 107, ensuring that the height consistency of the top of the dielectric material layer 107 after the first planarization is better, and correspondingly being beneficial to improving the height consistency of the top of the subsequent interlayer dielectric layer.
And, the subsequent step further includes etching the etching stop layer 106 and the dielectric material layer 107, and removing the etching stop layer 106 and the dielectric material layer 107 higher than the top of the hard mask layer 102, compared with the scheme that the etching stop layer 106 on the side wall of the dummy gate structure 101 is directly etched without the first planarization treatment, the thickness of the dielectric material layer 107 to be removed in the subsequent etching treatment is reduced through the first planarization treatment, so that the process time required by the etching treatment is shorter, the difference of the etching amounts of the dielectric material layer 107 in the regions with different pattern densities in the etching treatment is reduced, which is beneficial to not only improving the height consistency of the top of the subsequent interlayer dielectric layer, but also reducing the probability of loss of the etching stop layer 106 on the side wall of the dummy gate structure 101 caused by the difference of the etching amount of the dielectric material layer 107, thereby ensuring the protection effect of the etching stop layer 106 on the side wall of the formed gate structure 101 in the subsequent process, preventing the side wall loss of the gate structure 101, and improving the performance of the semiconductor structure.
In this embodiment, a low dielectric constant layer 1051 and an N/P interface layer 1052 on the top surface and the sidewall of the low dielectric constant layer 1051 are formed on the top surface and the sidewall of the dummy gate structure 101 at the interface between the first device region and the second device region, so the highest position on the top of the etching stop layer 106 refers to the top of the etching stop layer 106 on the top of the N/P interface layer 1052.
In this embodiment, the first planarization process is performed using a chemical mechanical polishing (CHEMMICALLY-MECHANICALLY POLISHING, CMP) process. By adopting the chemical mechanical polishing process, the highest position at the top of the etching stop layer 106 is advantageously accurately positioned, so that the stop position of the first planarization process is accurately controlled, the process difficulty of the first planarization process is reduced, and further, the flatness of the top surface of the dielectric material layer 107 after the first planarization process is further advantageously improved.
Specifically, during the first planarization process using a chemical mechanical polishing process, an endpoint detection (EPD) mode is used to take the highest position on top of the etching stop layer 106 as a polishing stop position.
In other embodiments, the first planarization process may further include performing an etch back (etching back) and a chemical mechanical polishing process sequentially.
Referring to fig. 13, after the first planarization process, an etching process is performed on the etching stop layer 106 and the dielectric material layer 107, and the etching stop layer 106 and the dielectric material layer 107 that are higher than the top of the hard mask layer 102 are removed.
By adopting the etching treatment mode, different materials are easy to remove in the same step at similar etching rates, and the difference of etching amounts of the dielectric material layers 107 in areas with different pattern densities in the etching treatment is reduced, so that after the etching treatment is finished, the consistency of the heights of the tops of the residual dielectric material layers 107 is also good, and the probability of loss of the etching stop layer 106 on the side wall of the pseudo gate structure 101 caused by the difference of the etching amounts of the dielectric material layers 107 is also reduced, thereby ensuring the protection effect of the etching stop layer 106 on the side wall of the formed gate structure in the subsequent process and preventing the side wall of the gate structure from being lost.
In this embodiment, the etch stop layer 106 and the dielectric material layer 107 are removed above the top of the top hard mask layer 1022. The top hard mask layer 1022 is used to define an etching stop position in the step of etching the etching stop layer 106 and the dielectric material layer 107, so as to improve the uniformity of the top of the dielectric material layer 107 after etching.
Moreover, the material of the top hard mask layer 1022 is silicon oxide, so that the adhesion between the silicon oxide layer and other film layers is high, thereby facilitating the subsequent formation of other film layers on the top hard mask layer 1022 and the dielectric material layer 107, and correspondingly facilitating the improvement of the quality of the subsequently formed film layers.
In this embodiment, the etching process is performed by using a sicoi process. The Siconi process is used as a low-strength high-precision chemical etching method, and the steps generally comprise: firstly, generating etching gas; etching the material layer to be etched through the etching gas to form byproducts; performing an annealing process to sublimate and decompose the byproducts into gaseous products; and removing the gaseous product by means of air suction.
In this embodiment, the etching gas of the sicoi process includes a C xFy gas and a C xHyFz gas.
The Siconi process is adopted to easily enable the etching rate of the etching treatment on the silicon nitride material and the silicon oxide material to be relatively close, so that the etching stop layer 106 and the dielectric material layer 107 which are higher than the top of the hard mask layer 102 can be removed in the same step, and the Siconi process is also beneficial to improving the etching load effect of the etching treatment, so that the height consistency of the top surface of the dielectric material layer 107 after the etching treatment is further improved; in addition, the Siconi process is easy to obtain a higher etching selection ratio, and is beneficial to reducing the damage probability of other film structures in the step of etching treatment.
In other embodiments, the etching process may also be performed by a dry etching process according to actual process requirements.
The bias voltage of the sicoi process should not be too small nor too large. If the bias voltage is too small, the plasma concentration of the etching process is easily reduced, thereby reducing the etching rate; if the bias voltage is too large, the uniformity of the etching rate is easily reduced, thereby reducing the uniformity of the height of the top surface of the dielectric material layer 107 after the etching process. For this reason, in this embodiment, the offset voltage of the Siconi process is 15 volts to 25 volts.
In this embodiment, in the step of performing the etching process, the process parameters of the etching process are set reasonably, so that the difference in height of the top surface of the dielectric material layer 107 in each region is less than 10nm after the etching process is performed, thereby improving the height uniformity of the top surface of the dielectric material layer 107.
In this embodiment, in the step of removing the etching stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102, the N/P interface layer 1052 and the low dielectric constant layer 1051 above the top of the hard mask layer 102 are also removed.
In this embodiment, after the etching treatment, the method further includes:
referring to fig. 14, a cross-sectional view of the semiconductor structure along the extension direction of the dummy gate structure 101 is shown, and in this embodiment, after the etching process, the method further includes: the dummy gate structure 101 is cut by an etching process, and openings 200 exposing the substrate 100 are formed in the dielectric material layer 107, and the openings 200 are distributed in the extending direction of the dummy gate structure 101.
By performing the cutting process on the dummy gate structure 101, the unnecessary dummy gate structure 101 is removed, so that the layout of the dummy gate structure 101 meets the design requirement of the integrated circuit.
In this embodiment, the step of forming the opening 200 includes: forming a mask pattern layer 108 on the hard mask layer 102; and cutting off the dummy gate structure 101 by using the mask pattern layer 108 as a mask and adopting a dry etching process, thereby forming an opening 200 exposing the substrate 100 in the dielectric material layer 107.
In this embodiment, the material of the mask pattern layer 108 is silicon oxide, the mask pattern layer 108 is formed on the top hard mask layer 1022, and the adhesion between the mask pattern layer 108 and the top hard mask layer 1022 is good, which is beneficial to improving the process effect of pattern transfer.
The dry etching process has the characteristic of anisotropic etching, is beneficial to improving the accuracy of pattern transfer, and is beneficial to enabling the profile of the opening 200 to meet the process requirements.
Referring to fig. 15 to 17, an isolation material layer 111 (as shown in fig. 17) is formed to fill the opening 200, and the isolation material layer 111 further covers the dielectric material layer 107 and the hard mask layer 102.
By filling the opening 200 with the isolation material layer 111, the remaining dummy gate structures 101 are isolated from each other in the extending direction of the dummy gate structures 101, and after the gate structures are formed at the positions of the dummy gate structures 101, the isolation material layer 111 located in the opening 200 can also electrically isolate the gate structures at both sides of the opening 200.
Accordingly, the material of the isolation material layer 111 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the isolation material layer 111 has a single-layer structure, and the isolation material layer 111 is made of silicon oxide.
In this embodiment, the isolation material layer 111 is formed by adopting a flowable chemical vapor deposition process, which is beneficial to reducing the probability of forming defects such as voids in the isolation material layer 111.
Specifically, the isolation material layer 111 covers the mask pattern layer 108.
It should be noted that, referring to fig. 15 to 16, after the opening 200 is formed, before the isolation material layer 111 is formed, the method further includes: a protective layer 110 is formed on the sidewalls of the opening 200.
After removing the dielectric material layer 107 higher than the top of the dummy gate structure 101 to form an interlayer dielectric layer, the method further includes: removing the dummy gate structure 101, and forming a gate opening in the dielectric material layer 107; a gate structure is formed within the gate opening. The protective layer 110 is used to protect the isolation material layer 111 located in the opening 200 during the step of forming the gate opening, thereby reducing the probability of damage to the isolation material layer 111 located in the opening 200.
In this embodiment, the material of the protection layer 110 is silicon nitride. The silicon nitride has higher density and hardness, which is beneficial to ensuring the protection effect of the protective layer 110 on the isolation material layer 111.
Specifically, the step of forming the protective layer 110 includes: forming a protective material layer 109 conformally covering the bottom and sidewalls of the opening 200, and the top of the hard mask layer 102 and dielectric material layer 107 (as shown in fig. 15); and removing the protective material layer 109 positioned on the top of the hard mask layer 102 and the dielectric material layer 107 and the bottom of the opening 200 by adopting an anisotropic etching process, and reserving the rest of the protective material layer 109 on the side wall of the opening 200 as the protective layer 110.
By conformally covering the bottom and the sidewalls of the opening 200 and the top of the hard mask layer 102 and the dielectric material layer 107 with the protective material layer 109, the protective material layer 109 on the top of the hard mask layer 102 and the dielectric material layer 107 and the bottom of the opening 200 can be removed by a maskless etching process, so that a photomask is not required in the process of forming the protective layer 110, which is beneficial to reducing the process cost.
In this embodiment, the protective material layer 109 is formed by an atomic layer deposition process. The use of an atomic layer deposition process is advantageous in improving the conformal coverage of the protective material layer 109 so that it can be formed on the sidewall of the opening 200, and in improving the thickness uniformity and compactness of the protective material layer 109, thereby ensuring the protective effect of the protective material layer 109 on the isolation material layer 111 of the opening 200.
The anisotropic etching process in this embodiment is a dry etching process. The dry etching process is easy to realize anisotropic etching, and is beneficial to reducing damage to the protective material layer 109 on the side wall of the opening 200, so that the protective layer 110 can have a corresponding protective effect.
Referring to fig. 18, with the top of the hard mask layer 102 as a stop position, a third planarization process is performed on the isolation material layer 111 and the dielectric material layer 107.
In this embodiment, the materials of the isolation material layer 111 and the bottom hard mask layer 1021 are different, so that in the step of the third planarization process, the bottom hard mask layer 1021 is used as a stop position, which is beneficial to improving the top height consistency of the isolation material layer 111 after the third planarization process.
In this embodiment, the chemical mechanical polishing process is used to perform the third planarization process.
Specifically, an endpoint detection (EPD) mode is adopted, and the highest position at the top of the bottom hard mask layer 1021 is used as a polishing stop position.
Referring to fig. 19, after the etching process, a second planarization process is performed on the dielectric material layer 107 and the hard mask layer 102 with the top of the dummy gate structure 101 as a stop position, and the remaining dielectric material layer 107 is used as the interlayer dielectric layer 120.
As can be seen from the foregoing, the top height uniformity of the dielectric material layer 107 after the first planarization process and the etching process is better, so that the polishing rate uniformity is better in the step of performing the second planarization process, and the top height uniformity of the interlayer dielectric layer 120 is improved after the interlayer dielectric layer 120 is formed.
In addition, the polishing rate uniformity of the second planarization process is better, which is also beneficial to reducing the probability of damage to the etching stop layer 106 on the side wall of the dummy gate structure 101 in the step of the second planarization process, so that after the gate structure is formed at the position of the dummy gate structure 101 later, the etching stop layer 106 can have a corresponding protection effect on the gate structure in the subsequent process, thereby reducing the probability of loss to the side wall of the gate structure and improving the performance of the semiconductor structure.
In this embodiment, the second planarization process is performed by using a chemical mechanical polishing process. The chemical mechanical polishing process is used to facilitate accurate positioning of the stop position of the second planarization process, reduce the process difficulty of the second planarization process, and further facilitate improvement of the flatness of the top surface of the interlayer dielectric layer 120.
Specifically, in the process of performing the second planarization process by using a chemical mechanical polishing process, an endpoint detection manner is used, and the top of the dummy gate structure 101 is used as a polishing stop position.
In this embodiment, an isolation material layer 111 (as shown in fig. 18) is further formed on the substrate 100 and is located in the opening 200 (as shown in fig. 18), and the top of the isolation material layer 111 is higher than the top of the dummy gate structure 101, so in the step of performing the second planarization process, the second planarization process is further performed on the isolation material layer 111, and the remaining isolation material layer 111 after the second planarization process is used as an isolation structure (not shown).
After the gate structure is subsequently formed at the position of the dummy gate structure 101, the isolation structure is used to achieve electrical isolation between adjacent gate structures along the extending direction of the gate structure.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method.
According to the method, the top height consistency of the interlayer dielectric layer formed by the method is good, and the etching stop layer on the pseudo gate structure is less in loss, so that the protection effect of the etching stop layer on the side wall of the subsequent gate structure is guaranteed, and the probability of loss of the side wall of the gate structure in the subsequent process is reduced. In summary, the performance of the semiconductor structure formed by the method is improved.
The semiconductor structure may be formed using the formation methods described in the previous embodiments. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a plurality of dummy gate structures are formed on the substrate, hard mask layers are formed on the tops of the dummy gate structures, and the heights of the highest parts of the hard mask layers on the tops of different dummy gate structures are the same;
forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure;
Forming a dielectric material layer on the substrate exposed by the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer;
Taking the highest position at the top of the etching stop layer as a stop position, and carrying out first planarization treatment on the dielectric material layer;
After the first planarization treatment is carried out, taking the highest position of the hard mask layer as a stop position, carrying out etching treatment on the etching stop layer and the dielectric material layer, and removing the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer;
after the etching treatment, forming an isolation material layer covering the top of the dielectric material layer;
taking the highest position at the top of the hard mask layer as a stop position, and carrying out third planarization treatment on the isolation material layer and the dielectric material layer;
And after the third planarization treatment, taking the top of the pseudo gate structure as a stop position, carrying out second planarization treatment on the dielectric material layer and the hard mask layer, and taking the rest of the dielectric material layer as an interlayer dielectric layer.
2. The method of claim 1, wherein the first planarization process is performed using a chemical mechanical polishing process.
3. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed using a dry etching process.
4. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed using a sicoi process.
5. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed with a difference in height of the top surface of the dielectric material layer in each region of less than 10 nm.
6. The method of claim 1, wherein the second planarization process is performed using a chemical mechanical polishing process.
7. The method of forming a semiconductor structure of claim 1, wherein after performing the etching process, before performing the second planarization process, further comprising:
Cutting off the pseudo gate structure through an etching process, and forming openings exposing the substrate in the dielectric material layer, wherein the openings are distributed in the extending direction of the pseudo gate structure;
The forming of the isolation material layer covering the top of the dielectric material layer includes:
Forming an isolation material layer filled in the opening, wherein the isolation material layer also covers the dielectric material layer and the hard mask layer;
and in the step of carrying out the second planarization treatment, carrying out the second planarization treatment on the isolation material layer, wherein the remaining isolation material layer after the second planarization treatment is used as an isolation structure.
8. The method of claim 7, wherein the hard mask layer comprises a bottom hard mask layer and a top hard mask layer on the bottom hard mask layer, the bottom hard mask layer being made of silicon nitride and the top hard mask layer being made of silicon oxide;
Removing the etching stop layer and the dielectric material layer which are higher than the top of the top hard mask layer in the step of etching the etching stop layer and the dielectric material layer;
in the third planarization step, the bottom hard mask layer is used as a stop position.
9. The method of claim 7, wherein the third planarization process is performed using a chemical mechanical polishing process.
10. The method of forming a semiconductor structure of claim 7, wherein after forming the opening, prior to forming the isolation material layer, further comprising:
A protective layer is formed on the sidewalls of the opening.
11. The method of forming a semiconductor structure of claim 10, wherein in the step of forming the protective layer, the material of the protective layer is silicon nitride.
12. The method of forming a semiconductor structure of claim 10, wherein the process of forming the protective layer comprises an atomic layer deposition process.
13. The method of forming a semiconductor structure of claim 10, wherein the step of forming the protective layer comprises: forming a protective material layer which conformally covers the bottom and the side wall of the opening and the tops of the hard mask layer and the dielectric material layer;
And removing the protective material layer positioned at the top of the hard mask layer and the dielectric material layer and at the bottom of the opening by adopting an anisotropic etching process, and reserving the rest protective material layer on the side wall of the opening as the protective layer.
14. A semiconductor structure formed by the method of any of claims 1-13.
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