CN117855254B

CN117855254B - Semiconductor device and manufacturing method thereof

Info

Publication number: CN117855254B
Application number: CN202410263407.7A
Authority: CN
Inventors: 朱会超; 李韦坤; 蔡富吉; 王文轩
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2024-03-08
Filing date: 2024-03-08
Publication date: 2024-05-28
Anticipated expiration: 2044-03-08
Also published as: CN117855254A

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate comprising a first region and a second region; forming a plurality of dummy gates on a substrate, and arranging a hard mask layer on the dummy gates; after forming the stress region on the second region, the thickness of the hard mask layer on the second region is smaller than that of the hard mask layer on the first region; forming a first stop layer and a first dielectric layer on the substrate, the hard mask layer and the side wall of the dummy gate; thinning and etching the first dielectric layer, wherein the surface of the first dielectric layer is lower than or flush with the surface of the dummy gate; forming a second stop layer and a second dielectric layer on the first dielectric layer and the first stop layer; taking the second stop layer on the substrate as a stop layer, and grinding until the pseudo grid electrode is flush with the second stop layers on two sides; and removing the dummy gate to form a metal gate. The semiconductor device and the manufacturing method thereof can improve the performance of the semiconductor device.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.

Background

With the continued scaling of process nodes, high dielectric constant metal gates are required for gate structures. Because metal gates are not resistant to high temperatures, the prior art typically uses a back gate process to form the metal gates. In the gate last process, a dummy gate is formed in the gate region, and after high temperature annealing, the gate material in the dummy gate is removed, and then metal is filled therein to form a metal gate. However, in the process of removing the dummy gate, the heights of the dummy gates in different regions are different, so that the formation of the subsequent metal gate is affected. In addition, in the process of removing the dummy gate, a large recess is easily formed on the dielectric layer between the gate regions, and metal residues are caused in the subsequent process, so that the electrical performance of the device is affected.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, and the semiconductor device and the manufacturing method thereof eliminate the height difference of grid electrodes on different areas, reduce the dent of a dielectric layer area and improve the electrical property of the semiconductor device.

In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, at least comprising the following steps:

providing a substrate comprising a first region and a second region;

Forming a plurality of dummy gates on the substrate, wherein a hard mask layer is arranged on the dummy gates;

after stress areas are formed on two sides of the pseudo gate on the second area, the thickness of the hard mask layer on the second area is smaller than that of the hard mask layer on the first area;

forming a first stop layer on the substrate, the hard mask layer and the side wall of the dummy gate;

forming a first dielectric layer on the first stop layer;

After thinning and etching the first dielectric layer, the surface of the first dielectric layer is lower than the surface of the dummy gate or is flush with the surface of the dummy gate;

Forming a second stop layer over the first dielectric layer and a portion of the first stop layer;

forming a second dielectric layer on the second stop layer;

Taking the second stop layer on the substrate as a grinding stop layer, and grinding until the height of the pseudo grid electrode is flush with the second stop layers on two sides; and

And removing the dummy gate to form a metal gate.

Further, the manufacturing method further comprises the following steps: and after the second dielectric layer is formed, performing a first grinding process, and grinding to remove the second dielectric layer by adopting a grinding mode of end point detection and taking the second stop layer on the pseudo gate as a grinding stop layer.

Further, the manufacturing method further comprises the following steps: and after the first grinding process, performing a second grinding process by adopting a grinding mode with limited grinding time, and grinding and removing the second dielectric layer, the second stop layer on the pseudo gate, the first stop layer and part of the hard mask layer until the surfaces of the hard mask layer on the first area and the second area are flush, and grinding until the thickness of the hard mask layer is 0A-50A.

Further, the manufacturing method further comprises the following steps: and after the second grinding process, performing a third grinding process, wherein a grinding mode of end point detection is adopted, the second stop layer on the first dielectric layer is taken as a detection end point, the grinding is performed until the pseudo grid electrode is flush with the second stop layer, and the heights of the plurality of pseudo grid electrodes are consistent.

Further, the manufacturing method further comprises the following steps: a heavily doped region is formed on both sides of the dummy gate on the first region prior to forming the stress region.

Further, when the first dielectric layer is thinned, the thickness of the first dielectric layer remaining on the dummy gate of the first region is 100 a to 200 a, or the first stop layer on the first region is taken as a polishing stop layer.

Further, when the surface of the first dielectric layer is lower than the surface of the dummy gate, the height difference between the first dielectric layer and the dummy gate is 200 a-400 a.

Further, the hard mask layer is made of one or more of silicon nitride, silicon oxide, titanium nitride or silicon carbide nitride; the first stop layer and the second stop layer are silicon nitride layers.

Further, after the stress region is formed, the thickness of the hard mask layer on the first region is 200 a-400 a, and the thickness of the hard mask layer on the second region is greater than 0 and less than 50 a.

The invention also provides a semiconductor device, which is obtained by adopting the manufacturing method, and at least comprises the following steps:

a substrate including a first region and a second region;

a plurality of metal gates arranged on the substrate, wherein the heights of the metal gates are the same;

a first stop layer disposed on sidewalls of the substrate and the metal gate;

a first dielectric layer disposed on the first stop layer and disposed between the plurality of metal gates; and

And the second stopping layer is arranged on the first dielectric layer and is flush with the surface of the metal gate.

In summary, the present application provides a semiconductor device and a method for manufacturing the same, and by improving the structure and the method for manufacturing the semiconductor device, the unexpected technical effects of the present application are as follows: the height of the dummy gate in different areas after chemical mechanical polishing can be ensured to be the same in the process of forming the metal gate by adopting a back gate process, so that the height of the subsequently formed metal gate is ensured to be consistent; the height of the pseudo grid can be effectively and accurately controlled by adopting a chemical mechanical polishing mode of end point detection; meanwhile, the stop layer is used as an endpoint of dielectric layer grinding removal, so that the recess caused by the dielectric layer between the grid electrode areas in the chemical mechanical grinding process is eliminated, and the electrical performance of the semiconductor device is improved.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of forming a first gate dielectric layer, a second gate dielectric layer, a gate material layer and a hard mask layer on a substrate according to an embodiment of the invention.

Fig. 2 is a schematic diagram illustrating formation of a first dummy gate and a second dummy gate according to an embodiment of the invention.

Fig. 3 is a schematic diagram illustrating formation of a sidewall structure and a heavily doped region according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of forming a groove according to an embodiment of the invention.

FIG. 5 is a schematic diagram illustrating formation of stress regions in accordance with an embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating formation of a first stop layer according to an embodiment of the invention.

FIG. 7 is a schematic diagram illustrating a first dielectric layer formed according to an embodiment of the invention.

FIG. 8 is a schematic diagram of polishing a first dielectric layer according to an embodiment of the invention.

FIG. 9 is a schematic diagram illustrating etching of a first dielectric layer according to an embodiment of the invention.

FIG. 10 is a schematic diagram illustrating formation of a second stop layer according to an embodiment of the invention.

FIG. 11 is a schematic diagram illustrating a second dielectric layer formed according to an embodiment of the invention.

Fig. 12 is a schematic view of a first polishing process according to an embodiment of the invention.

FIG. 13 is a schematic diagram of a second polishing process according to an embodiment of the invention.

FIG. 14 is a schematic diagram of a third polishing process according to an embodiment of the invention.

Fig. 15 is a schematic diagram illustrating formation of a metal gate according to an embodiment of the invention.

Description of the reference numerals:

10. A substrate; 101. an isolation region; 102. an active region; 11. a first gate dielectric layer; 12. a second gate dielectric layer; 13. a gate material layer; 14. a hard mask layer; 15. a heavily doped region; 16. a photoresist layer; 17. a groove; 18. a stress region; 21. a first dummy gate; 22. a second dummy gate; 23. a side wall structure; 31. a first stop layer; 32. a second stop layer; 41. a first dielectric layer; 42. a second dielectric layer; 51. a first metal gate; 52. a second metal gate; 1. a first region; 2. a second region.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

In the description of the present specification, it should be understood that the directions or positional relationships indicated in terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or component referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

The semiconductor device and the manufacturing method thereof can eliminate the problem of different heights of the pseudo grid electrodes in different areas on the substrate caused by etching processes, thereby ensuring the consistency of the heights of the metal grid electrodes formed later, avoiding the formation of pits on the dielectric layer in chemical mechanical polishing, improving the electrical performance and reliability of the semiconductor device, and being applicable to the process of forming the metal grid electrodes by different semiconductor devices. The semiconductor device prepared by the method can be widely applied to various fields such as optical communication, digital display, image receiving, optical integration, traffic, energy, medicine, household appliances, aerospace and the like. The invention is not limited to the specific type of semiconductor device formed, and in one embodiment of the invention, for example, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) is formed.

Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is provided first, the substrate 10 includes a first region 1 and a second region 2, wherein the first region 1 is used for forming a N-type metal oxide semiconductor field effect transistor (NEGATIVE CHANNEL METAL Oxide Semiconductor, NMOS), and the second region 2 is used for forming a P-type metal oxide semiconductor field effect transistor (PMOS), for example. The substrate 10 may be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compound semiconductor materials, and the like, and includes a stacked structure of these semiconductor materials, or is silicon on insulator, silicon on insulator stacked, silicon germanium on insulator, and the like. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, and the isolation region 101 and the active region 102 are formed on the substrate 10, the active region 102 is, for example, disposed on the first region 1 and the second region 2, the isolation region 101 is used to isolate adjacent active regions 102, and the isolation region 101 includes, for example, silicon dioxide or other materials that can isolate the active regions 102. The active region 102 of the first region 1 is doped P-type, for example, and the active region 102 of the second region 2 is doped N-type, for example. In other embodiments, the type of substrate 10 is selected depending on the semiconductor device being fabricated.

Referring to fig. 1, in an embodiment of the present invention, a first gate dielectric layer 11 is formed on a substrate 10, wherein the first gate dielectric layer 11 is, for example, one or more of hafnium oxide (HfO ₂), hafnium oxynitride (HfON), zirconium oxide (ZrO ₂), zirconium oxynitride (ZrON), zirconium oxynitridosilicate (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitridosilicate (HfSiON), lanthanum hafnium oxynitride (HfLaON), or hafnium aluminum oxide (HfAlO). The first gate dielectric layer 11 may be formed by using an atomic layer deposition (Atomic Layer Deposition, ALD), a Metal-organic vapor deposition (Metal-Organic Chemical Vapor Deposition, MOCVD), a Molecular beam epitaxy (Molecular BeamEpitaxy, MBE), a chemical vapor deposition (cvd) or a physical vapor deposition (Physical Vapor Deposition, PVD), and the thickness of the first gate dielectric layer 11 may be, for example, 4nm to 10nm. A silicon oxide layer (not shown) is further disposed between the first gate dielectric layer 11 and the substrate 10 to improve the interface performance between the first gate dielectric layer 11 and the substrate 10. After the first gate dielectric layer 11 is formed, a second gate dielectric layer 12 is formed on the first gate dielectric layer 11, where the second gate dielectric layer 12 is, for example, titanium nitride or titanium, and the second gate dielectric layer 12 is, for example, prepared by an atomic layer deposition method (Atomic Layer Deposition, ALD), and the thickness of the second gate dielectric layer 12 is selected according to the manufacturing requirement. By arranging the first gate dielectric layer 11, the performance of the metal gate which is manufactured later is improved.

Referring to fig. 1 to 2, in an embodiment of the invention, after forming the second gate dielectric layer 12, a gate material layer 13 is formed on the second gate dielectric layer 12, and the gate material layer 13 is, for example, polysilicon. The thickness of the gate material layer 13 is, for example, 200nm to 300nm. After the gate material layer 13 is formed, a hard mask layer 14 is formed on the gate material layer 13, and the hard mask layer 14 is formed by, for example, a selective chemical vapor deposition method or a physical vapor deposition method. The hard mask layer 14 is used as a protection layer of the pseudo gate, so that damage to the pseudo gate caused by etching or grinding process in the subsequent process of forming a stress region is avoided, and meanwhile, the hard mask layer 14 is used as a grinding stop layer, so that the height consistency of the pseudo gate after grinding is ensured. The material of the hard mask layer 14 is, for example, one or more of silicon nitride, silicon oxide, titanium nitride, silicon carbide nitride, etc., and the deposition method and thickness of the hard mask layer 14 are selected according to the manufacturing requirements. In this embodiment, the hard mask layer 14 is, for example, a silicon oxide layer, and the thickness of the hard mask layer 14 is, for example, 200 a to 400 a, so as to ensure that a portion of the hard mask layer 14 remains on the dummy gate in the second region 2 after the stress region is formed in the second region 2, so as to prevent the recess of the dummy gate in the planarization process. After forming the hard mask layer 14, a photoresist layer (not shown) is formed on the hard mask layer 14, and then the photoresist layer is exposed and developed to form a patterned photoresist layer. The hard mask layer 14, the gate material layer 13, the second gate dielectric layer 12 and the first gate dielectric layer 11 are then etched using the patterned photoresist layer as a mask, the substrate 10 as an etch stop layer, for example, by a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process, to form a complete dummy gate, which is a polysilicon gate. In the present embodiment, for example, the first dummy gate 21 is formed on the first region 1 at the same time, the second dummy gate 22 is formed on the second region 2, and the heights of the first dummy gate 21 and the second dummy gate 22 are the same.

Referring to fig. 2 to 3, in an embodiment of the present invention, after forming the polysilicon gate, lightly doped regions (not shown) are formed in the substrate 10 at both sides of the first dummy gate 21 and the second dummy gate 22, wherein the lightly doped regions are formed by ion implantation, and the ion type of the implantation is opposite to that of the active region. In this embodiment, the doping ions in the lightly doped region in the first region 1 are N-type impurities such As phosphorus (P) or arsenic (As), the doping ions in the lightly doped region in the second region 2 are P-type impurities such As boron (B) or gallium (Ga), and the edge portion of the lightly doped region formed extends to the bottom of the polysilicon gate electrode during the process of implanting the doping ions.

Referring to fig. 2 to 3, in an embodiment of the invention, after forming the lightly doped region, sidewall structures 23 are formed on both sides of the first dummy gate 21 and the second dummy gate 22, and heights of the sidewall structures 23 on both sides of the first dummy gate 21 and the second dummy gate 22 are the same. Specifically, the sidewall structure 23 is a stacked structure of silicon oxide, silicon nitride, or the like, for example, to improve stability of the polysilicon gate, thereby improving stability of the threshold voltage of the semiconductor structure. In this embodiment, the shape, the number of layers and the thickness of the sidewall structures 23 on the first region 1 and the second region 2 are the same, for example. In other embodiments, the shape, number of layers and thickness of the sidewall structures 23 are set, for example, according to the specific production requirements of PMOS and NMOS.

Referring to fig. 3 to 5, in an embodiment of the application, after forming the sidewall structure 23, heavily doped regions 15 are formed on both sides of the first dummy gate 21. Wherein the dopant ions of the heavily doped region 15 are formed, for example, by ion implantation, and the implanted ion type is opposite to the ion type in the active region. In this embodiment, the doped ions in the heavily doped region 15 are, for example, N-type impurities such as phosphorus or arsenic, and are used as the source/drain electrodes for the subsequent NMOS formation. After forming the heavily doped region 15, a photoresist layer 16 is formed on the substrate 10, and the photoresist layer 16 covers, for example, the first region 1 and a portion of the second region 2 adjacent to the first region 1. With the photoresist layer 16 as a mask, grooves 17 are formed in the substrate 10 on both sides of the second dummy gate 22 by dry etching and wet etching. In the present embodiment, the grooves 17 are provided in an open polygon, for example. A semiconductor material is deposited within recess 17 to form stress region 18. In this embodiment, the stress region 18 is, for example, a silicon germanium (SiGe) material, and the SiGe is, for example, siGe doped with P-type impurities. The shape of the stress region 18 is consistent with the shape of the recess 17, for example, the shape of a polygon, and one side of the polygon is parallel to the substrate 10, and the stress region 18 serves as a source/drain of the PMOS transistor, so that carrier mobility is improved. During the formation of the recess 17, the hard mask layer 14 on the second dummy gate 22 is partially removed during etching such that the thickness of the hard mask layer 14 on the second dummy gate 22 is less than the thickness of the hard mask layer 14 on the first dummy gate 21. In one embodiment of the present application, after forming the stress region 18, the thickness of the hard mask layer 14 on the second dummy gate 22 is, for example, less than or equal to 50 a and greater than 0 a. If the dielectric layer is directly deposited for grinding and the dummy gate is removed to prepare the metal gate, the height of the metal gate is different, which affects the performance of the semiconductor device.

Referring to fig. 4 to 6, in an embodiment of the invention, after forming the stress region 18, the photoresist layer 16 is removed, and a first stop layer 31 is formed on the substrate 10, and the first stop layer 31 is, for example, a silicon nitride layer. The first stop layer 31 covers, for example, the substrate 10, the hard mask layer 14 and the sidewall structure 23, and the first stop layer 31 can avoid the second dummy gate 22 from being polished in advance in a subsequent process, and simultaneously avoid affecting the stability of the sidewall structure 23 or damaging the substrate 10 in a subsequent process of forming a contact hole and other structures. In this embodiment, the first stop layer 31 is formed by, for example, selecting a Hard Mask (HM) process, and the thickness of the first stop layer 31 is, for example, 100 a to 300 a. The present invention is not limited to the method of forming the first stop layer 31, and may be formed by any one of physical vapor deposition, chemical vapor deposition (Chemical Vapor Deposition, CVD), and the like.

Referring to fig. 6 to 7, in an embodiment of the invention, after forming the first stop layer 31, a first dielectric layer 41 is formed on the first stop layer 31, and the first dielectric layer 41 is completely filled between the first dummy gate 21 and the second dummy gate 22 and completely covers the first stop layer 31, for example. In the present embodiment, the first dielectric layer 41 is, for example, silicon oxide, and is obtained by, for example, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, or the like. In order to enable the material of the first dielectric layer 41 to be sufficiently filled between the adjacent dummy gates, in this embodiment, the first dielectric layer 41 is formed by, for example, high density plasma chemical vapor deposition (HIGH DENSITY PLASMA CVD, HDP-CVD) or high aspect Ratio chemical vapor deposition (HIGH ASPECT Ratio Process CVD, HARP-CVD). In other embodiments, the first dielectric layer 41 is a material such as silicon fluoride (SiF), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF), and the first dielectric layer 41 is formed by, for example, selective fluid chemical vapor deposition (Fluid Chemical Vapor Deposition Process, FCVD), which is not particularly limited in the present invention.

Referring to fig. 7 to fig. 9, in an embodiment of the invention, after forming the first dielectric layer 41, the thickness of the first dielectric layer 41 is reduced, for example, by chemical mechanical polishing, and during polishing, polishing time is controlled, so that the remaining thickness of the first dielectric layer 41 on the first dummy gate 21 is, for example, 100a to 200 a, or the first stop layer 31 on the first region 1 is used as a polishing stop layer, so as to ensure that the first dielectric layer 41 between the first dummy gates 21 is not recessed. Next, a portion of the first dielectric layer 41 is etched away, for example, the first dielectric layer 41 on the first dummy gate 21 and the second dummy gate 22, and a portion of the first dielectric layer 41 between the first dummy gate 21 and the second dummy gate 22 are removed. In removing the first dielectric layer 41, one of dry etching or wet etching may be employed. In this embodiment, for example, dry etching is used to remove, and the etching gas may be chlorine, bromine, helium, hydrogen bromide, or a mixed gas of at least one of the gases and oxygen. In this embodiment, after the first dielectric layer 41 is etched, the surface of the first dielectric layer 41 is at least lower than or flush with the surface of the dummy gate, and when the surface of the dummy gate is lower than the surface of the dummy gate, the height difference between the surface of the dummy gate and the surface of the first dielectric layer 41 is, for example, 200 a to 400 a, so as to ensure the height of the metal gate formed later. By firstly thinning the first dielectric layer and then etching, the problem of poor uniformity possibly occurring in the whole etching process can be reduced, the surface of the first dielectric layer is ensured to be in the same plane, and the quality of the finally formed semiconductor device is improved.

Referring to fig. 9 to 11, in an embodiment of the invention, after etching the first dielectric layer 41, a second stop layer 32 is formed on the first dielectric layer 41 and a portion of the first stop layer 31, and the second stop layer 32 covers the exposed first stop layer 31 and the first dielectric layer 41, for example. The material of the second stop layer 32 is, for example, a silicon nitride material, and the silicon nitride material is, for example, formed by a hard mask process or a contact hole etching stop layer (Contact Etch Stop Layer, CESL) process, so that the first stop layer 31 is formed with a higher hardness, and thus, the recess is prevented from being formed in the polishing process. In this embodiment, for example, a hard mask process is selected to form the second stop layer 32, and the thickness of the second stop layer 32 is, for example, 100 a to 200 a. After forming the second stop layer 32, a second dielectric layer 42 is formed on the second stop layer 32, where the material of the second dielectric layer 42 is, for example, silicon oxide, silicon fluoride, silicon oxycarbide, or silicon oxyfluoride, and is obtained by, for example, selecting one or a combination of a high aspect ratio process, a plasma enhanced tetraethyl orthosilicate layer deposition (PLASMA ENHANCED deposition process of ethyl orthosilicate layer, PETEOS) process, or a high density plasma chemical vapor deposition. In the present embodiment, the material of the second dielectric layer 42 is the same as that of the first dielectric layer 41, i.e. the material of the second dielectric layer 42 is a silicon oxide material, and is formed by a deposition process of a selected plasma enhanced tetraethyl orthosilicate layer, for example, the second dielectric layer 42 is formed at a set temperature and pressure. Specifically, the reaction temperature is, for example, 300 ℃ to 350 ℃, and the reaction pressure is, for example, 20mpa to 40mpa, so that the second dielectric layer 42 is completely filled between the first dummy gate 21 and the second dummy gate 22.

Referring to fig. 11 to 14, in an embodiment of the invention, after forming the second dielectric layer 42, the second stop layer 32 is used as a polishing stop layer, and the second dielectric layer 42, the second stop layer 32 on the dummy gate, the first stop layer 31, the hard mask layer 14 and a portion of the dummy gate are removed so as to form a metal gate with a uniform height in a subsequent process. In this embodiment, a chemical mechanical mask is selected for removal, for example. After the polishing, the heights of the remaining first dummy gate 21 and second dummy gate 22 are flush, and the surfaces of the first dummy gate 21 and second dummy gate 22 are flush with the surfaces of the second stop layers 32 on both sides thereof. By forming the second stop layer 32 on the dielectric layer, the first dielectric layer 41 is prevented from forming a recess in the subsequent chemical mechanical polishing, and the reliability of the subsequently formed semiconductor device is improved. And the height of the subsequently formed metal gate is the same as the height of the second stop layer 32 on the first dielectric layer 41, and the height of the subsequently formed metal gate can be controlled by controlling the height of the etched first dielectric layer 41 and the thickness of the formed second stop layer 32, so that the performance of the semiconductor device is improved.

Referring to fig. 11 to 14, in an embodiment of the present invention, the second dielectric layer 42 is polished to the second stop layer 32, for example, by three polishing processes. The first polishing process, for example, selects the polishing mode for endpoint detection and, for example, polishes the second dielectric layer 42 to a stop for the second stop layer 32 on the second dummy gate 22. After the first polishing process, the second dielectric layer 42 on the second dummy gate 22 is removed, the second dielectric layer 42 on the first dummy gate 21 is removed, and the second dielectric layers 42 on both sides of the first dummy gate 21 are flush with the second dielectric layers 42 on both sides of the second dummy gate 22, and the thickness of the hard mask layer 14 on the first dummy gate 21 is still higher than the thickness of the hard mask layer 14 on the second dummy gate 22. The polishing mode of the end point detection is to set a polishing stop layer, and after the stop layer is detected in the polishing process, the polishing is stopped, and the stop layers on the first dummy gate 21 and the second dummy gate 22 can be completely exposed by stopping the second stop layer 32 on the second dummy gate 22, so that the stop layer is removed.

Referring to fig. 11 to 14, in an embodiment of the invention, after the first polishing process, a second polishing process is performed on the second dielectric layer 42, and the second dielectric layer 42, the first stop layer 31, the second stop layer 32 and the hard mask layer 14 are polished, for example, by a polishing mode for controlling polishing time, and the polishing is stopped until the remaining thickness of the hard mask layer 14 is, for example, 0a to 50 a. After the second polishing process, the hard mask layer 14 on the first dummy gate 21 and the second dummy gate 22 are on the same plane. In the second polishing process, the polishing is performed by controlling the polishing time so as to control the hard mask layer 14 on the first dummy gate 21 and the second dummy gate 22 to be in the same plane. After the second polishing process, a third polishing process is performed, for example, a polishing mode of endpoint detection is selected, so as to precisely control a polishing stop position, flexibly control the height of the obtained dummy gate, and the second stop layer 32 on the first dielectric layer 41 is used as a detection endpoint, and the second dielectric layer 42 on the first dielectric layer 41, the hard mask layer 14 on the dummy gate, the first stop layer 31, the second stop layer 32 and part of the dummy gate are polished and removed, so that the heights of the first dummy gate 21 and the second dummy gate 22 are consistent. And in this embodiment, the first dummy gate 21 and the second dummy gate 22 are flush with the second stop layer 32 on the first dielectric layer 41. By performing the three polishing processes, different polishing processes are selected, and in the third polishing process, a polishing mode for end point monitoring is selected, the height of the finally obtained dummy gate is precisely controlled, and the heights of the first dummy gate 21 and the second dummy gate 22 are ensured to be consistent. Meanwhile, the polishing is stopped until the second stop layer 32 stops, so that the first dielectric layer 41 is prevented from forming a recess in the polishing process, metal residues in the subsequent process are avoided, and the electrical performance and reliability of the device are improved.

Referring to fig. 14 to 15, in an embodiment of the present invention, after the third polishing, the gate material layer in the first dummy gate 21 and the second dummy gate 22 is removed to form an opening (not shown). After forming the openings, a plurality of metal function layers are deposited in the openings to form metal gates. In this embodiment, the material of the metal work function layer is, for example, one or a stack of tantalum nitride, titanium aluminide (TiAl), titanium aluminum nitride (TiAIN), tungsten nitride (WN), or the like, and the metal work function layer is formed by, for example, a method such as a plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition (PECVD), atomic layer Deposition, or physical Vapor Deposition (pvd). The invention is not limited to a particular number of layers and method of forming the metal work function layer, such as according to a particular semiconductor device arrangement being formed. In this embodiment, the first metal gate 51 is formed on the first region 1 and the second metal gate 52 is formed on the second region 2, for example, four metal work function layers are formed and obtained by a process of selective atomic layer deposition. In this embodiment, the heights of the first dummy gate 21 and the second dummy gate 22 are the same, so that the heights of the first metal gate 51 and the second metal gate 52 obtained after the gate material layer is removed are the same, thereby effectively ensuring the reliability of the semiconductor device.

In summary, the present application provides a semiconductor device and a method for manufacturing the same, and by improving the structure and the method for manufacturing the semiconductor device, the unexpected technical effect of the present application is that the heights of the dummy gates in different regions can be controlled to be consistent, so as to improve the quality of the subsequently manufactured metal gates; the second stop layer is arranged as the grinding stop layer, so that the height of the pseudo grid electrode is controlled, and the chemical mechanical grinding mode of end point detection is adopted, so that the height of the pseudo grid electrode is effectively and accurately controlled; meanwhile, the second stop layer is arranged on the first dielectric layer, so that the problem of depression of the dielectric layer between the grid regions in the chemical mechanical polishing process is solved, and the electrical performance and reliability of the semiconductor device are improved.

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.

The above description is only a preferred embodiment of the present application and the description of the technical principle applied, and it should be understood by those skilled in the art that the scope of the present application is not limited to the specific combination of the above technical features, but also covers other technical features formed by any combination of the above technical features or the equivalent features thereof without departing from the inventive concept, for example, the technical features disclosed in the present application (but not limited to) are replaced with technical features having similar functions. Other technical features besides those described in the specification are known to those skilled in the art, and are not described herein in detail to highlight the innovative features of the present application.

Claims

1. A method of fabricating a semiconductor device, comprising at least the steps of:

providing a substrate comprising a first region and a second region;

forming a first dielectric layer on the first stop layer;

forming a second dielectric layer on the second stop layer;

Removing the dummy gate to form a metal gate;

after forming a second dielectric layer, performing a first grinding process, and grinding to remove the second dielectric layer by taking the second stop layer on the pseudo gate as a grinding stop layer in a grinding mode of end point detection;

After the first grinding process, a second grinding process is carried out by adopting a grinding mode for limiting grinding time, and the second dielectric layer, the second stop layer on the pseudo gate, the first stop layer and part of the hard mask layer are removed by grinding until the surfaces of the hard mask layer on the first area and the second area are flush, and the thickness of the hard mask layer is 0A-50A;

And after the second grinding process, performing a third grinding process, wherein a grinding mode of end point detection is adopted, the second stop layer on the first dielectric layer is taken as a detection end point, the grinding is performed until the pseudo grid electrode is flush with the second stop layer, and the heights of the plurality of pseudo grid electrodes are consistent.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising: a heavily doped region is formed on both sides of the dummy gate on the first region prior to forming the stress region.

3. The method of claim 1, wherein when the first dielectric layer is thinned, the thickness of the first dielectric layer remaining on the dummy gate in the first region is 100 a to 200 a, or the first stop layer in the first region is used as a polish stop layer.

4. The method of manufacturing a semiconductor device according to claim 1, wherein when the surface of the first dielectric layer is lower than the surface of the dummy gate, a height difference between the first dielectric layer and the dummy gate is 200 a to 400 a.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the hard mask layer is one or more of silicon nitride, silicon oxide, titanium nitride, and silicon carbide nitride; the first stop layer and the second stop layer are silicon nitride layers.

6. The method of claim 1, wherein after the stress region is formed, the thickness of the hard mask layer on the first region is 200 a to 400 a, and the thickness of the hard mask layer on the second region is greater than 0 and less than 50 a.

7. A semiconductor device obtained by the method of any one of claims 1 to 6, comprising at least:

a substrate including a first region and a second region;

a first stop layer disposed on sidewalls of the substrate and the metal gate;