CN111796961A - Data reading method, storage controller and storage device - Google Patents

Data reading method, storage controller and storage device Download PDF

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Publication number
CN111796961A
CN111796961A CN201910281488.2A CN201910281488A CN111796961A CN 111796961 A CN111796961 A CN 111796961A CN 201910281488 A CN201910281488 A CN 201910281488A CN 111796961 A CN111796961 A CN 111796961A
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bit
codeword
target
syndrome
read
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萧又华
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Shenzhen Daxin Electronic Technology Co ltd
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Shenzhen Daxin Electronic Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The invention provides a data reading method, a storage controller and a storage device. The method comprises the following steps: respectively performing reading operation on a target code word by using a preset reading voltage, a left preset reading voltage group and a right preset reading voltage group corresponding to the preset reading voltage to obtain a hard bit code word, a left bit code word and a right bit code word; performing iterative decoding operations on the hard bit codeword, the left bit codeword, and the right bit codeword, respectively, to identify a trusted codeword having a smallest syndrome among the hard bit codeword, the left bit codeword, and the right bit codeword; performing a correction operation on a log-likelihood ratio table of the iterative decoding operation using a hard bit codeword, the left bit codeword, the right bit codeword, and the trust codeword to update the log-likelihood ratio table to a corrected log-likelihood ratio table.

Description

Data reading method, storage controller and storage device
Technical Field
The present invention relates to a data reading method, and more particularly, to a data reading method suitable for a memory device configured with a rewritable nonvolatile memory module and a memory controller thereof.
Background
Generally, when an iterative decoding operation (e.g., a low density parity check code decoding operation) performed on a codeword read from a physical side of a rewritable non-volatile memory module fails, a memory controller of a memory device attempts to correct a log-likelihood ratio table corresponding to the iterative decoding operation according to verification data (e.g., known data stored in advance in the rewritable non-volatile memory module) so as to perform the iterative decoding operation on the read codeword again by using the corrected log-likelihood ratio table.
However, since the conventional method requires additional preparation of the known verification data (i.e., storing the known verification data in a plurality of word lines of the rewritable nonvolatile memory module), the conventional method uses the free space of the rewritable nonvolatile memory module to store the verification data, thereby reducing the remaining available space of the rewritable nonvolatile memory module, and further causing the operating efficiency of the memory device to be reduced due to the reduced remaining available space (since many management operations of the memory device require the use of the remaining available space).
Therefore, it is one of the subjects studied by those skilled in the art how to efficiently correct the log-likelihood ratio table corresponding to the iterative decoding operation without preparing verification data, so as to improve the defects of the conventional method, improve the performance of the decoding operation, and improve the data reading efficiency of the rewritable nonvolatile memory module.
Disclosure of Invention
The invention provides a data reading method, a storage controller and a storage device, which can correct a log-likelihood ratio table of iterative decoding operation by using soft information of a code word stored corresponding to a specific entity page and a trust code word corresponding to a minimum syndrome under the condition of not preparing verified data so as to strengthen the correct rate of the decoding operation of the code word stored corresponding to the specific entity page and further improve the efficiency of the reading operation of the corresponding code word, wherein the code word is not preset data or known verified data.
An embodiment of the present invention provides a data reading method for a storage device configured with a rewritable nonvolatile memory module. The rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The method comprises the following steps: performing a read operation on a target codeword stored in a target entity page of a target word line using a preset read voltage to obtain a hard bit codeword, wherein the hard bit codeword is stored in a hard bit buffer, and a plurality of target memory cells of the target entity page are used to store a plurality of target bit values of the target codeword, respectively; performing an iterative decoding operation on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining the hard bit syndrome as the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored to a trusted buffer to be a trusted codeword and a trusted syndrome; in response to the plurality of bit values of the trust syndrome not all being zero, performing the following steps: reading the target codeword using a left preset read voltage group and a right preset read voltage group corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword, and soft bit codewords corresponding to the left bit codeword and the right bit codeword, wherein the soft bit codewords are stored to a soft bit buffer; performing iterative decoding operations on the left bit codeword and the right bit codeword, respectively, to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword and a decoded right bit codeword corresponding to the right bit codeword and a left bit syndrome corresponding to the decoded right bit codeword, using the hard bit codeword and the soft bit codeword to form soft information corresponding to the target codeword, and using the soft information and the trusted codeword to perform a correction operation on a log likelihood ratio table of the iterative decoding operations to update the log likelihood ratio table to a corrected log likelihood ratio table; and performing the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the reading operation, thereby completing the reading operation, wherein a plurality of bit values of the final decoded codeword are used to represent the plurality of target bit values of the stored target codeword.
An embodiment of the present invention provides a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The storage controller includes: the circuit comprises a connection interface circuit, a memory interface control circuit, a reading auxiliary circuit unit, an error checking and correcting circuit and a processor. The connection interface circuit is used for being coupled to a host system. The memory interface control circuit is configured to be coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The processor is coupled to the connection interface circuit, the memory interface control circuit, the read assist circuit unit, and the error checking and correcting circuit. The processor is configured to select a target word line of the word lines of the rewritable nonvolatile memory module and select a target physical page of the target word line. The read assist circuit unit is configured to perform a read operation on a target codeword stored in a target physical page using a preset read voltage to obtain a hard bit codeword, where the hard bit codeword is stored in a hard bit buffer, and a plurality of target memory cells of the target physical page are configured to store a plurality of target bit values of the target codeword, respectively. The error checking and correcting circuit is configured to perform an iterative decoding operation on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining that the hard bit syndrome is the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored by the error checking and correcting circuit into a trusted buffer of the read assist circuit unit to become a trusted codeword and a trusted syndrome. In addition, in response to the plurality of bit values of the trust syndrome not all being zero, the read operation further comprises the following operations: the reading auxiliary circuit unit is configured to read the target codeword using a left preset reading voltage group and a right preset reading voltage group corresponding to the preset reading voltages, respectively, to obtain a left bit codeword, a right bit codeword, and a soft bit codeword corresponding to the left bit codeword and the right bit codeword, where the soft bit codeword is stored in a soft bit buffer of the reading auxiliary circuit unit; the error checking and correcting circuit is configured to perform iterative decoding operations on the left bit codeword and the right bit codeword, respectively, to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword, and a decoded right bit codeword corresponding to the right bit codeword and a left bit syndrome corresponding to the decoded right bit codeword; the read-assist circuit unit is configured to use the hard-bit codewords and the soft-bit codewords to compose soft information corresponding to the target codewords, and use the soft information and the trust codewords to perform a correction operation on a log-likelihood ratio table of the iterative decoding operation to update the log-likelihood ratio table to a corrected log-likelihood ratio table; and the error checking and correcting circuit is further configured to perform the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the read operation, thereby completing the read operation, wherein a plurality of bit values of the final decoded codeword are used to represent the plurality of target bit values of the stored target codeword.
An embodiment of the present invention provides a memory device. The storage device comprises a rewritable nonvolatile memory module, a memory interface control circuit and a processor. The rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The memory interface control circuit is used for being coupled to the rewritable nonvolatile memory module. The processor is coupled to the memory interface control circuit, and loads and executes the reading auxiliary program code module to realize the data reading method. The data reading method comprises the following steps: performing a read operation on a target codeword stored in a target entity page of a target wordline using a preset read voltage to obtain a hard bit codeword, wherein the hard bit codeword is stored in a hard bit buffer, wherein a plurality of target memory cells of the target entity page are used to store a plurality of target bit values of the target codeword, respectively, and the target wordline is selected from the plurality of wordlines of the rewritable non-volatile memory module; performing an iterative decoding operation on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining the hard bit syndrome as the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored to a trusted buffer to be a trusted codeword and a trusted syndrome; in response to the plurality of bit values of the trust syndrome not all being zero, performing the following steps: reading the target codeword using a left preset read voltage group and a right preset read voltage group corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword, and soft bit codewords corresponding to the left bit codeword and the right bit codeword, wherein the soft bit codewords are stored to a soft bit buffer; performing iterative decoding operations on the left bit codeword and the right bit codeword, respectively, to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword and a decoded right bit codeword corresponding to the right bit codeword and a left bit syndrome corresponding to the decoded right bit codeword, using the hard bit codeword and the soft bit codeword to form soft information corresponding to the target codeword, and using the soft information and the trusted codeword to perform a correction operation on a log likelihood ratio table of the iterative decoding operations to update the log likelihood ratio table to a corrected log likelihood ratio table; and performing the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the reading operation, thereby completing the reading operation, wherein a plurality of bit values of the final decoded codeword are used to represent the plurality of target bit values of the stored target codeword.
Based on the above, the data reading method, the memory controller and the memory device provided in the embodiments of the invention can perform the read assist operation on any programmed target word line corresponding to the target physical page of the target word line without preparing verified data. In the read-assist operation, the log-likelihood ratio table of the iterative decoding operation can be corrected by using the soft information of the codeword (the codeword is not preset data or known verification data) stored in the corresponding specific entity page and the trusted codeword with the smallest syndrome corresponding to the codeword without preparing verified data, so as to strengthen the accuracy of the decoding operation on the codeword stored in the specific entity page. Therefore, the correctness and the reliability of the data read from the target word line can be improved, the load of the decoding operation performed on the read data is reduced, and the overall efficiency of the data reading operation is improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1A is a block diagram of a host system and a storage device according to an embodiment of the invention;
FIG. 1B is a block diagram illustrating a soft information management circuit according to an embodiment of the invention;
FIG. 2 is a flow chart illustrating a data reading method according to an embodiment of the invention;
FIG. 3A is a diagram illustrating threshold voltage distributions of a plurality of memory cells corresponding to P Golay codes read by a read voltage set and storage states of corresponding physical pages according to an embodiment of the present invention;
FIG. 3B is a diagram illustrating a second read voltage pattern (2/3/2) according to one embodiment of the invention;
FIG. 3C is a diagram illustrating the generation of soft information for the storage status of a lower entity page according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating a data reading method according to another embodiment of the present invention;
FIG. 5 is a diagram illustrating generation of soft information of a storage status of a lower entity page according to another embodiment of the present invention;
fig. 6 is a diagram illustrating calculation of a plurality of log-likelihood ratio values of a corrected log-likelihood ratio table from a belief codeword, according to an embodiment of the invention.
Description of the reference numerals
10: host system
20: storage device
110. 211: processor with a memory having a plurality of memory cells
120: host memory
130: data transmission interface circuit
210: storage controller
212: data management circuit
213: memory interface control circuit
214: error checking and correcting circuit
215: read assist circuit unit
2151: soft information management circuit
2152: LLR table correction circuit
218: buffer memory
219: power management circuit
220: rewritable nonvolatile memory module
230: connection interface circuit
S31, S32, S33, S34, S35: flow steps of data reading method
S41, S42, S43, S44, S45, S46, S47, S48, S50, S51: process steps of distinguishing code mode setting method
V(1)1～V(i)7: read voltage
L: bit value of lower entity page
M: bit value of middle entity page
U: bit value of upper entity page
G1-G8: kuei code
SL1, SL 2: storage state of lower entity page
SM1, SM2, SM 3: memory state of middle entity page
SU1, SU2, SU3, SU4, SU 5: memory state of upper entity page
Voffset: testing voltage deviation values
A51, A61, A62, A71, A72, A73, A81, A82, A12-1 to A12-6, A13-1 to A13-8, A14-1 to A14-8, A15-1 to A15-8: arrow head
Detailed Description
In the embodiment, the memory device includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a memory device controller (also referred to as a memory controller or a memory control circuit). Further, the storage device is used with a host system so that the host system can write data to or read data from the storage device.
FIG. 1A is a block diagram of a host system and a storage device according to an embodiment of the invention.
Referring to fig. 1A, a Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, and a Data Transfer Interface Circuit (Data Interface Circuit) 130. In the present embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 are coupled to each other by a System Bus (System Bus).
The Memory device 20 includes a Memory Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a connection interface Circuit (connection interface Circuit) 230. The Memory controller 210 includes a processor 211, a data management Circuit (DataManagement Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.
In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.
In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of the data transmission interface circuits 130 may be one or more. The motherboard can be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.
In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data by using a Non-Volatile Memory interface (NVMe) protocol.
However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-eMI) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-P Package) interface standard, multimedia Memory Card (Multi-Media) interface, flash Memory standard (MMC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.
In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present exemplary embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.
The memory controller 210 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.
More specifically, the processor 211 in the memory controller 210 is computing hardware for controlling the overall operation of the memory controller 210. Specifically, the processor 211 has a plurality of control commands, and the control commands are executed to write, read and erase data when the memory device 20 is in operation.
It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.
In one embodiment, the memory controller 210 further has a read only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (bootstrap code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit of the rewritable nonvolatile memory module 220 dedicated for storing system data.
In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be referred to as operations performed by the storage controller 210.
The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory cells of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.
The memory interface control circuit 213 is used to receive an instruction from the processor 211, and cooperate with the data management circuit 212 to perform a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220.
For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units (also called target physical units) of the corresponding read instruction of the rewritable nonvolatile memory module 220; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.
In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence indicating to write data, a read command sequence indicating to read data, an erase command sequence indicating to erase data, and corresponding command sequences for indicating various memory operations (e.g., changing a plurality of preset read voltage values of a preset read voltage set for performing a read operation or a read assist operation, or performing a garbage collection procedure, etc.). The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), a three-dimensional NAND flash memory module (3D NAND flash memory), or a Vertical NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), or other flash memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.
In the embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each of the word lines is coupled to a plurality of memory cells. Multiple memory cells on the same word line constitute one or more physical programming units. In addition, a plurality of physical programming units can be combined into one physical unit (a physical block or a physical erasing unit). In the present embodiment, a Triple Level Cell (TLC) NAND flash memory module is taken as an example, i.e., in the following embodiments, a memory Cell capable of storing 3 bit values is taken as a Physical programming unit (i.e., in each programming operation, a programming voltage is applied to the Physical programming unit and then the Physical programming unit to program data), wherein each memory Cell can be divided into a Lower Physical Page (Lower Physical Page), a Middle Physical Page (Middle Physical Page), and an Upper Physical Page (Upper Physical Page) which can respectively store one bit value.
In this embodiment, the memory cell is used as the minimum unit for writing (programming) data. The physical cells are the minimum unit of erase, i.e., each physical cell contains the minimum number of memory cells that are erased together.
In the following embodiments, a third-Level flash memory module is taken as an example, and a Page-Level read assist operation (a read assist operation is performed on a plurality of memory cells of a specific physical Page) is performed on a specific physical Page (e.g., one of a lower physical Page, a middle physical Page, and an upper physical Page) of a specific word line in the third-Level flash memory module. The data reading method used in the read assist operation is also described below. However, the page-level read assist operation and data read method provided by the embodiments of the present invention can also be applied to other types of flash memory modules.
The memory controller 210 configures a plurality of logic units to the rewritable nonvolatile memory module 220. The host system 10 accesses the user data stored in the plurality of physical units through the configured logical unit. Here, each logical unit may be composed of one or more logical addresses. For example, a Logical unit may be a Logical block (Logical block), a Logical Page (Logical Page), or a Logical Sector (Logical Sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasing units. In this embodiment, the logic units are logic blocks, and the logic sub-units are logic pages. Each logic unit has a plurality of logic sub-units.
In addition, the memory controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record an address mapping relationship between a Logical unit (e.g., a Logical block, a Logical page, or a Logical sector) and a Physical unit (e.g., a Physical erase unit, a Physical program unit, a Physical sector) allocated To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may look up the entity unit mapped by a logic unit through the logical-to-entity address mapping table, and the memory controller 210 may look up the logic unit mapped by an entity unit through the entity-to-logic address mapping table. However, the technical concepts related to the mapping of the logical units and the physical units are conventional technical means for those skilled in the art and are not the technical solutions to be described in the present invention, and are not described herein again.
In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code. In addition, after the error checking and correcting process, if the read data is successfully decoded, the error checking and correcting circuit 214 may return the number of error bits to the processor 211.
In the present embodiment, the error checking and correcting circuit 214 performs an iterative decoding operation using a Low Density Parity Check (LDPC) algorithm. Specifically, after receiving the codeword to be decoded (also referred to as a target codeword or an original codeword), the error checking and correcting circuit 214 starts an iterative decoding operation on the received codeword, identifies a plurality of data bits of the received codeword, queries a Log Likelihood Ratio (LLR) table (also referred to as an LLR table) according to the plurality of data bits to obtain a plurality of Log Likelihood Ratio values of the corresponding plurality of data bits, and performs a round of iterative decoding operation on the codeword through the Log Likelihood Ratio values.
In this embodiment, each time the error checking and correcting circuit 214 completes one iteration of decoding operation performed on one of the codewords, the error checking and correcting circuit 214 may obtain the decoded codeword corresponding to the codeword and the syndrome corresponding to the decoded codeword. The error checking and correcting circuit 214 can determine whether the iterative decoding operation currently performed is decoding success or decoding failure according to the syndrome.
If the decoding fails, the error checking and correcting circuit 214 may determine whether to perform one or more subsequent iterative operations again according to the counted total number of iterative decoding operations performed on the codeword and a predetermined threshold value of iterative operations. If the total number is greater than the predetermined threshold, the error checking and correcting circuit 214 determines that the overall decoding operation (which may include one or more iterative decoding operations) of the codeword has failed, and outputs the finally obtained decoded codeword and the corresponding syndrome; if the total number of times is not greater than the predetermined threshold value of iteration times, the error checking and correcting circuit 214 performs a new iteration decoding operation again by using the obtained decoded codeword and the corresponding syndrome. The manufacturer can set the threshold value of the preset iteration number according to the requirement, but the invention is not limited thereto.
At the end of each (every) iteration of the decoding operation, the error checking and correcting circuit 214 calculates the syndrome corresponding to the decoded codeword that should be obtained last before to determine whether the iteration of the decoding operation is successful. If the decoding is successful (the generated code word after decoding is correct, namely, an effective code word), ending the iteration operation and ending the whole decoding operation of the code word; if the decoding fails (the codeword generated after decoding is an error, i.e., an invalid codeword), ending the current iteration operation and restarting a new iteration operation (next round) if the total number of times is not greater than the preset iteration time threshold value.
More specifically, during each iterative decoding operation, the error checking and correcting circuit 214 determines whether all of the bit values of the syndrome corresponding to the decoded codeword are zero. If all of the plurality of bit values of the syndrome are zero (i.e., "0"), the error checking and correcting circuit 214 determines that the decoded codeword is correct, completes the iterative decoding operation of this time, and completes the overall decoding operation corresponding to the codeword. Otherwise, if the bit values of the syndrome are not all zero (i.e., have one or more "1"), the error checking and correcting circuit 214 determines that the decoded codeword is erroneous, completes the iterative decoding operation, completes the overall decoding operation of the codeword, and outputs the decoded codeword. It should be noted that the above description is only used to explain the corresponding relationship between the original codeword and the decoded codeword and the corresponding syndrome, and the details of the iterative decoding operation of the low density parity check code algorithm, the original codeword, the syndrome and the decoded codeword are not technical solutions of the present invention and are not described herein again.
In one embodiment, the memory controller 210 further includes a buffer memory 218 and a power management circuit 219. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data (e.g., log likelihood ratio table) for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 218. The power management circuit 219 is coupled to the processor 211 and is used for controlling the power of the storage device 20.
In the present embodiment, the read assist circuit unit 215 includes a soft information management circuit 2151 and an LLR table correction circuit. The read assist circuit unit 215 is used to perform read assist operations on a particular physical page of a plurality of word lines. More specifically, the processor 211 may select one of the plurality of word lines belonging to the plurality of physical units (also referred to as a target word line) and a specific physical page of the target word line (also referred to as a target physical page) of the rewritable non-volatile memory module 220 at a specific time point, and instruct the read assist circuit unit 215 to perform a read assist operation on the target physical page of the target word line.
For example, the particular points in time include, but are not limited to: (1) when the decoding operation fails; (2) when reading the physical page of the word line with poor physical state (for example, the word line with more erase times, more read times, longer lifetime (retention time) or more error bit number); or (3) when the number of bits error of data read from a wordline exceeds a threshold number of bits error.
Specifically, when the number of bits of error of data read from a physical page corresponding to a wordline exceeds a threshold number of bits of error, the wordline is selected as the target wordline and the physical page is selected as the target physical page. It should be noted that the selected target word line has stored data, i.e., programmed data. In this embodiment, the stored data is not known data or verification data preset by a manufacturer or a system, for example, the stored data is user data.
In this embodiment, the soft information management circuit 2151 may perform soft information operations on a particular entity page (e.g., a target entity page) to obtain soft information. Before describing the operation of soft information, the concept of memory states is described. In the present embodiment, as described above, the target word line stores data. Specifically, the memory cells of each word line are programmed to store bit values corresponding to one of a plurality of different Gray codes (Gray codes), and the total number of the Gray codes is P. P is a first predetermined positive integer greater than 2, and the value of P is predetermined according to the type of the rewritable nonvolatile memory module 220. For example, if the rewritable nonvolatile memory module 220 is an MLC, P is 4; if the rewritable nonvolatile memory module 220 is SLC, P is 2; if the rewritable nonvolatile memory module 220 is QLC, P is 16.
For the sake of uniform description, the present embodiment is exemplified by a three-level flash memory module, and a plurality of memory cells of the target word line can store bit values corresponding to 8 gray codes (P ═ 8). The following describes details of the golay codes with reference to fig. 3A.
Fig. 3A is a schematic diagram illustrating threshold voltage distributions of a plurality of memory cells corresponding to P gray codes read by a read voltage group and storage states of corresponding physical pages according to an embodiment of the invention. Since the exemplary embodiment is described with reference to the rewritable non-volatile memory module 220 being a three-level cell NAND flash memory module, where P is equal to 8 (i.e., 2)3). Each memory cell of the three-rank memory cell NAND type flash memory module has three Physical pages for respectively storing bit data, and each memory cell includes a Lower Physical Page (L), a Middle Physical Page (M), and an upper Physical Page (U) that can respectively store one bit value. Assume that processor 211 reads voltages V (i) via read voltage set V (i)1～V(i)7Reading a plurality of memory cells (a plurality of target memory cells) of a target word line of a three-level cell NAND type flash memory module, and thereby identifying different bit values (respectively corresponding to the bit values of different Golay codes) stored by the plurality of memory cells. The gate voltage of each memory cell can be based on a predetermined read voltage V (i) in a set of read voltages V (i) (e.g., a set of predetermined read voltages corresponding to i equal to 1)1～V(i)7The other is 8 Golay codes, such as "L: 1M:1U: 1", "L: 1M:1U: 0", "L: 1M:0U: 1", "L: 0M:8 Golay codes of 0U:1, L:0M:0U:0, L:0M:1U:0 and L:0M:1U:1 (L: ' indicates the bit value of the lower entity page, M: ' indicates the bit value of the middle entity page, and U: ' indicates the bit value of the upper entity page). The 8 gray codes can also be represented as "111", "110", "100", "101", "001", "000", "010" and "011", 8 bit value combinations, wherein the bit values in each bit value combination are ordered according to the sequence of the lower, middle and upper physical pages. That is, by applying the read voltages V (i) of different voltage values of the read voltage group V (i)1～V(i)7To a memory cell of the target word line, the processor 211 may respectively determine that the bit value (also referred to as bit data or read bit value) stored in the memory cell corresponds to one of the plurality of gray codes ("111", "110", "100", "101", "001", "000", "010", and "011") according to whether the channel of the memory cell is turned on (i.e., the read bit value is read from a memory cell of the target word line by using the first read voltage group v (i)). It should be noted that the memory cells in the rewritable non-volatile memory module 220 may have a number of gray codes (in this example, 8), and the number of the read voltages in each read voltage group is equal to the number of the gray codes minus one (in this example, 7, i.e., N-1-8-1-7).
In more detail, the gray code stored in one memory unit may be sequentially combined through the storage State (SL) of the lower physical page, the storage State (SM) of the lower physical page, and the storage State (SU) of the upper physical page of the memory unit (as shown by the arrows in fig. 1A).
In the present embodiment, the preset read voltage V (i)4A storage state SL1 ("1") to distinguish the lower physical page from SL2 ("0"); preset read Voltage V (i)2And V (i)6Memory states SM1 ("1"), SM2 ("0"), and SM3 ("1") to distinguish the middle entity pages; preset read Voltage V (i)1、V(i)3、V(i)5、V(i)7Memory shape to distinguish upper physical pagesStates SU1 ("1"), SU2 ("0"), SU3 ("1"), SU4 ("0"), and SU5 ("1").
The processor 211 (or the read assist circuit unit 215) may sequentially read the word lines by using the preset read voltages corresponding to the lower physical page, the middle physical page, and the upper physical page in the preset read voltage set, so as to obtain the storage states of the lower physical page, the middle physical page, and the upper physical page of the plurality of memory cells of the word lines, and further obtain the gray codes of the plurality of memory cells. For example, assume that the processor 211 (or the read assist circuit unit 215) reads a word line using a set of preset read voltages v (i) to obtain a plurality of gray codes of a plurality of memory cells of the word line. The processor 211 (or the read assist circuit unit 215) first uses the preset read voltage V (i)4To identify whether the memory state of the lower physical page of all the memory cells is the memory state SL1 or the memory state SL 2; then, the processor 211 (or the read auxiliary circuit unit 215) uses the preset read voltage V (i)2、V(i)6To identify whether the storage state of the middle physical page of such memory cells is storage state SM1, storage state SM3, or storage state SM 3; then, the processor 211 (or the read auxiliary circuit unit 215) uses the preset read voltage V (i)1、V(i)3、V(i)5、V(i)7The storage state to identify the upper physical page of such storage units is storage state SU1, storage state SU2, storage state SU3, storage state SU4, or storage state SM 5. In this way, the processor 211 (or the read assist circuit unit 215) can identify the storage statuses of the lower physical page, the middle physical page, and the upper physical page of all the memory cells, and further identify the gray codes stored in all the memory cells.
In addition, the rewritable nonvolatile memory module 220 with the characteristics of the plurality of physical pages and the corresponding predetermined number of read voltages can also be regarded as a rewritable nonvolatile memory module 220 (three-level cell NAND-type flash memory module) with the first read voltage pattern (1/2/4). The "1/2/4" corresponds to the total number of the preset read voltages of the "lower/middle/upper physical pages", respectively.
For convenience of explaining the technical solutions provided by the present invention, in the following embodiments, the rewritable nonvolatile memory module 220 (three-level cell NAND flash memory module) having the first read voltage pattern (1/2/4) is mostly taken as an example for explanation. However, the data reading method and the memory controller provided by the present invention can also be applied to the rewritable nonvolatile memory module 220 with other reading voltage patterns.
FIG. 3B is a diagram illustrating a second read voltage pattern (2/3/2) according to one embodiment of the invention. Referring to FIG. 3B, the second read voltage pattern (2/3/2) is applied to the rewritable nonvolatile memory module 220 (three-level cell NAND flash memory module), read voltage V (i)1And V (i)5The storage states SL1 ("1"), SL2 ("0"), and SL3 ("1") to distinguish the lower physical page; read Voltage V (i)2、V(i)4And V (i)6Memory states SM1 ("1"), SM2 ("0"), SM3 ("1"), and SM4 ("0") to distinguish the middle entity pages; read Voltage V (i)3And V (i)7The memory states SU1 ("1"), SU2 ("0"), and SU3 ("1") to distinguish the upper entity page.
In the present embodiment, the threshold voltage distribution of the physical page of the memory cells of the word line may be shifted from the predetermined threshold voltage distribution. Due to the shift of the threshold voltage distribution, the preset read voltage originally corresponding to the preset threshold voltages of the plurality of physical pages is no longer suitable for distinguishing the storage states of the corresponding physical pages. In other words, in this case, the read bit values (also called hard bit values) stored in the plurality of memory cells of the originally read and identified physical page are distorted. At this time, it is necessary to perform a soft information operation to obtain soft information corresponding to the plurality of memory cells, so as to assist the processor 211 or the error checking and correcting circuit 214 to further identify the read bit values or the corresponding reliabilities stored in the plurality of memory cells (the reliability of the corresponding plurality of memory cells can be represented by the log-likelihood ratio of the corresponding plurality of memory cells).
FIG. 1B is a block diagram illustrating a soft information management circuit according to an embodiment of the invention. In the present embodiment, the soft information management circuit 2151 includes the soft information calculation circuit 216 and the buffer memory 217. Buffer memory 217 includes a plurality of buffers, such as trusted buffer 2171, hard bit buffer 2172, and soft bit buffers 2173(1) -2173 (N). N is a positive integer greater than or equal to 1. The buffer memory 217 is, for example, a static random access memory, and is used for temporarily storing data. The soft information calculating circuit 216 is used for calculating soft information according to the data buffered in the plurality of buffers. The details of the data reading method (also called as a read assist method) and the function of the read assist circuit unit 215 provided by the present invention are described below with reference to fig. 2. It should be noted that the operation of each component of the read assist circuit unit 215 can be regarded as the operation of the read assist circuit unit 215 as a whole.
Fig. 2 is a flowchart illustrating a data reading method according to an embodiment of the invention. Referring to fig. 2, in step S21, the read assist circuit unit 215 (or the soft information management circuit 2151) performs a read operation on a target codeword stored in a target physical page of a target word line using a preset read voltage to obtain a hard bit codeword (also called an original codeword), wherein the hard bit codeword is stored in the hard bit buffer 2172. Specifically, a plurality of read bit values read from a plurality of target memory cells of a target physical page using a predetermined read voltage constitute the hard bit codeword (also referred to as an original codeword). In addition, the selection manner of the target word line and the target entity page has already been described above, and is not described herein again. It should be noted that the present invention is not limited to the above-described selection. That is, if the processor 211 is going to perform a page-level read assist operation on a particular physical page, the particular physical page may be considered a target physical page and the wordline to which the particular physical page belongs may be considered a target wordline.
In step S22, the error checking and correcting circuit 214 performs an iterative decoding operation on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining the hard bit syndrome as the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored to a trusted buffer to become a trusted codeword and a trusted syndrome. Specifically, the original codeword (i.e., the hard bit codeword) is subjected to an iterative decoding operation (also referred to as an LDPC decoding operation) by the error checking and correction circuit 214. As described above, after a round of iterative decoding operation is completed, the error checking and correcting circuit 214 obtains a decoded codeword corresponding to the original codeword and a syndrome (also referred to as a hard bit syndrome) corresponding to the decoded codeword (also referred to as a decoded hard bit codeword). In addition, in the case where the trust buffer 2171 stores a trust syndrome and a corresponding trust codeword, the error checking and correcting circuit 214 further identifies the number of first bit values (i.e., "1") of the plurality of bit values of the hard bit syndrome and the trust syndrome stored in the trust buffer 2171, and determines the syndrome with the least first bit value of the hard bit syndrome and the trust syndrome as the smallest syndrome. In response to the hard bit syndrome being determined as the smallest syndrome, the error checking and correcting circuit 214 may store the hard bit syndrome and the corresponding decoded hard bit codeword into the trusted buffer 2171 to replace the original trusted codeword and trusted syndrome, thereby forming a new trusted codeword and trusted syndrome in the trusted buffer 2171.
On the other hand, in the case where trust buffer 2171 does not store any trust syndromes and corresponding trust codewords, error checking and correction circuit 214 (or soft information management circuit 2151) may directly treat the decoded hard bit codewords as trust codewords, treat the hard bit syndromes as corresponding trust syndromes, and store the hard bit syndromes and corresponding decoded hard bit codewords into trust buffer 2171.
In this embodiment, similar to the above-mentioned manner of determining success or failure of the iterative decoding operation, the error checking and correcting circuit 214 determines whether all of the bit values in the trust syndrome are zero. In response to determining that the plurality of bit values of the trust syndrome are not all zero, proceeding to step S23; in response to determining that the plurality of bit values of the trust syndrome are all zero, the process continues to step S27. In step S27, the read assist circuit unit 215 (or the error checking and correcting circuit 214) takes the trusted codeword as the final decoded codeword corresponding to the read operation to complete the read operation. Specifically, if all of the bit values of the trusted codeword are zero, the read assist circuit unit 215 (or the error checking and correcting circuit 214) determines that the trusted codeword is a valid codeword, the iterative decoding operation is successful, and correspondingly outputs the valid codeword (i.e., the finally decoded codeword) to complete the read operation.
In step S23, the read assist circuit unit 215 reads the target codeword using the left preset read voltage group and the right preset read voltage group corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword and a soft bit codeword corresponding to the left bit codeword and the right bit codeword, wherein the soft bit codeword is stored in a soft bit buffer. The following description is made with reference to fig. 3C, but it should be noted that the following embodiments are described with reference to the following entity page as an example of the target entity page, but the present invention is not limited thereto. Those skilled in the art can apply the data reading method of the present invention to other types of target physical pages, such as middle physical pages or upper physical pages, by referring to the example of the lower physical page.
Fig. 3C is a diagram illustrating generation of soft information of the storage status of a lower entity page according to an embodiment of the invention. Referring to FIG. 3C, it is assumed that the threshold voltage distribution can be divided into regions R1-R4 according to the soft information index values "1" to "4". In addition, in the embodiment, the read assist circuit 215 can use the predetermined access voltage V (i) for the storage states and hard bit values of the memory cells of the lower physical page4Corresponding preset read voltage V (i)4Left preset read voltage VL (i)4The right preset read voltage VR (i)4Reading the lower entity page to respectively obtain a plurality of storages corresponding to the lower entity pageA hard bit codeword of a cell. For example, the hard bit value of "1100" in the soft information regions corresponding to the soft information index value shown in FIG. 3C (the threshold voltage is at the predetermined read voltage V (i))4The bit value of the target memory cell on the left side is recognized as 1; threshold voltage at a predetermined read voltage V (i)4The bit value of the target memory cell on the right side is recognized as 0); corresponding to the left preset read voltage VL (i)4Left bit value of "1000" (critical voltage at left preset read voltage VL (i))4The bit value of the target memory cell at the left is recognized as 1, the critical voltage is at the left preset reading voltage VL (i)4The bit value of the target memory cell on the right side is recognized as 0); and corresponding to the right preset read voltage VR (i)4Right bit value of "1110" (threshold voltage at right preset read voltage VR (i))4The bit value of the target memory cell at the left is recognized as 1, the threshold voltage is at the right preset read voltage VR (i)4The bit value of the target memory cell on the right side is recognized as 0). The soft information areas comprise a left preset reading voltage VL (i)4A region R1 of the threshold voltage distribution corresponding to the soft information index "1" on the left; at a predetermined read voltage V (i)4And a left preset read voltage VL (i)4Region R2 of the threshold voltage distribution corresponding to the soft information index "2" therebetween; at a predetermined read voltage V (i)4And a right preset read voltage VR (i)4Region R3 of the threshold voltage distribution corresponding to the soft information index "3" therebetween; at the right preset read voltage VR (i)4The right side corresponds to region R4 of the threshold voltage distribution of soft information index "4".
In this embodiment, a plurality of hard bit values of the plurality of target memory cells may constitute the hard bit codeword, a plurality of left bit values of the plurality of target memory cells may constitute the left bit codeword, and a plurality of right bit values of the plurality of target memory cells may constitute the right bit codeword.
In the embodiment, the read assist circuit unit 215 can be based on a predetermined read voltage V (i)4To generate the corresponding preset read voltage V (i)4Left preset read voltage VL (i)4And a right preset read voltage VR (i)4. For example, the corresponding preset read voltage V (i)4Left preset read voltage VL (i)4For example, less than a predetermined read voltage V (i)4A voltage of a first preset voltage deviation value; the corresponding preset read voltage V (i)4Is a right preset read voltage VR (i)4For example, greater than a predetermined read voltage V (i)4The second preset voltage is deviated from the value of the voltage. The first preset voltage deviation value and the second preset voltage deviation value may be equal.
In this embodiment, the read assist circuit unit 215 (or the soft information management circuit 2151) may store the hard bit codeword into the hard bit buffer 2172 as indicated by arrow a 31.
As indicated by arrow a32, the read assist circuit unit 215 (or the soft information management circuit 2151) may subject the obtained left bit value and right bit value of the plurality of target memory cells to exclusive or operation (XOR operation) or exclusive nor operation (XNOR operation) to obtain an operation result, and treat the operation result as a soft bit value corresponding to the plurality of target memory cells. For example, the result of the XOR operation between the left bit value "1000" (representing the left bit value of each of the target memory cells in the regions R1 to R4 corresponding to the soft information indexes "1", "2", "3" and "4") and the right bit value "1110" (representing the right bit value of each of the target memory cells in the regions R1 to R4 corresponding to the soft information indexes "1", "2", "3" and "4") is "0110", which is the corresponding soft bit value "0110" (representing the soft bit value of each of the target memory cells in the regions R1 to R4 corresponding to the soft information indexes "1", "2", "3" and "4"). The soft-bit code words may be composed of a plurality of soft-bit values of a plurality of target memory cells.
Next, as indicated by arrow a33, the read assist circuit unit 215 (or the soft information management circuit 2151) may store the soft bit codeword into the soft bit buffer 2173 (1).
Referring to fig. 2 again, in step S24, the error checking and correcting circuit 214 performs iterative decoding operations on the left bit codeword and the right bit codeword respectively to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword and a decoded right bit codeword corresponding to the right bit codeword and a right bit syndrome corresponding to the decoded right bit codeword. This step is similar to step S22, and details thereof are not repeated here.
It should be noted that, in general conventional methods, an iterative decoding operation is not additionally performed on the left bit codeword and the right bit codeword, respectively, to obtain a corresponding decoded left bit codeword, the left bit syndrome, the right bit codeword, and the right bit syndrome. Because, in the conventional method, the left bit codeword and the right bit codeword are only used to constitute a soft bit codeword.
In this embodiment, since the iterative decoding operations are additionally performed on the left bit codeword and the right bit codeword, respectively, the error checking and correcting circuit 214 may further determine whether the left bit syndrome or the right bit syndrome is the minimum syndrome. Similarly, error checking and correction circuit 214 may compare either the left bit syndrome or the right bit syndrome to the trust syndrome present in trust buffer 2171 to find the smallest syndrome of the left bit syndrome, the right bit syndrome, and the trust syndrome having the least first bit value.
In response to determining that said left bit syndrome is the smallest syndrome, soft information management circuit 2151 stores said decoded left bit codeword and said left bit syndrome in said trust buffer 2171 to update said trust codeword and said trust syndrome; in response to determining that the right bit syndrome is the smallest syndrome, soft information management circuit 2151 stores the decoded right bit codeword and the right bit syndrome in trust buffer 2171 to update the trust codeword and the trust syndrome.
Next, in step S25, the soft information management circuit 2151 composes soft information corresponding to the target codeword using the hard bit codeword and the soft bit codeword, and the LLR table correction circuit 2152 performs a correction operation on the log-likelihood ratio table of the iterative decoding operation using the soft information and the trust codeword to update the log-likelihood ratio table to a corrected log-likelihood ratio table.
Referring back to fig. 3C, the soft information management circuit 2151 may combine the obtained soft bit value "0110" with the hard bit value "1100" (representing the hard bit values of the respective target memory cells of the regions R1-R4 corresponding to the soft information indexes "1", "2", "3", "4") to obtain soft information "10110100" (representing the soft information of the respective target memory cells of the regions R1-R4 corresponding to the soft information indexes "1", "2", "3", "4"). The first bit value of each bit pair (pair) (e.g., "10") of the soft information "10110100" is a hard bit value and the second bit value is a soft bit value.
In this way, according to the bit pair "10" in the soft information "10110100", the processor 211 or the error checking and correcting circuit 214 can know that the hard bit value "1" corresponding to the bit pair "10" is farther from the boundary of the threshold voltage distributions of the SL1 and the SL2, i.e., the hard bit value "1" has higher reliability; from the bit pair "11" in the soft information "10110100", the processor 211 or the error checking and correcting circuit 214 can know that the hard bit value "1" corresponding to the bit pair "11" is closer to the boundary of the threshold voltage distributions of the SL1 and the SL2, i.e., the hard bit value "1" has lower reliability; from the bit pair "01" in the soft information "10110100", the processor 211 or the error checking and correcting circuit 214 can know that the hard bit value "1" corresponding to the bit pair "01" is closer to the boundary of the threshold voltage distributions of the SL1 and the SL2, i.e., the hard bit value "0" has lower reliability; from the bit pair "00" in the soft information "10110100", the processor 211 or the error checking and correcting circuit 214 can know that the hard bit value "0" corresponding to the bit pair "00" is farther from the boundary of the threshold voltage distributions of the SL1 and the SL2, i.e., the hard bit value "0" has higher reliability.
In this embodiment, the LLR table correcting circuit 2152 specifically indicates the reliability and bit values corresponding to different soft information according to the log likelihood ratios corresponding to different soft information indexes in the log likelihood ratio table of the lower entity page. Specifically, the LLR table correcting circuit 2152 calculates the log-likelihood ratios corresponding to different soft information indexes by using the following formula to correct the plurality of log-likelihood ratios of the previously preset log-likelihood ratio table.
Figure BDA0002021808350000151
Said "SIi"indicates soft information index," Pr (X ═ 0| SIi) "indicates that soft information index" SI "corresponds toi"probability that the bit value of the memory cell of the region R1 (i.e., the target memory cell) is" 0 ", and" Pr (X ═ 1| SIi) "indicates that the soft information index" SI "corresponds toi"probability that the bit value of the memory cell of the region R1 is" 1 ", CNT (X ═ 0 ═ SI-i) "indicates belonging to Soft information index" SIi"total number of a plurality of memory cells having bit value" 0 "in the trust code word of the region R1," CNT (X ═ 1 ═ n SI ═ SIi) "indicates belonging to Soft information index" SIi"total number of a plurality of memory cells having bit value" 1 "in the trust code word of the region R1," CNT (SI)i) "indicates belonging to Soft information index" SIi"the total number of the plurality of memory cells of the region R1.
Fig. 6 is a diagram illustrating calculation of a plurality of log-likelihood ratio values of a corrected log-likelihood ratio table from a belief codeword, according to an embodiment of the invention. Referring to fig. 6, for example, as shown in table 600, the LLR table correcting circuit 2152 may count the total number of the target memory cells having the bit value "0" and the total number of the target memory cells having the bit value "1" in the regions R1-R4 corresponding to different soft information index values according to the soft information of the target memory cells having the bit value "0" in the trusted codeword and the soft information of the target memory cells having the bit value "1" in the trusted codeword.
For example, the LLR table correction circuit 2152 selects one of the trust codewords as "Bit value of 0 "(which corresponds to a memory cell), and soft information index value corresponding to the memory cell is identified as SI1. Next, the LLR table correcting circuit 2152 accumulates the soft information index SI1Is the total number of bit values "0" (i.e., the SI index to the original soft information)1Plus 1) the total number of bit values of "0"). By analogy, the LLR table correction circuit 2152 selects the next bit value in the trusted codeword and accumulates the corresponding total number according to the selected bit value of "0" or "1" and the corresponding soft information index value. The statistical results are shown in table 600.
After obtaining the statistical results, the LLR table correcting circuit 2152 calculates log-likelihood ratios corresponding to different soft information indices according to the above formula (i.e., performs a correction operation) to obtain a corrected log-likelihood ratio table. E.g. for SI1，LLR(SI1) Ln (5/17497) ═ 8.1603468042105194090619179701932. The LLR table correction circuit 2152 then rounds "-8.1603468042105194090619179701932" to an integer bit of "-8". The obtained corrected log-likelihood ratio table can be used to update the original log-likelihood ratio table. It should be noted that, in the above example, the LLR table correcting circuit 2152 simplifies the calculated log-likelihood ratio value by "rounding", but the present invention is not limited thereto. For example, in other embodiments, the LLR table correction circuit 2152 may utilize an "unconditional carry-to-integer bit" or "unconditional discard decimal point" approach to simplify the calculated log-likelihood ratio values. Alternatively, the calculated log-likelihood ratio value is reduced to a specific type of value by other suitable methods.
In this embodiment, if the log-likelihood ratio value corresponding to one soft information index is a negative number, it indicates that the bit value stored in the corresponding memory cell should be "1", and a smaller log-likelihood ratio value indicates that the probability that the bit value stored in the corresponding memory cell is "1" is higher; if the log-likelihood ratio value corresponding to one soft information index is a positive number, it indicates that the bit value stored in the corresponding memory cell should be "0", and a larger log-likelihood ratio value indicates that the probability that the bit value stored in the corresponding memory cell is "0" is higher.
Next, in step S26, the error checking and correcting circuit 214 performs the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the reading operation, thereby completing the reading operation. Specifically, after obtaining a more accurate corrected log-likelihood ratio table corresponding to the target entity page, the error checking and correcting circuit 214 may perform one or more iterative decoding operations on the soft information according to the corrected log-likelihood ratio table to obtain a successfully decoded valid codeword (also referred to as a final decoded codeword). As described above, the plurality of bit values of the syndrome corresponding to the valid codeword are all zero.
After the final decoded codeword is obtained, the error checking and correcting circuit 214 determines that the read operation of the target codeword stored corresponding to the target physical page is complete. The plurality of bit values of the final decoded codeword is used to represent the plurality of target bit values read from the stored target codeword.
In an embodiment, after obtaining the final decoded codeword (or valid codeword), LLR table correction circuit 2152 may perform the correction operation on the log-likelihood ratio table of the iterative decoding operation again using the soft information for the target codeword and the final decoded codeword to update the corrected log-likelihood ratio table of the iterative decoding operation again. Similar to the above, the LLR table correcting circuit 2152 may select a bit value corresponding to a memory cell from the finally decoded codeword, and further accumulate the total number of the bit values of the corresponding soft information index value according to the soft information corresponding to the memory cell/bit value. And after statistics of corresponding soft information indexes of all bit values of the finally decoded code word is completed, calculating log likelihood ratios corresponding to different soft information index values to obtain a corrected log likelihood ratio table.
Furthermore, in an embodiment, after updating the log likelihood ratio table corresponding to the target entity page in the iterative decoding operation to a corrected log likelihood ratio table, the error checking and correcting circuit 214 performs the iterative decoding operation on the soft information again according to the corrected log likelihood ratio table to obtain the decoded hard bit codeword corresponding to the hard bit codeword and the hard bit syndrome corresponding to the decoded hard bit codeword. In particular, since the log-likelihood ratio table of the iterative decoding operation has been corrected, a more accurate decoded codeword can be obtained via the corrected log-likelihood ratio table. In this regard, the error checking and correction circuit 214 may again perform the iterative decoding operation on the soft information in the hope of obtaining a more correct valid codeword.
It should be noted that, in the above embodiment, the number of the left preset read voltages corresponding to the preset read voltage is 1, and the number of the right preset read voltages corresponding to the preset read voltage is 1, but the invention is not limited thereto. For example, in another embodiment, the number of left preset read voltages corresponding to the preset read voltage is N, and the number of right preset read voltages corresponding to the preset read voltage is N. The buffer memory 217 may have N soft bit buffers 2173(1) -2173 (N) for N left preset read voltages and N right preset read voltages. The following description will be made with reference to fig. 4.
Fig. 4 is a flowchart illustrating a data reading method according to another embodiment of the present invention. Referring to fig. 4, steps S41, S42, S44, S47, S48, and S49 of the data reading method according to the another embodiment are the same as steps S21, S22, S23, S25, S26, and S27 of the data reading method in fig. 2, and details are not repeated. Only the differences are explained below.
In step S43, the read assist circuit unit 215 (or the soft information management circuit 2151) reads the target codeword using an ith left preset read voltage of the N left preset read voltages and an ith right preset read voltage of the N right preset read voltages corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword, and a soft bit codeword corresponding to the left bit codeword and the right bit codeword, where the soft bit codeword is stored to an ith soft bit buffer of the N soft bit buffers, where i is a positive integer and an initial value is 1, and a maximum value of i is N, where N is a positive integer. The i is used to represent the arrangement sequence of the left preset read voltage/the right preset read voltage currently selected to generate the soft bit. The following description will be made with reference to fig. 5.
Fig. 5 is a diagram illustrating generation of soft information of a storage state of a lower entity page according to another embodiment of the present invention. Referring to FIG. 5, it is assumed that the threshold voltage distribution can be divided into regions R1-R6 according to the soft information index values "1" to "6" and N is 2. Corresponding to the preset read voltage V (i)4Has 2 preset read voltages, which are respectively the left preset read voltage VL (i)4And a left preset read voltage VL (i)4'; corresponding to the preset read voltage V (i)4There are 2 preset right read voltages, VR (i)4And a right preset read voltage VR (i)4'. Wherein, the left preset reading voltage VL (i)4And a left preset read voltage VL (i)4' the voltage difference between them is a first preset voltage deviation value; right preset read voltage VR (i)4' and Right preset read Voltage VR (i)4The voltage difference between the first and second preset voltage deviation values is a second preset voltage deviation value.
Similar to FIG. 3C, the soft information management circuit 2151 can use the predetermined read voltage V (i)4Left preset read voltage VL (i)4(1 st of the 2 left preset read voltages, left preset read voltage) and the right preset read voltage VR (i)4' (the 1 st of the 2 right preset read voltages) to obtain a hard bit codeword "111000" (hard bit values for the plurality of memory cells corresponding to regions R1-R6, respectively) and a soft bit codeword "001100" (soft bit values for the plurality of memory cells corresponding to regions R1-R6, respectively), storing the hard bit codeword "111000" (arrow a31) to a hard bit buffer 2172, and storing the soft bit codeword "001100" (arrow a32) to a hard bit buffer 2173 (1). Then, the error checking and correcting circuit 214 executes step S44. It should be noted that at this point in time, N equals 2 and i equals 1.
Next, in step S45, the soft information management circuit 2151 determines whether i is equal to N. In response to determination that i is equal to N, the soft information management circuit 2151 executes step S47; in response to determining that i is not equal to N, the soft information management circuit 2151 performs step S46. In step S46, the soft information management circuit 2151 adds 1 to i, and proceeds to step S43.
In this example, since i is not equal to N, i is added by 1 to become 2. That is, the soft information management circuit 2151 selects the 2 nd left preset read voltage of the 2 left preset read voltages and the 2 nd right preset read voltage of the 2 right preset read voltages to perform step S43. Referring to FIG. 5, the soft information management circuit 2151 further utilizes the left predetermined read voltage VL (i)4' to obtain a left bit codeword "100000" (corresponding to the left bit values of the plurality of memory cells of the regions R1-R6, respectively), and using a right preset read voltage VR (i)4' to obtain a right bit codeword "111110" (corresponding to the right bit values of the plurality of memory cells of regions R1-R6, respectively). Next, as indicated by an arrow a50, the soft information management circuit 2151 may calculate a soft bit codeword "011110" (corresponding to soft bit values of a plurality of storage cells of the regions R1-R6, respectively) from the left bit codeword "100000" and the right bit codeword "111110" via an XOR operation, and store the soft bit codeword "011110" in another soft bit buffer 2173(2) (as indicated by an arrow a 51). The process continues to step S44 and step S45.
At this time, in step S45, the soft information management circuit 2151 determines that i is equal to N (because i is equal to 2), and then proceeds to step S47. For example, the soft information management circuit 2151 composes soft information "100101111011001000" (soft information of a plurality of memory cells respectively corresponding to the regions R1 to R6) from the hard bit codeword "111000", the soft bit codeword "001100", and the soft bit codeword "011110" (step S47). For example, the soft information of the memory cell belonging to the region R2 corresponding to the soft information index "2" is "101".
In this other embodiment, the total number of bit values of the soft information of each memory cell is "3", which is equal to N +1, but the present invention is not limited thereto. The manufacturer may set the total number of bit values of the soft information from each memory cell on demand and set the value of N accordingly.
It should be noted that, in the above embodiments, the read assist circuit unit 215 is implemented by a hardware circuit, but the invention is not limited thereto. For example, in one embodiment, the read assist circuit unit 215 may be implemented in software as a read assist code module having the functionality of the read assist circuit unit 215. The read assist code module may include a soft information management code module and an LLR table correction code module. The soft information management program code module is a program code module with the function of the soft information management circuit 2151; the LLR table correction program code module is a program code module with the function of an LLR table correction circuit. The processor 211 can access and execute the read assist code module (or the soft information management code module and the LLR table correction code module) to implement the data reading method (or the read assist method) provided by the present invention.
In summary, the data reading method, the memory controller and the memory device provided by the embodiments of the invention can perform the read assist operation on any programmed target word line corresponding to the target physical page of the target word line without preparing verified data. In the read-assist operation, the log-likelihood ratio table of the iterative decoding operation can be corrected by using the soft information of the codeword (the codeword is not preset data or known verification data) stored in the corresponding specific entity page and the trusted codeword with the smallest syndrome corresponding to the codeword without preparing verified data, so as to strengthen the accuracy of the decoding operation on the codeword stored in the specific entity page. Therefore, the correctness and the reliability of the data read from the target word line can be improved, the load of the decoding operation performed on the read data is reduced, and the overall efficiency of the data reading operation is improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (17)

1. A data reading method applied to a storage device configured with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value, the method comprising:
performing a read operation on a target codeword stored in a target entity page of a target word line using a preset read voltage to obtain a hard bit codeword, wherein the hard bit codeword is stored in a hard bit buffer, and a plurality of target memory cells of the target entity page are used to store a plurality of target bit values of the target codeword, respectively;
performing an iterative decoding operation on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining the hard bit syndrome as the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored to a trusted buffer to be a trusted codeword and a trusted syndrome;
in response to the plurality of bit values of the trust syndrome not all being zero, performing the following steps:
reading the target codeword using a left preset read voltage group and a right preset read voltage group corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword, and soft bit codewords corresponding to the left bit codeword and the right bit codeword, wherein the soft bit codewords are stored to a soft bit buffer;
performing iterative decoding operations on the left bit codeword and the right bit codeword, respectively, to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword and a decoded right bit codeword corresponding to the right bit codeword and a left bit syndrome corresponding to the decoded right bit codeword,
using the hard bit codewords and the soft bit codewords to compose soft information corresponding to the target codewords, and using the soft information and the trust codewords to perform a correction operation on a log-likelihood ratio table of the iterative decoding operation to update the log-likelihood ratio table to a corrected log-likelihood ratio table; and
performing the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the read operation, thereby completing the read operation, wherein a plurality of bit values of the final decoded codeword are used to represent the plurality of target bit values of the stored target codeword.
2. A data reading method according to claim 1, the method further comprising:
in response to determining that the left bit syndrome is the smallest syndrome, the decoded left bit codeword and the left bit syndrome are stored to the trust buffer to update the trust codeword and the trust syndrome,
wherein in response to determining that the right bit syndrome is the smallest syndrome, the decoded right bit codeword and the right bit syndrome are stored to the trust buffer to update the trust codeword and the trust syndrome.
3. A method of reading data according to claim 2, wherein in response to all of the plurality of bit values of the trust syndrome being zero, the method further comprises:
taking the trusted codeword as the final decoded codeword corresponding to the read operation to complete the read operation.
4. A method of data reading according to claim 1, wherein after obtaining the final decoded codeword, the method further comprises:
performing the correction operation again on the log-likelihood ratio table of the iterative decoding operation using the soft information and the final decoded codeword to update the corrected log-likelihood ratio table of the iterative decoding operation again.
5. A data reading method according to claim 1, wherein after updating the corrected log-likelihood ratio table, the method further comprises:
and performing the iterative decoding operation on the soft information again according to the corrected log-likelihood ratio table to obtain the decoded hard bit codeword corresponding to the hard bit codeword and the hard bit syndrome corresponding to the decoded hard bit codeword.
6. A data reading method according to claim 1, wherein
The voltage value of the left preset read voltage corresponding to the preset read voltage is the voltage value of the preset read voltage minus a first preset voltage offset value,
wherein a voltage value of the right preset read voltage corresponding to the preset read voltage is the voltage value of the preset read voltage plus a second preset voltage offset value.
7. The data reading method according to claim 6, wherein the first preset voltage deviation value is equal to the second preset voltage deviation value.
8. The data reading method according to claim 7, wherein the step of reading the target codeword using the left preset read voltage group and the right preset read voltage group corresponding to the preset read voltages respectively to obtain the left bit codeword, the right bit codeword and the soft bit codeword corresponding to the left bit codeword and the right bit codeword comprises:
reading the target codeword stored in the target physical page using a left-assist read voltage to obtain a left bit value of each of the plurality of target memory cells, wherein the left bit values of the plurality of target memory cells constitute the left bit codeword;
reading what the target physical page stores using a right auxiliary read voltage to obtain a right bit value of each of the plurality of target memory cells, wherein the right bit values of the plurality of target memory cells constitute the right bit codeword; and
performing an XOR operation or an XNOR operation on the left bit value and the right bit value of each of the plurality of target memory cells, and regarding the obtained first operation result corresponding to the XOR operation or the obtained second operation result corresponding to the XNOR operation as a soft bit value of each of the plurality of target memory cells, wherein a plurality of soft bit values of the plurality of target memory cells constitute the soft bit codeword.
9. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:
a connection interface circuit for coupling to a host system;
a memory interface control circuit coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value;
a read assist circuit unit;
an error checking and correcting circuit; and
a processor coupled to the connection interface circuit, the memory interface control circuit, the read assist circuit unit, and the error checking and correcting circuit,
wherein the processor is to select a target wordline of the plurality of wordlines of the rewritable non-volatile memory module and to select a target physical page of the target wordline,
wherein the read assist circuit unit is configured to perform a read operation on a target codeword stored in a target physical page using a preset read voltage to obtain a hard bit codeword, wherein the hard bit codeword is stored in a hard bit buffer, wherein a plurality of target memory cells of the target physical page are configured to store a plurality of target bit values of the target codeword respectively,
wherein the error checking and correcting circuit is further configured to perform iterative decoding operations on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining the hard bit syndrome as the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored by the error checking and correcting circuit into a trusted buffer of the read assist circuit unit to be a trusted codeword and a trusted syndrome,
wherein the read operation further comprises the following operations in response to the plurality of bit values of the trust syndrome not all being zero:
the read assist circuit unit is configured to read the target codeword using a left preset read voltage group and a right preset read voltage group corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword, and a soft bit codeword corresponding to the left bit codeword and the right bit codeword, where the soft bit codeword is stored in a soft bit buffer of the read assist circuit unit,
wherein the error checking and correcting circuit is configured to perform iterative decoding operations on the left bit codeword and the right bit codeword, respectively, to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword, and a decoded right bit codeword corresponding to the right bit codeword and a left bit syndrome corresponding to the decoded right bit codeword,
wherein the read assist circuit unit is configured to use the hard bit codewords and the soft bit codewords to compose soft information corresponding to the target codewords and use the soft information and the trust codewords to perform a correction operation on a log-likelihood ratio table of the iterative decoding operation to update the log-likelihood ratio table to a corrected log-likelihood ratio table,
wherein the error checking and correcting circuit is further configured to perform the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the read operation, thereby completing the read operation, wherein a plurality of bit values of the final decoded codeword are used to represent the plurality of target bit values of the stored target codeword.
10. The storage controller of claim 9, wherein
In response to determining that the left bit syndrome is the smallest syndrome, the error checking and correction circuitry stores the decoded left bit codeword and the left bit syndrome in the trusted buffer to update the trusted codeword and the trusted syndrome,
wherein in response to determining that the right bit syndrome is the smallest syndrome, the error checking and correction circuitry stores the decoded right bit codeword and the right bit syndrome in the trusted buffer to update the trusted codeword and the trusted syndrome.
11. The memory controller of claim 10, wherein the plurality of bit values in response to the trust syndrome are all zero,
the read assist circuit unit takes the trusted codeword as the final decoded codeword corresponding to the read operation to complete the read operation.
12. The memory controller of claim 9, wherein after obtaining the final decoded codeword,
the read assist circuit unit performs the correction operation on the log likelihood ratio table of the iterative decoding operation again using the soft information and the finally decoded codeword to update the corrected log likelihood ratio table of the iterative decoding operation again.
13. The storage controller of claim 9, wherein after updating the corrected log-likelihood ratio table,
the error checking and correcting circuit performs the iterative decoding operation on the soft information again according to the corrected log-likelihood ratio table to obtain the operations of the decoded hard bit codeword corresponding to the hard bit codeword and the hard bit syndrome corresponding to the decoded hard bit codeword.
14. The storage controller of claim 9, wherein
The voltage value of the left preset read voltage corresponding to the preset read voltage is the voltage value of the preset read voltage minus a first preset voltage offset value,
wherein a voltage value of the right preset read voltage corresponding to the preset read voltage is the voltage value of the preset read voltage plus a second preset voltage offset value.
15. The memory controller of claim 14, wherein the first preset voltage offset value is equal to the second preset voltage offset value.
16. The memory controller of claim 15, wherein in operation of the read assist circuit unit to read the target codeword using the left and right preset read voltage sets corresponding to the preset read voltages respectively to obtain the left and right bit codewords and the soft bit codewords corresponding to the left and right bit codewords,
the read-assist circuit unit reads the target codeword stored in the target physical page using a left-assist read voltage to obtain a left-bit value of each of the target memory cells, wherein the left-bit values of the target memory cells form the left-bit codeword,
wherein the read-assist circuit unit reads what the target physical page stores using a right-assist read voltage to obtain a right-bit value for each of the plurality of target memory cells, wherein the plurality of right-bit values for the plurality of target memory cells form the right-bit codeword,
wherein the read assist circuit unit performs an XOR operation or an XNOR operation on the left bit value and the right bit value of each of the plurality of target memory cells, and takes the obtained first operation result corresponding to the XOR operation or the obtained second operation result corresponding to the XNOR operation as a soft bit value of each of the plurality of target memory cells, wherein a plurality of soft bit values of the plurality of target memory cells constitute the soft bit codeword.
17. A storage device, the storage device comprising:
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value;
a memory interface control circuit for coupling to the rewritable nonvolatile memory module; and
a processor coupled to the memory interface control circuit, wherein the processor loads and executes the read assist code module to implement a data reading method, the data reading method comprising the steps of:
performing a read operation on a target codeword stored in a target entity page of a target wordline using a preset read voltage to obtain a hard bit codeword, wherein the hard bit codeword is stored in a hard bit buffer, wherein a plurality of target memory cells of the target entity page are used to store a plurality of target bit values of the target codeword, respectively, and the target wordline is selected from the plurality of wordlines of the rewritable non-volatile memory module;
performing an iterative decoding operation on the hard bit codeword to obtain a decoded hard bit codeword corresponding to the hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword, wherein in response to determining the hard bit syndrome as the smallest syndrome, the decoded hard bit codeword and the hard bit syndrome are stored to a trusted buffer to be a trusted codeword and a trusted syndrome;
in response to the plurality of bit values of the trust syndrome not all being zero, performing the following steps:
reading the target codeword using a left preset read voltage group and a right preset read voltage group corresponding to the preset read voltages, respectively, to obtain a left bit codeword, a right bit codeword, and soft bit codewords corresponding to the left bit codeword and the right bit codeword, wherein the soft bit codewords are stored to a soft bit buffer;
performing iterative decoding operations on the left bit codeword and the right bit codeword, respectively, to obtain a decoded left bit codeword corresponding to the left bit codeword and a left bit syndrome corresponding to the decoded left bit codeword and a decoded right bit codeword corresponding to the right bit codeword and a left bit syndrome corresponding to the decoded right bit codeword,
using the hard bit codewords and the soft bit codewords to compose soft information corresponding to the target codewords, and using the soft information and the trust codewords to perform a correction operation on a log-likelihood ratio table of the iterative decoding operation to update the log-likelihood ratio table to a corrected log-likelihood ratio table; and
performing the iterative decoding operation on the soft information according to the corrected log-likelihood ratio table to obtain a final decoded codeword corresponding to the read operation, thereby completing the read operation, wherein a plurality of bit values of the final decoded codeword are used to represent the plurality of target bit values of the stored target codeword.
CN201910281488.2A 2019-04-09 2019-04-09 Data reading method, storage controller and storage device Pending CN111796961A (en)

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