CN111781545A - Port state management circuit, method, device and readable storage medium - Google Patents
Port state management circuit, method, device and readable storage medium Download PDFInfo
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- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
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Abstract
The application provides a port state management circuit, a method, a device and a readable storage medium, wherein the port state management circuit comprises: the control chip is provided with a control pin and an analog sampling pin; and the signal acquisition circuit is connected with the control pin and the analog sampling pin of the control chip and is connected with each port to be detected. The signal acquisition circuit is used for acquiring the voltage of the connected ports according to the control signal when receiving the control signal sent by the control pin and feeding back the total voltage value of each acquired port to the control chip through the analog sampling pin; the control chip is used for determining the state of each port connected with the signal acquisition circuit according to the total voltage value; wherein, the total voltage values corresponding to the different state combinations of the collected ports are different. According to the method and the device, the pin resources can be minimized through the analog signals, so that one analog sampling pin can be correspondingly used for detecting the states of a plurality of ports, and the limitation on the pin resources is reduced.
Description
Technical Field
The present disclosure relates to the field of port status detection technologies, and in particular, to a port status management circuit, a port status management method, a port status management apparatus, and a readable storage medium.
Background
In electronic products, there is a need for managing the status of ports. At present, a General implementation manner is realized by a GPIO (General Purpose Input/Output) of a PLD (Programmable Logic Device) or an MCU (Micro Controller Unit). Specifically, each GPIO of the PLD or MCU is connected to a port to be managed, so as to determine the port state according to the state signal acquired by each GPIO.
However, with the development of electronic technology, many electronic devices have more ports, for example, desktop optical interface devices have a maximum of 52 ports. At this time, with a single PLD or MCU, due to the limitation of the number of GPIOs, there may be a problem that the pin resources are insufficient, and the state management for all ports of the electronic device cannot be realized. At this time, the number of PLDs or MCUs must be increased, which results in an increase in the Printed Circuit Board (PCB) layout and a more complicated Circuit on the PCB, and also results in an increase in the cost due to the need to increase the number of PLDs or MCUs.
Disclosure of Invention
An object of the embodiments of the present application is to provide a port state management circuit, a method, an apparatus, and a readable storage medium, so as to solve the technical problems that when an existing port state management circuit implements port state management for an electronic device with a plurality of ports, the number of PLDs or MCUs needs to be increased, which results in an increase in PCB layout and makes a circuit on a circuit board more complicated.
An embodiment of the present application provides a port state management circuit, including: the control chip is provided with a control pin and an analog sampling pin; the signal acquisition circuit is connected with the control pin and the analog sampling pin of the control chip and is connected with each port to be detected; the signal acquisition circuit is used for acquiring the voltage of the connected ports according to the control signal when receiving the control signal sent by the control pin and feeding back the total voltage value of each acquired port to the control chip through the analog sampling pin; the control chip is used for determining the state of each port connected with the signal acquisition circuit according to the total voltage value; the total voltage values corresponding to the collected different state combinations of the ports are different.
In the implementation process, the signal acquisition circuit is respectively connected with the ports to be detected, so that the total voltage value of each port is acquired, and different port state combination conditions can be determined according to different total voltage values because the total voltage values corresponding to different state combinations of the acquired ports are different.
For example, voltage values of two ports are collected, assuming that voltages respectively corresponding to the two ports (port 1 and port 2) in an accessed state are a1 and a2, a voltage corresponding to the two ports in the accessed state is A3(a1, a2 and A3 are not equal), and a voltage corresponding to the two ports in an unaccessed state is 3.3V, then when the total voltage is 3.3V, it can be determined that no port is in the accessed state, when the total voltage value is a1, it can be determined that only port 1 is in the accessed state, when the total voltage value is a2, it can be determined that only port 2 is in the accessed state, and when the total voltage value is A3, it can be determined that both port 1 and port 2 are in the accessed state.
Therefore, the overall state detection can be carried out on the plurality of ports acquired by the signal acquisition circuit at the same time through different total voltage values acquired by the signal acquisition circuit. Therefore, through the mixed detection of multiple paths of signals, the pin resources are minimized through the analog signals, so that one analog sampling pin can be correspondingly used for detecting the states of a plurality of ports, the limitation on the pin is reduced, the necessity of increasing the number of PLDs or MCUs is reduced when the port state management of electronic equipment with more ports is realized, compared with the related technology, the PCB layout is reduced to a certain extent, and the circuit on the circuit board is simpler.
Furthermore, the number of the signal acquisition circuits is one or more; when the signal acquisition circuit is a plurality of, more than one signal acquisition circuit is connected with the same control pin.
In the implementation process, one control chip can realize state monitoring on m × N (m is the number of ports connected to one signal acquisition circuit, and N is the number of signal acquisition circuits) ports at most through the multi-channel signal acquisition circuit, so that the port state detection capability of the control chip is greatly expanded, and the necessity of increasing the number of PLDs or MCUs is reduced. Meanwhile, the acquisition control of a plurality of signal acquisition circuits can be realized through one control pin (a digital signal pin such as a GPIO pin can be adopted), so that the digital signal pin resource can be saved.
Furthermore, each signal acquisition circuit comprises a gating control circuit and two paths of acquisition sub-circuits; the two acquisition sub-circuits are respectively connected with different ports to be detected; the gating control circuit is used for gating one of the two acquisition sub-circuits according to the received control signal sent by the control pin.
It should be understood that a digital signal typically has two different signal values, a logic "0" level signal and a logic "1" level signal. When the scheme of the embodiment of the present application is adopted, it is obvious that as the number of the ports acquired by one signal acquisition circuit increases, the number of the port state combinations of the signal acquisition circuit increases (if the voltage values of m ports are acquired at a time, then 2 existsm(m power of 2) port state combination conditions, and 2 m power total voltage values exist), the control chip has larger processing amount when determining the state of each port connected with the signal acquisition circuit according to the total voltage values. In the implementation process, each signal acquisition circuit comprises a gating control circuit and two acquisition sub-circuits, so that one path of control signals transmitted by the control pins can be gated for acquisition (two control signals, namely a logic '0' level signal and a logic '1' level signal, are used for gating different acquisition sub-circuits respectively), the number of ports acquired each time can be reduced on the premise that one signal acquisition circuit can correspondingly acquire enough voltage values of the ports, and the processing pressure of the control chip is reduced.
Furthermore, the signal acquisition circuit also comprises a pull-up voltage; the first acquisition sub-circuit of the two acquisition sub-circuits comprises a first triode, and the second acquisition sub-circuit of the two acquisition sub-circuits comprises a second triode; the collector electrodes of the first triode and the second triode are connected with the pull-up voltage, and the base electrodes of the first triode and the second triode are respectively connected with the gating control circuit; and all ports connected with the first path of acquisition sub-circuit are connected in parallel to the emitting electrode of the first triode, and all ports connected with the second path of acquisition sub-circuit are connected in parallel to the emitting electrode of the second triode.
When the triode is used as a switch, the conduction of the triode can be controlled through the signal input of the collector of the triode. Therefore, in the implementation process, the triode is arranged in the acquisition sub-circuit, so that two control signals, namely a logic '0' level signal and a logic '1' level signal, can effectively control the conduction of the two acquisition sub-circuits.
Further, the gate control circuit includes: the signal access circuit and the third triode; the input end of the signal access circuit is connected with the control pin, and the output end of the signal access circuit is connected with the base electrode of the second triode and the base electrode of the third triode; a collector of the third triode is connected with the pull-up voltage and is connected with a base of the first triode, and an emitter of the third triode is grounded; the first triode, the second triode and the third triode are NPN type triodes.
In the implementation process, when the input control signal is a logic "1" signal, the signal reflected on the circuit is a high level, so that the second transistor Q2 and the third transistor Q3 are turned on. And the third triode Q3 is conducted, so that the pull-up voltage is grounded, the base voltage of the first triode Q1 is 0, the collector and the emitter of the first triode Q1 are not conducted, and the second triode Q2 is conducted, so that the second path of collecting sub-circuit is gated, and the port voltage value is collected. When the input control signal is a logic '0' signal, the signal is reflected to be a low level on the circuit, so that the collector and the emitter of the second triode Q2 and the third triode Q3 are not conducted, at the moment, due to the action of a pull-up voltage VDD, the base voltage of the first triode Q1 is VDD, and the collector and the emitter of the first triode Q1 are conducted, so that the first path of acquisition sub-circuit is gated to acquire the voltage value of the port.
Furthermore, each port connected with the first path of acquisition sub-circuit is connected in parallel to an emitter of the first triode through resistors with different resistance values; and all ports connected with the second path of acquisition sub-circuit are connected in parallel to an emitting electrode of the second triode through resistors with different resistance values.
It is generally assumed that the voltage values generated by the ports in the switched-in state are approximately the same. In order to ensure that the voltage values acquired by different ports in the access state are different, and therefore port state identification is facilitated, in the implementation process, resistors with different resistance values are connected in parallel at the ports, namely the acquired voltage values are different due to the voltage division effect of the resistors when the different ports are in the access state.
An embodiment of the present application further provides a port state management method, which is applied to any one of the port state management circuits, and includes: when any analog sampling pin receives a voltage value fed back by the signal acquisition circuit, determining a port set corresponding to the analog sampling pin according to a preset corresponding relation between the analog sampling pin and the port set; matching the voltage value with each standard voltage value corresponding to the pre-stored port set; different standard voltage values correspond to different state combinations of each port in the port set; and determining the state of each port in the port set according to the matched standard voltage value.
In the embodiment of the present application, by acquiring and storing the standard voltage values corresponding to different state combinations of each port in each set in advance, when any analog sampling pin of the port state management circuit receives a voltage value fed back by the signal acquisition circuit, a port set corresponding to the analog sampling pin can be determined according to a preset corresponding relationship between the analog sampling pin and the port set, and then the standard voltage values received by the analog sampling pin are matched with the standard voltage values of the port set corresponding to the analog sampling pin, so that the states of each port in the port set are determined according to the matched standard voltage values, and the state detection of the port is realized.
For example, assume that the port set is a set of port 1 and port 2, and has standard voltage values of 3.3V, A1, a2 and A3, the state combination corresponding to the standard voltage value of 3.3V is that no port is in an access state, the state combination corresponding to the standard voltage value a1 is that only port 1 is in an access state, the state combination corresponding to the standard voltage value a2 is that only port 2 is in an access state, and the state combination corresponding to the standard voltage value A3 is that both port 1 and port 2 are in an access state. Assuming that the voltage value received by the analog sampling pin is a1, it can be determined that port 1 is in the connected state and port 2 is in the non-connected state.
Through the implementation mode, the high-density state signal detection function can be realized based on a simple circuit structure, the resource shortage scheme design is facilitated, and the practical value is high.
Further, the method further comprises: and sequentially controlling the control pins to send control signals to the signal acquisition circuits according to a preset period.
An embodiment of the present application further provides a port state management device, which is applied to any one of the port state management circuits, and includes: the device comprises a determining module, a matching module and a processing module; the determining module is used for determining a port set corresponding to an analog sampling pin according to a preset corresponding relation between the analog sampling pin and the port set when any analog sampling pin receives a voltage value fed back by the signal acquisition circuit; the matching module is used for matching the voltage value with each standard voltage value corresponding to the pre-stored port set; different standard voltage values correspond to different state combinations of each port in the port set; and the processing module is used for determining the state of each port in the port set according to the matched standard voltage value.
An embodiment of the present application further provides a readable storage medium, where one or more programs are stored, and the one or more programs are executable by one or more processors to implement any one of the centralized gateway deployment methods described above.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1-1 is a schematic structural diagram of a port state management circuit having a signal acquisition circuit according to an embodiment of the present application;
fig. 1-2 are schematic structural diagrams of a port state management circuit having a plurality of signal acquisition circuits according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a signal acquisition circuit using an NPN type transistor according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a signal acquisition circuit using a PNP triode according to an embodiment of the present disclosure;
fig. 4-1 is a schematic structural diagram of a signal acquisition circuit controlled by a single control signal according to an embodiment of the present disclosure;
fig. 4-2 is a schematic structural diagram of another single-control-signal-controlled signal acquisition circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a port state management method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a specific port state management circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a specific signal acquisition circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a port status management device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
The first embodiment is as follows:
in order to solve the problems that in the multi-port state detection process, the use of a plurality of PLDs or MCUs leads to the increase of the PCB layout and makes the circuit on the circuit board more complicated, embodiments of the present application provide a port state management circuit and a port state management method implemented based on the port state management circuit.
Referring to fig. 1-1 and fig. 1-2, in the embodiment of the present application, the port state management circuit may include a control chip and a signal acquisition circuit. Wherein:
the control chip may be a PLD chip or an MCU, which has a control pin and an analog sampling pin.
The signal acquisition circuit is respectively connected with the control pin and the analog sampling pin of the control chip and respectively connected with each port (namely each port to be detected) which needs to be subjected to state detection.
In the embodiment of the application, the signal acquisition circuit is used for acquiring the voltage of the connected port according to the control signal when receiving the control signal sent by the control pin, and feeding back the acquired total voltage value of each port to the control chip through the analog sampling pin.
And the control chip is used for determining the state of each port connected with the signal acquisition circuit according to the total voltage value.
It should be noted that, in the embodiment of the present application, in order to enable different port state combinations to generate different total voltage values, and enable the control chip to accurately determine the states of the ports connected to the signal acquisition circuit according to the total voltage values, the ports acquired by the signal acquisition circuit need to be set, and the corresponding total voltage values should be different in different state combinations.
It should be noted that for a port, it has two states: one is an access state, that is, the port is accessed to the electronic device, and the port is used by the electronic device and forms a load loop with the electronic device, so as to generate voltage; and the other is an unaccessed state, namely the port is not accessed into the electronic equipment and is not used, and the port does not generate voltage.
The different state combinations refer to state combinations of a plurality of ports. For example, for the case of acquiring two ports at a time, there are 4 state combinations, i.e., both ports are in an unaccessed state, one of the two portsThe port is in the accessed state, the other port is in the unaccessed state, and both ports are in the accessed state. In general, one signal acquisition circuit acquires k (k is 1 or more) ports, and then the k ports have 2k(the k power of 2) state combinations.
In the embodiment of the application, the total voltage values corresponding to the ports acquired by one signal acquisition circuit at one time are different under different state combinations through circuit design or setting of control parameters of the ports. For example, resistors with different resistance values can be set at the connection ends of the signal acquisition circuit and each port, so that the acquired voltages of different ports in the access state can be different, and the corresponding total voltage values under different state combinations are different.
It should be noted that in the embodiment of the present application, there may be only one signal acquisition circuit connected to the control chip, for example, as shown in fig. 1-1. At this time, all the ports to be detected are subjected to circuit acquisition by the signal acquisition circuit.
It should be understood that although in theory, detection of the state of any number of ports may be achieved by one signal acquisition circuit. However, when there are too many ports to be acquired by one signal acquisition circuit at a time, the combination of different states present in the signal acquisition circuit increases exponentially. There are two problems with this: one is as follows: when the control chip determines the state of each port connected with the signal acquisition circuit according to the acquired total voltage value, the detection efficiency is affected due to overlarge workload; the second step is as follows: too many different state combinations may also cause difficulties in circuit design, since different state combinations need to correspond to different total voltage values. Therefore, in the embodiment of the present application, the number of ports acquired by a single signal acquisition circuit at a time may be set within a certain range, for example, the number of ports acquired by a single signal acquisition circuit at a time may be set to not exceed 10.
In this case, when the number of ports acquired by a single signal acquisition circuit at a time is set, in order to manage the port states of the electronic device having a large number of ports, the port states may be managed by adding a signal acquisition circuit.
Therefore, in the embodiment of the present application, the signal acquisition circuit may be provided in plurality, for example, as shown in fig. 1 to 2. The number of the signal acquisition circuits to be set can be determined according to the number of ports to be actually detected and the number of ports to which a single signal acquisition circuit can be connected. For example, assuming that one signal acquisition circuit defines that a maximum of 8 ports can be connected, assuming that the number of ports actually required to be detected is 64, at least 8 signal acquisition circuits need to be provided.
It should be noted that, in the embodiment of the present application, each signal acquisition circuit feeds back to the control chip the total voltage value of each acquired port, where the total voltage value is an analog signal, and therefore, an analog sampling pin capable of receiving and identifying the analog signal in the control chip needs to be used to connect with the signal acquisition circuit. The control pin for controlling the signal acquisition circuit to work is not limited, and can be realized by a digital signal pin, such as a GPIO pin.
In the embodiment of the present application, when a plurality of signal acquisition circuits are provided, in order to save pin resources of the control chip, more than one signal acquisition circuit of the plurality of signal acquisition circuits may be connected to the same control pin.
For example, referring to fig. 1-2, the circuits shown in fig. 1-2 have a total of N (N is 2 or more) signal acquisition circuits, where every N signal acquisition circuits are connected to the same control pin. Therefore, the n signal acquisition circuits can be controlled to simultaneously acquire the port voltage through one control pin.
It should be noted that the value of N should be an integer greater than or equal to 1 and less than or equal to N, and the specific value thereof can be determined by an engineer according to actual needs. For example, when the resources of the control pins are sufficient, n may be set to 1, that is, each control pin is connected to only one signal acquisition circuit.
It should be understood that it has been described in the foregoing that the number of ports acquired at one time by each signal acquisition circuit is not necessarily too large. And, as for the control signal, it can output two signals, i.e., a logic "0" level signal and a logic "1" level signal. Therefore, in the embodiment of the present application, a gating control circuit and two paths of acquisition sub-circuits may be set up in each signal acquisition circuit, so as to control the gating of the two paths of acquisition sub-circuits in each signal acquisition circuit according to the logic "0" level signal and the logic "1" level signal output by the control pin. Therefore, one control signal can correspondingly control and gate one path of acquisition sub-circuit, so that the signal acquisition circuit can only acquire the port connected with one path of acquisition sub-circuit when one acquisition is carried out, and the number of the ports which can be connected with the whole signal acquisition circuit can be increased on the premise of ensuring that the number of the ports acquired each time is not too large.
In the embodiment of the present application, the two acquisition sub-circuits of each signal acquisition circuit may be respectively connected to different ports (i.e., ports to be detected) that need to be subjected to state detection. And the gating control circuit is connected with the control pin and used for gating one of the two acquisition sub-circuits according to a received control signal sent by the control pin.
For example, assuming that the number of ports to which each signal acquisition circuit is connected is m as shown in fig. 1-1 and fig. 1-2, the two-way acquisition sub-circuit of each signal acquisition circuit may be set to be connected with m1 ports and m2 ports, respectively. Wherein m1 and m2 are integers of 1 or more, and the sum of m1 and m2 is m.
It should be understood that the values of m1 and m2 can be determined by engineers according to actual needs, and m1 and m2 can be equal to m/2 for convenience of management and circuit layout, wherein m is required to be a double number.
It should also be understood that in fig. 1-2, the number of ports connected to each signal acquisition circuit may be different, and specifically, the number of ports connected to each signal acquisition circuit may be set by an engineer according to actual needs.
In the embodiment of the present application, the structure of a signal acquisition circuit can be seen in fig. 2. The signal acquisition circuit can be provided with a pull-up voltage VDD, a first acquisition sub-circuit in the two acquisition sub-circuits comprises a first triode Q1, a second acquisition sub-circuit in the two acquisition sub-circuits comprises a second triode Q2, collectors of a first triode Q1 and a second triode Q2 are connected with the pull-up voltage VDD, bases of the first triode and the second triode are respectively connected with a gating control circuit, m1 ports are connected with an emitting electrode of the first triode Q1 in parallel, and m2 ports are connected with an emitting electrode of the second triode Q2 in parallel.
Specifically, the gating control circuit comprises a signal access circuit and a third triode Q3, wherein the input end of the signal access circuit is connected with the control pin, and the output end of the signal access circuit is connected with the base electrode of the second triode Q2 and the base electrode of the third triode Q3. The collector of the third triode Q3 is connected to the pull-up voltage VDD and is connected to the base of the first triode Q1, and the emitter of the third triode Q3 is grounded.
At this time, when the input control signal is a logic "1" level signal, the signal reflected on the circuit is a high level, i.e., the base electrodes of the second transistor Q2 and the third transistor Q3 input a high level, and the collector electrodes and the emitter electrodes of the second transistor Q2 and the third transistor Q3 are turned on. And the collector and the emitter of the second triode Q2 are conducted, namely the second path of collecting sub-circuit is gated to collect the voltage value of the port. And because the third triode Q3 is conducted, the pull-up voltage is connected to the ground in a pressing mode, and further the base voltage of the first triode Q1 is 0, so that the collector and the emitter of the first triode Q1 are not conducted, and the gating operation of the second path of acquisition sub-circuit is realized.
When the input control signal is a logic "0" level signal, the signal reflected on the circuit is a low level, i.e., the base electrodes of the second transistor Q2 and the third transistor Q3 input a low level, and the collector electrodes and the emitter electrodes of the second transistor Q2 and the third transistor Q3 are not conductive. At this time, for the first triode Q1, since the collector and the emitter of the third triode Q3 are not conductive, the base voltage of the first triode Q1 is the pull-up voltage VDD, so that the collector and the emitter of the first triode Q1 are conductive, the first path of collecting sub-circuit is gated, and the port voltage value is collected.
It should be noted that, in the embodiment of the present application, one end of the collector of the first transistor Q1 and one end of the collector of the second transistor Q2 may be connected to an analog sampling pin of the control chip, so as to implement feedback of the total collected voltage value of each port.
It should be further noted that, in order to make the total voltage values corresponding to different state combinations of the ports different, in the circuit structure described above, in the first path of collecting sub-circuit, m1 ports may be connected in parallel to the emitter of the first triode Q1 through resistors with different resistance values, and in the first path of collecting sub-circuit, m2 ports may be connected in parallel to the emitter of the second triode Q2 through resistors with different resistance values.
Illustratively, the resistance values of the resistors can adopt a step difference form (such as 10K Ω, 8K Ω, 6K Ω, 4K Ω, and the like), so that the sampling and identification of the control chip can be more convenient after the signal acquisition circuit is driven to work.
It should be noted that in the structure of fig. 2, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are NPN transistors. In the embodiment of the present application, besides being implemented by using an NPN type triode, the PNP type triode may also be implemented by using a PNP type triode, and at this time, since the PNP type triode is turned on when the control signal is a logic "0" level signal, the connection structure of the signal access circuit needs to be modified to a certain extent with respect to fig. 2, which is shown in fig. 3.
At this time, since the PNP transistor is turned on when the control signal is a logic "0" level signal, the emitter sets of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are connected to the pull-up voltage VDD, and are connected to the collectors of the first transistor Q1 and the second transistor Q2 in parallel with the m1 ports and the m2 ports, respectively. The collector of the third transistor Q3 is not grounded and is directly connected to the base of the first transistor Q1.
At this time, when the input control signal is a logic "0" level signal, the signal reflected on the circuit is a low level, i.e., the base electrodes of the second transistor Q2 and the third transistor Q3 input a low level, and the collector electrodes and the emitter electrodes of the second transistor Q2 and the third transistor Q3 are turned on. And the collector and the emitter of the second triode Q2 are conducted, namely the second path of collecting sub-circuit is gated to collect the voltage value of the port. And because the third triode Q3 is conducted, the pull-up voltage is connected into the base electrode of the first triode Q1, so that the collector electrode and the emitter electrode of the first triode Q1 are not conducted, and the gating operation of the second path of acquisition sub-circuit is realized.
When the input control signal is a logic "1" level signal, the signal reflected on the circuit is a high level, i.e., the base electrodes of the second transistor Q2 and the third transistor Q3 input a high level, and the collector electrodes and the emitter electrodes of the second transistor Q2 and the third transistor Q3 are not conductive. At this time, for the first triode Q1, since the collector and the emitter of the third triode Q3 are not conductive, the base voltage of the first triode Q1 of the first triode Q1 is a low-level voltage, so that the collector and the emitter of the first triode Q1 are conductive, the first path of collecting sub-circuit is gated, and the port voltage value is collected.
It should be noted that, in the embodiment of the present application, one end of the emitters of the first transistor Q1 and the second transistor Q2 may be connected to an analog sampling pin of the control chip, so as to implement feedback on the total voltage value collected at each port.
It should be understood that fig. 3 is an equivalent circuit in nature, which is an adaptation made in conjunction with the characteristics of the PNP transistor based on the structure shown in fig. 2.
It should be noted that, in order to make the total voltage values corresponding to different state combinations of the ports different, in the circuit structure shown in fig. 3, in the first path of collecting sub-circuit, m1 ports may be connected in parallel to the collector of the first triode Q1 through resistors with different resistance values, and in the second path of collecting sub-circuit, m2 ports may be connected in parallel to the collector of the second triode Q2 through resistors with different resistance values.
It should be understood that, in the embodiment of the present application, each NPN type transistor in fig. 2 may also be implemented by using an N-channel MOS transistor, and each PNP type transistor in fig. 3 may also be implemented by using a P-channel MOS transistor. Besides, the gating circuit and the switching element with other structures can be adopted to realize the gating of the two acquisition sub-circuits. In fact, any circuit structure that can gate the two acquisition sub-circuits according to the logic "0" level signal and the logic "1" level signal can be adopted in the embodiments of the present application.
In the above-described configurations shown in fig. 2 and 3, in order to prevent short-circuit and the like, a resistor may be provided between the pull-up voltage VDD and each transistor, and a resistor may be provided at an input terminal of the signal access circuit.
It should be understood that the signal acquisition circuit in the embodiment of the present application may also be configured to perform voltage value acquisition only when the control pin outputs a logic "0" level signal and a logic "1" level signal, for example, see the single signal acquisition circuit shown in fig. 4-1 and 4-2. For the structure shown in fig. 4-1, the circuit is turned on when the control pin outputs a logic "1" level signal, thereby realizing voltage acquisition of the port; for the structure shown in fig. 4-2, the circuit is turned on when the control pin outputs a logic "0" level signal, thereby realizing the voltage acquisition of the port.
It should be noted that the foregoing fig. 4-1 and 4-2 are only two possible signal acquisition circuit implementation structures for port voltage acquisition under a single control signal exemplified by the present application, and it should not be understood that the present application can be implemented only by using the foregoing two signal acquisition circuits.
It should be noted that, in the embodiments of the present application, R1 to R11 in the drawings represent resistances.
Based on the port state management circuit, an embodiment of the present application further provides a port state management method applied to the port state management circuit, as shown in fig. 5, including:
s501: and when any analog sampling pin receives a voltage value fed back by the signal acquisition circuit, determining a port set corresponding to the analog sampling pin according to a preset corresponding relation between the analog sampling pin and the port set.
In this embodiment, after the port state management circuit is implemented, the total voltage values corresponding to all port state combinations may be collected for the ports to which the signal acquisition circuits are connected in advance, and each collected total voltage value is used as a standard voltage value and stored in the database in association with the corresponding port state combination.
Meanwhile, in the embodiment of the application, the corresponding relation between the analog sampling pin and the port set can be established. Since each analog sampling pin is connected with a signal acquisition circuit with determined identity, and the port connected with the signal acquisition circuit is also determined, the corresponding relation between the analog sampling pin and the port set can be constructed.
S502: and matching the received voltage value with each standard voltage value corresponding to the pre-stored port set.
In the embodiment of the application, if the signal acquisition circuit has two paths of acquisition sub-circuits which are gated according to different control signals. At this time, each path of the acquisition sub-circuit corresponds to one port sub-set. Therefore, in the corresponding relation between the analog sampling pin and the port set, the ranges of two port subsets in the port set can be clear.
When the received voltage value is matched with each standard voltage value corresponding to the pre-stored port set, the port subset corresponding to the analog sampling pin can be determined according to the control signal output by the signal acquisition circuit, and then the received voltage value is matched with each standard voltage value corresponding to the port subset.
S503: and determining the state of each port in the port set according to the matched standard voltage value.
In the embodiment of the present application, in consideration of the influence of a complex external environment during the actual voltage collection process, even for the same port state combination, a certain amount of fluctuation may exist in the voltage value collected each time. Therefore, in the embodiment of the present application, a certain floating threshold range may be set, so that when a difference value between a received voltage value and a certain standard voltage value is within the floating threshold range, the received voltage value is considered to be matched with the standard voltage value, and thus, it is determined that a port state combination corresponding to the standard voltage value is the current actual state of each currently acquired port.
For example, assuming that the port set is a set of port 1 and port 2, and has standard voltage values of 3.3V, A1, a2, and A3(a1 is not equal to a2), the state combination corresponding to the standard voltage value of 3.3V is that no port is in an access state, the state combination corresponding to the standard voltage value a1 is that only port 1 is in an access state, the state combination corresponding to the standard voltage value a2 is that only port 2 is in an access state, and the state combination corresponding to the standard voltage value A3 is that both port 1 and port 2 are in an access state. Assuming that the voltage value received by the analog sampling pin is a1, it can be determined that port 1 is in the connected state and port 2 is in the non-connected state.
In the embodiment of the application, each control pin can be sequentially controlled to send a control signal to each signal acquisition circuit according to a preset period, so that port detection is performed periodically.
It should be noted that the port state management method provided in the embodiment of the present application may be implemented by designing a corresponding software system.
The port state management circuit and the port state management method provided in the embodiment of the application are respectively connected with each port through the signal acquisition circuit, so that the total voltage value of each port is acquired, and different port state combination conditions can be determined according to different total voltage values because the acquired total voltage values corresponding to different state combinations of each port are different. Therefore, through the mixed detection of multiple paths of signals, the pin resources are minimized through the analog signals, so that one analog sampling pin can be correspondingly used for detecting the states of a plurality of ports, the limitation on the pin is reduced, the necessity of increasing the number of PLDs or MCUs is reduced when the port state management of electronic equipment with more ports is realized, compared with the related technology, the PCB layout is reduced to a certain extent, and the circuit on the circuit board is simpler.
Example two:
in this embodiment, on the basis of the first embodiment, a specific port state management circuit is taken as an example to exemplify the scheme of the present application.
Referring to fig. 6 and 7, the control chip has control pins S (1) to S (N/4), and analog sampling pins AVIN (1) to AVIN (N).
The control pins S (1) to S (N/4) are used to select the signal acquisition circuit that is required for acquisition, where N denotes the nth signal acquisition circuit. 1 control signal can drive 4 signal acquisition circuits, and 8 ports are connected to a signal acquisition circuit, so that the collection of state signals of 32 ports can be realized by one control signal. By analogy, if the collection of status signals for 32 ports needs to be realized, N/4 control pins need to be adopted.
The analog sampling pins AVIN (1) to AVIN (n) are used for sampling the port status signals (i.e., the total voltage value) integrated by the signal acquisition circuit.
It should be noted that the ST 1-STM signals in the figure are transition signal inputs of the ports, which may be '1' or '0' states, and are converted into model voltage signals after being input to the signal acquisition circuit.
In the embodiment of the present application, referring to fig. 7, the signal acquisition circuit divides 8 ST signals into 2 groups and connects them together in parallel, and the signals are driven by the transistor and form a voltage division relationship with the series connection of resistors at the collector of the transistor. Each group of ST signals has 4 resistors, and the resistance values of the 4 resistors form step differences (such as 10K omega, 8K omega, 6K omega and 4K omega), so that the signal acquisition circuit can more conveniently control the chip to sample and identify after driving work.
Meanwhile, the signal acquisition circuit realizes 2 groups of state signal switching sampling through three triodes of Q1, Q2 and Q3, and saves control signal resources.
And a port state management software is realized in the control chip, and the software forms a management database according to the total voltage value generated by different port state combinations in the actual sampling process. For example, each set of state signals used in this embodiment has 4 resistors connected in parallel (e.g., 10K Ω, 8K Ω, 6K Ω, 4K Ω), so that different port state combinations may generate total voltage values, and different total voltage values may represent different port state combinations.
After the system is started normally, software can control each control pin to send a control signal to each signal acquisition circuit in sequence according to a preset period, so that the signal acquisition circuits are controlled to acquire according to actual needs.
Specifically, the gating of the signal acquisition circuit is first controlled by the control signal S.
For example, the output of the control signal S1 is "0", which indicates that the control signal acquisition circuit 1, 2, 3, 4 acquires the status signals of the ports (1, 2, 3, 4), (9, 10, 11, 12), (17, 18, 19, 20), (25, 26, 27, 28); the output of S1 is "1", which indicates that the control signal acquisition circuits 1, 2, 3, 4 acquire status signals of ports (5, 6, 7, 8), (13, 14, 15, 16), (21, 22, 23, 24), (29, 30, 31, 32); according to actual requirements, the execution of the N/4 control signals is completed.
While the control signal switching is performed, the total voltage is sampled by AVIN (1) to AVIN (4). For example, when the control signal output at S1 is a logic "0" level signal, the AVIN (1) to AVIN (4) respectively obtain the total voltages of (1, 2, 3, 4), (9, 10, 11, 12), (17, 18, 19, 20), (25, 26, 27, 28), and the total voltages of the other group (5, 6, 7, 8), (13, 14, 15, 16), (21, 22, 23, 24), (29, 30, 31, 32) are acquired in a state where the control signal is at "1" level. By analogy, the collection of the voltage of the N-8 ports can be realized at most through the S (N/4) signal.
And searching and matching the acquired mixed state signal data (namely the total voltage) in a database so as to obtain the actual state of each current port.
The scheme of the embodiment of the application can realize the high-density port state detection function by using the minimum GPIO resources, reduces the necessity of increasing the number of PLDs or MCUs, and has higher practical value compared with the related technology. Meanwhile, the scheme of the embodiment of the application belongs to a low-cost circuit, the area of a PCB is saved, and the complexity of layout and wiring is reduced.
Example three:
based on the same inventive concept, the embodiment of the application also provides a port state management device. Referring to fig. 8, fig. 8 shows a port state management device 100 corresponding to the method according to the first embodiment. It should be understood that the specific functions of the port state management device 100 can be referred to the above description, and the detailed description is appropriately omitted here to avoid redundancy. The port state management device 100 includes at least one software functional module that can be stored in a memory in the form of software or firmware or solidified in the port state management device 100. Specifically, the method comprises the following steps:
referring to fig. 8, the port state management apparatus 100 is applied to the port state management circuit provided in the first embodiment, and includes: a determination module 101, a matching module 102 and a processing module 103. Wherein:
the determining module 101 is configured to determine, when any analog sampling pin receives a voltage value fed back by the signal acquisition circuit, a port set corresponding to the analog sampling pin according to a preset corresponding relationship between the analog sampling pin and the port set;
the matching module 102 is configured to match the voltage value with each standard voltage value corresponding to the pre-stored port set; different standard voltage values correspond to different state combinations of each port in the port set;
the processing module 103 is configured to determine a state of each port in the port set according to the matched standard voltage value.
In this embodiment of the application, the processing module 103 is further configured to sequentially control each of the control pins to send a control signal to each of the signal acquisition circuits according to a preset period.
It should be understood that, for the sake of brevity, the contents described in some embodiments are not repeated in this embodiment.
In addition, this embodiment also provides a readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash Memory, a usb (Secure Digital Memory Card), an MMC (Multimedia Card), etc., in which one or more programs implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the port state management method in the first embodiment. And will not be described in detail herein.
It should be understood that, in the description of the readable storage medium in the previous paragraph, the processor may be the control chip described in the embodiments of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In this context, a plurality means two or more.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A port state management circuit, comprising:
the control chip comprises a control pin and an analog sampling pin;
the signal acquisition circuit is connected with the control pin and the analog sampling pin of the control chip and is connected with each port to be detected;
the signal acquisition circuit is used for acquiring the voltage of the connected ports according to the control signal when receiving the control signal sent by the control pin and feeding back the total voltage value of each acquired port to the control chip through the analog sampling pin;
the control chip is used for determining the state of each port connected with the signal acquisition circuit according to the total voltage value; the total voltage values corresponding to the collected different state combinations of the ports are different.
2. The port state management circuit of claim 1,
the number of the signal acquisition circuits is one or more; when the signal acquisition circuit is a plurality of, more than one signal acquisition circuit is connected with the same control pin.
3. The port state management circuit of claim 1 or 2,
each signal acquisition circuit comprises a gating control circuit and two paths of acquisition sub-circuits;
the two acquisition sub-circuits are respectively connected with different ports to be detected;
the gating control circuit is used for gating one of the two acquisition sub-circuits according to the received control signal sent by the control pin.
4. The port state management circuit of claim 3, wherein the signal acquisition circuit further comprises a pull-up voltage;
the first acquisition sub-circuit of the two acquisition sub-circuits comprises a first triode, and the second acquisition sub-circuit of the two acquisition sub-circuits comprises a second triode;
the collector electrodes of the first triode and the second triode are connected with the pull-up voltage, and the base electrodes of the first triode and the second triode are respectively connected with the gating control circuit;
and all ports connected with the first path of acquisition sub-circuit are connected in parallel to the emitting electrode of the first triode, and all ports connected with the second path of acquisition sub-circuit are connected in parallel to the emitting electrode of the second triode.
5. The port state management circuit of claim 4, wherein the gating control circuit comprises: the signal access circuit and the third triode;
the input end of the signal access circuit is connected with the control pin, and the output end of the signal access circuit is connected with the base electrode of the second triode and the base electrode of the third triode;
a collector of the third triode is connected with the pull-up voltage and is connected with a base of the first triode, and an emitter of the third triode is grounded; the first triode, the second triode and the third triode are NPN type triodes.
6. The port state management circuit of claim 4,
each port connected with the first path of acquisition sub-circuit is connected in parallel to an emitting electrode of the first triode through resistors with different resistance values;
and all ports connected with the second path of acquisition sub-circuit are connected in parallel to an emitting electrode of the second triode through resistors with different resistance values.
7. A port state management method applied to the port state management circuit according to any one of claims 1 to 6, comprising:
when any analog sampling pin receives a voltage value fed back by the signal acquisition circuit, determining a port set corresponding to the analog sampling pin according to a preset corresponding relation between the analog sampling pin and the port set;
matching the voltage value with each standard voltage value corresponding to the pre-stored port set; different standard voltage values correspond to different state combinations of each port in the port set;
and determining the state of each port in the port set according to the matched standard voltage value.
8. The port state management method of claim 7, wherein the method further comprises:
and sequentially controlling the control pins to send control signals to the signal acquisition circuits according to a preset period.
9. A port state management device applied to the port state management circuit according to any one of claims 1 to 6, comprising: the device comprises a determining module, a matching module and a processing module;
the determining module is used for determining a port set corresponding to an analog sampling pin according to a preset corresponding relation between the analog sampling pin and the port set when any analog sampling pin receives a voltage value fed back by the signal acquisition circuit;
the matching module is used for matching the voltage value with each standard voltage value corresponding to the pre-stored port set; different standard voltage values correspond to different state combinations of each port in the port set;
and the processing module is used for determining the state of each port in the port set according to the matched standard voltage value.
10. A readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the port state management method according to claim 7 or 8.
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