CN220935161U - Chip head address judging circuit, chip and cascade chip addressing control circuit - Google Patents

Abstract

The utility model relates to a chip head address judging circuit, a chip and a cascade chip addressing control circuit, and relates to the field of chip addressing circuits. The chip head address judging circuit comprises an N-type field effect transistor Q1 and a P-type field effect transistor Q2 which are connected with each other by drain electrodes, and an N-type field effect transistor Q3 and a P-type field effect transistor Q4 which are connected with each other by source electrodes; the source electrode of the N-type field effect tube Q1 is grounded, the grid electrode of the P-type field effect tube Q2 is connected with the source electrodes of the N-type field effect tube Q3 and the P-type field effect tube Q4, the source electrode of the P-type field effect tube Q2 is connected with the power supply VDD, the drain electrode of the N-type field effect tube Q3 is grounded, the drain electrode of the P-type field effect tube Q4 is connected with the power supply VDD, and the grid electrode of the P-type field effect tube Q4 is connected with the drain electrodes of the N-type field effect tube Q1 and the P-type field effect tube Q2. When the front-stage chip address input port and the chip signal port of the chip head address judging circuit are at low level, the chip address input port generates high level based on the gate charge accumulation effect, so that when the chip is abnormal, the subsequent chip continues addressing.

Description

Chip head address judging circuit, chip and cascade chip addressing control circuit

Technical Field

The utility model relates to the field of chip addressing circuits, in particular to a chip head address judging circuit, a chip and a cascade chip addressing control circuit.

Background

The larger the scale of the driving object related to the circuit, the more driving chips are required for the driving object, and in order to control the plurality of driving chips, the plurality of driving chips need to be automatically addressed. Such as: in a traditional LED landscape display system, display module chips are connected in series, a controller performs data communication with the display module chips according to addresses of the display module chips connected in series, and the number of the display module chips is increased in proportion to the scale of a landscape lamp. In order to automatically address a plurality of chips, it is necessary to determine the first chip address (i.e., the chip first address) of the serial chipset to quickly detect the first chip address to quickly address the plurality of chips of the serial chipset. Existing light control chips typically use address encoders or switch settings to determine the head address. The following are several common methods: address encoder: the light control chip typically has an address input, and the address is encoded as a unique binary code by connecting an address encoder to the input pins. The address encoder maps different addresses to different output signals, and the head address can be judged by reading the output signals. DIP switch/dial switch: some light control chips have DIP switches or dial switches on the chip for manually setting the head address. The binary code can be manually set to the desired home address by toggling the switch. Data manual or programming tool: some light control chips may provide a data manual or programming tool by which the head address information of the chip may be obtained or set by reading the relevant documents or using a specific programming interface. When the first-stage chip or the previous-stage chip is abnormal and cannot be normally used as the first-stage or the previous-stage chip, the subsequent chips cannot be used because address coding cannot be performed.

Disclosure of utility model

In order to solve the above technical problems or at least partially solve the above technical problems, the present utility model provides a chip head address determination circuit, a chip and a cascade chip addressing control circuit.

In a first aspect, the present utility model provides a chip head address determination circuit, applied to a cascaded chip, comprising: the N-type field effect transistor Q1 and the P-type field effect transistor Q2 with mutually connected drain electrodes, the N-type field effect transistor Q3 and the P-type field effect transistor Q4 with mutually connected source electrodes, wherein the grid electrode of the N-type field effect transistor Q1 is used as a front-stage chip address input port, the source electrode of the N-type field effect transistor Q1 is grounded, the grid electrode of the P-type field effect transistor Q2 is connected with the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4, the source electrode of the P-type field effect transistor Q2 is connected with a power supply VDD, the grid electrode of the N-type field effect transistor Q3 is used as a chip signal port, the drain electrode of the N-type field effect transistor Q3 is grounded, the drain electrode of the P-type field effect transistor Q4 is connected with the drain electrodes of the N-type field effect transistor Q1 and the P-type field effect transistor Q2, and the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4 are used as front-stage chip address receiving ports.

Further, the chip signal port is kept at a low level before the first high level appears in the preceding-stage chip address input port, and the chip signal port is in an opposite state to the preceding-stage chip address input port after the first high level appears in the preceding-stage chip address input port.

Still further, the chip signal port is electrically connected with the trigger switch, the trigger switch is electrically connected with the inverter, the inverter is electrically connected with the pre-stage chip address input port, the trigger end of the trigger switch is electrically connected with the pre-stage chip address input port, when the pre-stage chip address input port has a first high level, the trigger switch is started, the chip signal port is set to be in an opposite state of the pre-stage chip address input port, and before the trigger switch is started, the chip signal port inputs a low level.

Further, the trigger switch is a selection switch, and the trigger switch is connected with the inverter and the grounding signal.

Still further, when the front-end chip address input port and the chip signal port are low, the chip address input port generates a high level based on the gate charge accumulation effect.

In a second aspect, the present utility model provides a chip, to which the chip head address determination circuit is applied, the chip including: the system comprises a head address determining module, an address receiving module, an address creating module and an address outputting module; the first address determining module is electrically connected with a front-stage chip address receiving port of the chip first address judging circuit, determines whether the chip is selected as a chip corresponding to the first address according to the state of the front-stage chip address receiving port, and is electrically connected with a front-stage chip address input port of the chip first address judging circuit and used for acquiring a chip address or a first address judging signal of the front-stage chip;

The address creation module adds 1 to create own chip address on the basis of the chip address of the front-stage chip;

the address output module outputs an address to the back-stage chip through the chip address output port.

Further, the chip comprises a timing module, and the timing module controls the address output module to output the address to the back-stage chip after delaying for a set time.

Still further, the address creation module randomly generates an address when the chip address is selected as the first address.

In a third aspect, the present utility model provides a cascaded chip addressing control circuit, applied to a chip configuring the chip head address determination circuit, the chip comprising: the system comprises a head address determining module, an address receiving module, an address creating module and an address output module, wherein the head address determining module is electrically connected with a front-stage chip address receiving port of a chip head address judging circuit, and is used for determining whether a chip is selected as a chip corresponding to a head address according to the state of the front-stage chip address receiving port, and the address receiving module is electrically connected with a front-stage chip address input port of the chip head address judging circuit and is used for acquiring a chip address or a head address judging signal of the front-stage chip; the address creation module adds 1 to create own chip address on the basis of the chip address of the front-stage chip; the address output module outputs an address to a back-stage chip through a chip address output port; characterized by comprising the following steps: the pull-up resistor RA is electrically connected with the power supply VDD, and the pull-up resistor RA is electrically connected with a front-stage chip address input port of the chip head address judging circuit;

The chip address output port of the chip is coupled with the front chip address input port of the rear chip through a resistor RB, and a pull-up resistor RA is arranged between the resistor RB and the front chip address input port of the rear chip and is electrically connected with a power supply VDD.

Further, the power-on control circuit controls the power-on time of the power supply VDD for the cascade chip.

Compared with the prior art, the technical scheme provided by the embodiment of the utility model has the following advantages:

The N-type field effect transistor Q1 and the P-type field effect transistor Q2 with mutually connected drain electrodes, the N-type field effect transistor Q3 and the P-type field effect transistor Q4 with mutually connected source electrodes, wherein the grid electrode of the N-type field effect transistor Q1 is used as a front-stage chip address input port, the source electrode of the N-type field effect transistor Q1 is grounded, the grid electrode of the P-type field effect transistor Q2 is connected with the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4, the source electrode of the P-type field effect transistor Q2 is connected with a power supply VDD, the grid electrode of the N-type field effect transistor Q3 is used as a chip signal port, the drain electrode of the N-type field effect transistor Q3 is grounded, the drain electrode of the P-type field effect transistor Q4 is connected with the drain electrodes of the N-type field effect transistor Q1 and the P-type field effect transistor Q2, and the source electrodes of the N-type field effect transistor Q4 are used as front-stage chip address receiving ports. After the first high level appears in the front-end chip address input port, the chip signal port is in the opposite state of the front-end chip address input port, so that the front-end chip address receiving port can receive the front-end chip address. When the front-end chip address input port and the chip signal port are at low level, the chip address input port generates high level based on the gate charge accumulation effect so as to support that when the front-end chip is short-circuited and the chip address input port of the next chip is short-circuited, the chip is high level based on the gate charge accumulation effect, the next chip is selected as the first address chip, and address coding is continued.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model.

In order to more clearly illustrate the embodiments of the utility model or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic diagram of a chip first address determination circuit according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another first chip address determination circuit according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a chip according to an embodiment of the present utility model;

fig. 4 is a schematic diagram of a cascaded chip addressing control circuit according to an embodiment of the present utility model.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Example 1

Referring to fig. 1, an embodiment of the present utility model provides a chip head address determining circuit, including: the N-type field effect transistor Q1 and the P-type field effect transistor Q2 with mutually connected drain electrodes, the N-type field effect transistor Q3 and the P-type field effect transistor Q4 with mutually connected source electrodes, wherein the grid electrode of the N-type field effect transistor Q1 is used as a front-stage chip address input port, the source electrode of the N-type field effect transistor Q1 is grounded, the grid electrode of the P-type field effect transistor Q2 is connected with the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4, the source electrode of the P-type field effect transistor Q2 is connected with a power supply VDD, the grid electrode of the N-type field effect transistor Q3 is used as a chip signal port, the drain electrode of the N-type field effect transistor Q3 is grounded, the drain electrode of the P-type field effect transistor Q4 is connected with the drain electrodes of the N-type field effect transistor Q1 and the P-type field effect transistor Q2, and the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4 are used as front-stage chip address receiving ports.

In order to ensure that the pre-chip address receiving port receives the input pre-chip address, the chip signal port is in the opposite state of the pre-chip address input port after the first high level appears in the pre-chip address input port. When the input of the address receiving port of the front-stage chip is 1 and the input of the signal port of the chip is 0, the address receiving port of the front-stage chip is 1; when the input of the address receiving port of the front-stage chip is 0 and the input of the signal port of the chip is 1, the address receiving port of the front-stage chip is 0. The chip signal port remains low until the first high level appears at the pre-chip address input port.

In a possible implementation manner, referring to fig. 2, the chip signal port is electrically connected to a trigger switch, the trigger switch is electrically connected to an inverter, the inverter is electrically connected to the chip address input port, the trigger end of the trigger switch is electrically connected to the chip address input port, when the first high level occurs in the chip address input port, the trigger switch is started, the chip signal port is set to be in an opposite state to the chip address input port, and before the trigger switch is started, the chip signal port inputs the low level. The trigger switch is a selection switch and is connected with the inverter and the grounding signal.

When the pre-chip address input port and the chip signal port are low, the chip address input port generates a high level based on the gate charge accumulation effect. During rapid power-up, the gate-source junction of the P-type field effect transistor may be reversed biased, resulting in occurrence of gate-source leakage current. This is because the instant of fast power-up, the gate voltage is lower, the source voltage is higher, and a larger potential difference is generated, so that the gate-source junction is reversed biased, and the gate-source leakage current is increased. However, for the N-type field effect transistor, the problem of gate-source leakage can not exist during quick power-up. The power supply VDD is rapidly powered up, and the initial charge which is not released on the gate oxide layer between the gate and the source of the P-type field effect transistor causes a short leakage current, i.e., a gate charge accumulation effect, so that the voltage value of the address receiving port of the front-end chip can exceed the identification flip level value, thereby being identified as a high level, and enabling the chip to be determined as the first chip.

Example 2

Referring to fig. 3, an embodiment of the present utility model provides a chip, and the chip includes: the system comprises a head address determining module, an address receiving module, an address creating module and an address outputting module; the first address determining module is electrically connected with a front-stage chip address receiving port of the chip first address judging circuit and determines whether the chip is selected as the chip corresponding to the first address according to the state of the front-stage chip address receiving port; the address receiving module is electrically connected with a chip address input port of the chip head address judging circuit and is used for acquiring a chip address or a head address judging signal of a front-stage chip; the address creation module adds 1 to create own chip address on the basis of the chip address of the front-stage chip; the address creation module randomly generates an address when the chip address is selected as the first address. The address output module outputs an address to the back-stage chip through the chip address output port.

In the specific implementation process, the chip comprises a timing module, and the timing module controls the address output module to output an address to a post-stage chip after delaying for a set time.

Example 3

Referring to fig. 4, an embodiment of the present utility model provides a cascaded chip addressing control circuit, which is applied to a chip configured with the chip first address determination circuit, where the chip includes: the system comprises a head address determining module, an address receiving module, an address creating module and an address output module, wherein the head address determining module is electrically connected with a front-stage chip address receiving port of a chip head address judging circuit, determines whether a chip is selected as a chip corresponding to a head address according to the state of the front-stage chip address receiving port, and is electrically connected with a front-stage chip address input port of the chip head address judging circuit and used for acquiring a chip address or a head address judging signal of the front-stage chip; the address creation module adds 1 to create own chip address on the basis of the chip address of the front-stage chip; the address output module outputs an address to a back-stage chip through a chip address output port; characterized by comprising the following steps: the pull-up resistor RA is electrically connected with the power supply VDD, and the pull-up resistor RA is electrically connected with a front-stage chip address input port of the chip head address judging circuit; the chip address output port of the chip is coupled with the front chip address input port of the rear chip through a resistor RB, and a pull-up resistor RA is arranged between the resistor RB and the front chip address input port of the rear chip and is electrically connected with a power supply VDD. The power-on control circuit controls the power-on time of the power supply VDD for the cascade chip.

The address input port of the front chip is connected with the power supply VDD through the pull-up resistor RA. The power supply VDD is used for powering on the head chip, the address input port of the front chip of the head chip is in a high level, and the chip signal port is in an opposite state to the address input port of the front chip after the first high level appears on the address input port of the front chip. When the input of the address receiving port of the front-stage chip is 1 and the input of the signal port of the chip is 0, the address receiving port of the front-stage chip is 1. The first address determining module determines that the first chip is selected according to the first chip address receiving port 1, the address creating module creates a chip address and transmits the chip address to the first chip address input port of the second chip through the address output module. And the chip addressing is realized by sequential transmission. If any preceding chip is abnormal and causes a short circuit of the chip address output end, when the preceding chip address input port and the chip signal port of the next chip of the preceding chip are at low level, the chip address input port generates high level based on the gate charge accumulation effect, so that the next chip is selected as the first chip, and the addressing process is performed.

In the embodiments provided in the present utility model, it should be understood that the disclosed structure may be implemented in other manners. For example, the structural embodiments described above are merely illustrative, and for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via interfaces, structures or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present utility model may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The foregoing is only a specific embodiment of the utility model to enable those skilled in the art to understand or practice the utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A chip head address determination circuit applied to a cascade chip, comprising: the N-type field effect transistor Q1 and the P-type field effect transistor Q2 with mutually connected drain electrodes, the N-type field effect transistor Q3 and the P-type field effect transistor Q4 with mutually connected source electrodes, wherein the grid electrode of the N-type field effect transistor Q1 is used as a front-stage chip address input port, the source electrode of the N-type field effect transistor Q1 is grounded, the grid electrode of the P-type field effect transistor Q2 is connected with the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4, the source electrode of the P-type field effect transistor Q2 is connected with a power supply VDD, the grid electrode of the N-type field effect transistor Q3 is used as a chip signal port, the drain electrode of the N-type field effect transistor Q3 is grounded, the drain electrode of the P-type field effect transistor Q4 is connected with the drain electrodes of the N-type field effect transistor Q1 and the P-type field effect transistor Q2, and the source electrodes of the N-type field effect transistor Q3 and the P-type field effect transistor Q4 are used as front-stage chip address receiving ports.

2. The chip head address determination circuit of claim 1 wherein the chip signal port remains low until a first high level occurs at the front-end chip address input port, and wherein the chip signal port is in an inverse state of the front-end chip address input port after the first high level occurs at the front-end chip address input port.

3. The chip head address determination circuit of claim 2 wherein the chip signal port is electrically connected to a trigger switch, the trigger switch is electrically connected to an inverter, the inverter is electrically connected to a preceding chip address input port, the trigger terminal of the trigger switch is electrically connected to a preceding chip address input port, the trigger switch is activated when a first high level occurs in the preceding chip address input port, the chip signal port is set to an opposite state of the preceding chip address input port, and the chip signal port inputs a low level before the trigger switch is activated.

4. The chip head address determination circuit of claim 3 wherein the trigger switch is a select switch, the trigger switch connecting the inverter and the ground signal.

5. The chip head address determination circuit according to claim 1, wherein when the front-end chip address input port and the chip signal port are at low levels, the chip address input port generates a high level based on a gate charge accumulation effect.

6. A chip employing the chip head address determination circuit of any one of claims 1-5, the chip comprising: the system comprises a head address determining module, an address receiving module, an address creating module and an address outputting module; the first address determining module is electrically connected with a front-stage chip address receiving port of the chip first address judging circuit, determines whether the chip is selected as a chip corresponding to the first address according to the state of the front-stage chip address receiving port, and is electrically connected with a front-stage chip address input port of the chip first address judging circuit and used for acquiring a chip address or a first address judging signal of the front-stage chip;

The address creation module adds 1 to create own chip address on the basis of the chip address of the front-stage chip;

the address output module outputs an address to the back-stage chip through the chip address output port.

7. The chip of claim 6, wherein the chip includes a timing module that controls the address output module to output an address to a subsequent chip after a delay set time.

8. The chip of claim 6, wherein the address creation module randomly generates an address when a chip address is selected as a head address.

9. A cascaded chip addressing control circuit for use in a chip for configuring the chip head address determination circuit of any one of claims 1-5, said chip comprising: the system comprises a head address determining module, an address receiving module, an address creating module and an address output module, wherein the head address determining module is electrically connected with a front-stage chip address receiving port of a chip head address judging circuit, determines whether a chip is selected as a chip corresponding to a head address according to the state of the front-stage chip address receiving port, and is electrically connected with a front-stage chip address input port of the chip head address judging circuit and used for acquiring a chip address or a head address judging signal of the front-stage chip; the address creation module adds 1 to create own chip address on the basis of the chip address of the front-stage chip; the address output module outputs an address to a back-stage chip through a chip address output port; characterized by comprising the following steps: the pull-up resistor RA is electrically connected with the power supply VDD, and the pull-up resistor RA is electrically connected with a front-stage chip address input port of the chip head address judging circuit;

The chip address output port of the chip is coupled with the front chip address input port of the rear chip through a resistor RB, and a pull-up resistor RA is arranged between the resistor RB and the front chip address input port of the rear chip and is electrically connected with a power supply VDD.

10. The cascaded chip addressing control circuit of claim 9, wherein the power-on control circuit controls a power-on time of the power supply VDD for the cascaded chip.