CN111769095B - 基于高功能密度硅通孔结构的三维电容电感及制备方法 - Google Patents
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Abstract
本发明属于半导体器件技术领域,具体为一种基于高功能密度硅通孔结构的三维电容电感及制备方法。本发明三维电容电感包括:衬底,形成有硅通孔;三维电容,形成在所述硅通孔的侧壁上,依次包括第一金属层、第二绝缘层和第二金属层;三维电感,由所述硅通孔的中心填充金属和平面厚金属再布线构成;其中,所述硅通孔的侧壁与所述三维电容之间设有第一绝缘层,所述三维电容与所述三维电感之间设有第三绝缘层。本发明能够有效增加集成***中电容和电感的值,同时能够在三维集成中将电容电感集成在芯片附近,也能提高三维集成中硅通孔的功能密度,提高***集成中硅的利用率。与其他有机基板上的离散电容电感相比,集成度大大提高。
Description
技术领域
本发明属于半导体器件技术领域,具体涉及一种基于高功能密度硅通孔结构的三维电容电感及制备方法。
背景技术
随着集成电路的集成度不断提高,器件的特征尺寸已经接近物理极限。为进一步提高性能和集成度,研究人员开始不断提高硅的利用率,即功能密度。其中将芯片在三维方向上进行***集成就能极大地提高芯片的功能密度,但是随着***集成中芯片密度提高,信号耦合变得异常严重,所需要的去耦电容和电感也越来越多。仅仅依靠PCB板上的电容电感无法满足芯片集成中的要求,原因是电容电感数值太小、数量太少且距离较远。因此,具有较高电容电感值的硅上三维电容和三维电感的制备具有非常重要的意义。
目前,硅上三维电容或电感多是基于硅通孔(TSV)的单个三维电容,或基于厚金属再布线的三维电感,但TSV仅作为互连导线。这些结构TSV占用硅的面积较大,且功能单一。因此,TSV的功能密度非常较低,硅的利用率非常低。
发明内容
本发明的目的在于提供一种硅通孔功能密度大、硅利用率高的硅通孔结构的三维电容电感及其制备方法。
本发明提供的基于高功能密度硅通孔结构的三维电容电感,包括:
衬底,形成有硅通孔;
三维电容,形成在所述硅通孔的侧壁上,依次包括第一金属层、第二绝缘层和第二金属层;
三维电感,由所述硅通孔的中心填充金属和平面厚金属再布线构成;其中,所述硅通孔的侧壁与所述三维电容之间设有第一绝缘层,所述三维电容与所述三维电感之间设有第三绝缘层。
本发明的三维电容电感中,优选为,所述第二绝缘层为高K介质材料。
本发明的三维电容电感中,优选为,所述第一金属层、所述第二金属层为Cu、TiN或Cr。
本发明的三维电容电感中,优选为,所述衬底为高阻硅或玻璃。
本发明的三维电容电感中,优选为,所述第一绝缘层、所述第三绝缘层为氧化硅或氮化硅。
本发明还公开上述基于高功能密度硅通孔结构的三维电容电感制备方法,包括以下步骤:
在衬底上刻蚀形成盲孔;
在所述盲孔中及衬底表面形成第一绝缘层;
在所述第一绝缘层上形成三维电容的各层,包括依次沉积第一金属层、第二绝缘层和第二金属层,并光刻及刻蚀去除多余的第二绝缘层和第二金属层,使部分第一金属层表面露出,然后光刻刻蚀去除多余的第一金属层,使部分第一绝缘层表面露出,形成焊盘下金属层;
形成第三绝缘层,使其覆盖所述第二金属层、所述第一金属层和所述第一绝缘层;
电镀金属,并化学机械抛光和干法刻蚀去除多余金属,仅保留所述盲孔内的中心填充金属,作为三维电感的一部分;
在所述第一金属层和所述第二金属层上的第三层绝缘层进行光刻及刻蚀,从而对所述第一金属层和所述第二金属层分别进行开窗,并通过电镀及刻蚀制作测试或连接焊盘;
在所述盲孔的中心填充金属表面溅射种子层、光刻、电镀及刻蚀制作三维电感的测试或连接焊盘;
临时键合保护衬底正面图形,对衬底背部进行机械研磨、抛光和干法刻蚀露出背部硅通孔,并干法刻蚀去除硅通孔底部的部分所述第一绝缘层、所述第一金属层、所述第二绝缘层和所述第二金属层,直至露出中心填充金属;
进行背部绝缘并光刻刻蚀开窗,再沉积厚金属及刻蚀形成互连,形成三维电感的平面厚金属再布线部分;
去除临时键合,进行封装。
本发明制备方法中,优选为,所述第二绝缘层为高K介质材料。
本发明制备方法中,优选为,所述第一金属层、所述第二金属层为Cu、TiN或Cr。
本发明制备方法中,优选为,所述衬底为高阻硅或玻璃。
本发明制备方法中,优选为,所述中心填充金属为Cu、W。
发明能够有效增加集成***中电容和电感的值,同时能够在三维集成中将电容电感集成在芯片附近,也能提高三维集成中硅通孔的功能密度,提高***集成中硅的利用率。与其他有机基板上的离散电容电感相比,集成度大大提高。
附图说明
图1是本发明的基于高功能密度硅通孔结构的三维电容电感制备方法的流程图。
图2~14示出了基于高功能密度硅通孔结构的三维电容电感制备方法各步骤的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
在本发明的描述中,需要说明的是,术语“上”、“下”、“垂直”“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性。
此外,在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。除非在下文中特别指出,器件中的各个部分可以由本领域的技术人员公知的材料构成,或者可以采用将来开发的具有类似功能的材料。
以下结合附图1~14,以在高阻硅衬底上制备三维电容电感的方法为实施例,对本发明的技术方案做进一步的说明。图1是基于高功能密度硅通孔结构的三维电容电感制备方法的流程图,图2~14示出了基于高功能密度硅通孔结构的三维电容电感制备方法各步骤的结构示意图。
步骤S1,在衬底上刻蚀形成盲孔。具体而言,选用高阻硅作为衬底200,在其上采用标准光学光刻工艺,曝光出图形,作为光刻原始对准图形。薄胶光刻制作出硅通孔图形,用深硅刻蚀方法刻蚀出厚度为200微米、直径为50微米的盲孔201,所得结构如图2所示。
步骤S2,在上述结构上,采用热氧化的方法形成二氧化硅作为第一绝缘层202,所得结构如图3所示。二氧化硅的厚度优选为500nm,较厚的绝缘层能够有效降低衬底带来的电容和电感。然后,采用化学气相沉积(PECVD)方法沉积200nm的氮化硅,用以消除二氧化硅的应力,当然也可以采用其他消除应力的方法。
步骤S3,如图4~5所示,在第一绝缘层上形成三维电容的各层,包括依次沉积第一金属层203、第二绝缘层204和第二金属层205,并光刻及刻蚀去除多余的第二绝缘层204和第二金属层205,使部分第一金属层203表面露出,去除光刻胶。然后光刻刻蚀去除多余的第一金属层203,使部分第一绝缘层202表面露出,形成焊盘下金属层,去除光刻胶。第一金属层、第二金属层优选为Cu、TiN、Cr等金属。第二绝缘层优选为HfO2等高K介质材料。第一金属层、第二金属层、第二绝缘层可以采用原子层沉积(ALD)、溅射等方法制备。
步骤S4,形成第三绝缘层206,使其覆盖第二金属层205、第一金属层203和第一绝缘层202,所得结构如图6所示。
步骤S5,沉积种子层并电镀金属207,如图7所示。然后化学机械抛光去除大部分金属Cu,之后退火去除Cu和二氧化硅之间的应力,再进行干法刻蚀去除残余的Cu和孔内凸出的Cu,仅保留盲孔内的中心填充金属207,作为三维电感的一部分,所得结构如图8所示。
步骤S6,在第一金属层203和第二金属层205上的第三层绝缘层206进行光刻及刻蚀,从而对第一金属层203和第二金属层205分别进行开窗,并通过电镀及刻蚀制作测试或连接焊盘208,209,所得结构如图9所示。
步骤S7,在盲孔的中心填充金属207表面溅射种子层、光刻、电镀及刻蚀制作三维电感的测试或连接焊盘210。
步骤S8,将透明玻璃212与衬底200正面通过临时键合胶211进行临时键合,将正面图形保护起来,所得结构如图10所示。对衬底200背部进行机械研磨、抛光去除300微米厚的硅(硅衬底的总厚度为525微米),在距离盲孔底部25微米处停止,所的结构如图11所示。然后,干法刻蚀露出背部硅通孔,并干法刻蚀去除硅通孔底部的部分第一绝缘层202、第一金属层203、第二绝缘层204和第二金属层205,直至露出中心填充金属207,所得结构如图12所示。
步骤S9,进行背部绝缘,并光刻刻蚀开窗,再沉积厚金属及刻蚀形成互连,形成三维电感的平面厚金属再布线部分213,所得结构如图13所示。
步骤S10,去除临时键合,进行封装,所得结构如图14所示。
如图14所示,本发明的基于高功能密度硅通孔结构的三维电容电感包括:衬底200,形成有硅通孔;三维电容,形成在硅通孔的侧壁上,依次包括第一金属层203、第二绝缘层204和第二金属层205。三维电感,由硅通孔的中心填充金属207和平面厚金属再布线213构成;其中,硅通孔的侧壁与三维电容之间设有第一绝缘层202,三维电容与三维电感之间设有第三绝缘层206。
优选地,第二绝缘层为高K介质材料,例如HfO2等。第一金属层、第二金属层为Cu、TiN、Cr等金属。衬底可选用高阻硅、玻璃等。第一绝缘层、第三绝缘层可以是氧化硅、氮化硅等。中心填充金属优选为Cu、W等。
本发明巧妙地在TSV侧壁形成金属-绝缘层-金属的三维电容,同时以TSV的中心填充金属作为三维电感一部分和平面厚金属再布线共同作为三维电感。不仅仅大大节省了硅表面的面积,有效增加集成***中电容和电感的值,而且可以在三维集成中将无源元件较近地集成在芯片有源元件附近。也能提高三维集成中TSV的功能密度,提高***集成中硅的利用率。与其他有机基板上的离散电容电感相比,集成度大大提高。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。
Claims (10)
1.一种基于高功能密度硅通孔结构的三维电容电感,其特征在于,金属-绝缘层-金属的三维电容形成在硅通孔侧壁,同时以硅通孔的中心填充金属作为三维电感一部分和平面厚金属再布线共同作为三维电感,提高了三维集成中硅通孔的功能密度,且增加了集成***中电容和电感的值,
包括:
衬底,形成有硅通孔;
三维电容,形成在所述硅通孔的侧壁上,依次包括第一金属层、第二绝缘层和第二金属层;
三维电感,由所述硅通孔的中心填充金属和平面厚金属再布线构成;
其中,所述硅通孔的侧壁与所述三维电容之间设有第一绝缘层,所述三维电容与所述三维电感之间设有第三绝缘层。
2.根据权利要求1所述的基于高功能密度硅通孔结构的三维电容电感,其特征在于,所述第二绝缘层为高K介质材料。
3.根据权利要求1所述的基于高功能密度硅通孔结构的三维电容电感,其特征在于,所述第一金属层、所述第二金属层为Cu、TiN或Cr。
4.根据权利要求1所述的基于高功能密度硅通孔结构的三维电容电感,其特征在于,所述衬底为高阻硅或玻璃。
5.根据权利要求1所述的基于高功能密度硅通孔结构的三维电容电感,其特征在于,所述第一绝缘层、所述第三绝缘层为氧化硅或氮化硅。
6.一种基于高功能密度硅通孔结构的三维电容电感制备方法,其特征在于,具体步骤为:
在衬底上刻蚀形成盲孔;
在所述盲孔中及衬底表面形成第一绝缘层;
在所述第一绝缘层上形成三维电容的各层,包括依次沉积第一金属层、第二绝缘层和第二金属层,并光刻及刻蚀去除多余的第二绝缘层和第二金属层,使部分第一金属层表面露出,然后光刻刻蚀去除多余的第一金属层,使部分第一绝缘层表面露出,形成焊盘下金属层;
形成第三绝缘层,使其覆盖所述第二金属层、所述第一金属层和所述第一绝缘层;
电镀金属,并化学机械抛光和干法刻蚀去除多余金属,仅保留所述盲孔内的中心填充金属,作为三维电感的一部分;
在所述第一金属层和所述第二金属层上的第三绝缘层进行光刻及刻蚀,从而对所述第一金属层和所述第二金属层分别进行开窗,并通过电镀及刻蚀制作测试或连接焊盘;
在所述盲孔的中心填充金属表面溅射种子层、光刻、电镀及刻蚀制作三维电感的测试或连接焊盘;
临时键合保护衬底正面图形,对衬底背部进行机械研磨、抛光和干法刻蚀露出背部硅通孔,并干法刻蚀去除硅通孔底部的部分所述第一绝缘层、所述第一金属层、所述第二绝缘层和所述第二金属层,直至露出中心填充金属;
进行背部绝缘并光刻刻蚀开窗,再沉积厚金属及刻蚀形成互连,形成三维电感的平面厚金属再布线部分;
去除临时键合,进行封装,
获得形成在硅通孔侧壁的金属-绝缘层-金属的三维电容,同时以硅通孔的中心填充金属作为三维电感一部分和平面厚金属再布线共同作为三维电感,提高了三维集成中硅通孔的功能密度,且增加了集成***中电容和电感的值。
7.根据权利要求6所述的基于高功能密度硅通孔结构的三维电容电感制备方法,其特征在于,所述第二绝缘层为高K介质材料。
8.根据权利要求6所述的基于高功能密度硅通孔结构的三维电容电感制备方法,其特征在于,所述第一金属层、所述第二金属层为Cu、TiN或Cr。
9.根据权利要求6所述的基于高功能密度硅通孔结构的三维电容电感制备方法,其特征在于,所述衬底为高阻硅或玻璃。
10.根据权利要求6所述的基于高功能密度硅通孔结构的三维电容电感制备方法,其特征在于,所述中心填充金属为Cu或W。
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