CN111739904B

CN111739904B - Preparation method of three-dimensional phase change memory and three-dimensional phase change memory

Info

Publication number: CN111739904B
Application number: CN202010814167.7A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-08-13
Filing date: 2020-08-13
Publication date: 2020-11-20
Anticipated expiration: 2040-08-13
Also published as: CN111739904A

Abstract

The embodiment of the invention discloses a preparation method of a three-dimensional phase change memory and the three-dimensional phase change memory, wherein the method comprises the following steps: forming a first address line material layer, and forming a first phase change memory stack layer on the first address line material layer; etching the first phase change memory stack layer and the first address line material layer into a first phase change structure body and a first layer of address lines respectively in a first direction; forming a second address line material layer on the first phase change structure body, and forming a second phase change memory stack layer on the second address line material layer; and etching the second phase change memory stack layer and the second address line material layer into a second phase change structure body and a second address line layer respectively in a second direction intersecting the first direction, and etching the first phase change structure body into a first phase change memory unit.

Description

Preparation method of three-dimensional phase change memory and three-dimensional phase change memory

Technical Field

The invention relates to the technical field of memories, in particular to a three-dimensional phase change memory and a preparation method thereof.

Background

Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.

The 3D memory includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, a Phase Change Memory (PCM) may utilize a difference between resistivities of an amorphous Phase and a crystalline Phase in a Phase Change material based on heating and quenching of the Phase Change material in an electrothermal manner. Phase change memory cells may be vertically stacked in 3D to form a 3D PCM; optimization of the structure and preparation process of 3D PCM is an important research direction in the art.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a method for manufacturing a three-dimensional phase change memory and a three-dimensional phase change memory, so as to solve at least one problem in the background art.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

the embodiment of the invention provides a preparation method of a three-dimensional phase change memory, which comprises the following steps:

forming a first address line material layer, and forming a first phase change memory stack layer on the first address line material layer;

etching the first phase change memory stack layer and the first address line material layer in a first direction into a plurality of first phase change structure bodies and first address lines extending along the first direction respectively; wherein the first layer of address lines are first signal address lines;

forming a second address line material layer on the etched first phase change structure body, and forming a second phase change memory stack layer on the second address line material layer;

etching the second phase change memory stack layer and the second address line material layer into a plurality of second phase change structure bodies and second address lines extending along a second direction in the second direction which is intersected with the first direction, and etching the first phase change structure bodies into a plurality of columnar first phase change memory units which are independent of each other and vertical to the surface of the substrate; wherein the second layer address line is a second signal address line.

In the above scheme, the method further comprises: forming the second phase change structure into a second phase change memory cell;

the second layer of address lines are conductively coupled to the first phase change memory cell and the second phase change memory cell to form a second signal address line that is common to the first phase change memory cell and the second phase change memory cell.

In the above scheme, the method further comprises:

forming a third address line material layer on the etched second phase change structure body, and forming a third phase change storage stack layer on the third address line material layer;

etching the third phase change memory stack layer and the third address line material layer into a plurality of third phase change structures and third layer address lines extending along the first direction and etching the second phase change structures into a plurality of columnar second phase change memory units which are independent of each other and vertical to the surface of the substrate in the first direction respectively; wherein the third layer address line is a first signal address line.

In the above solution, the first signal address line is a bit line, and the first direction is a bit line lateral extension direction; the second signal address line is a word line, and the second direction is a word line transverse extension direction; alternatively, the first and second electrodes may be,

the first signal address line is a word line, and the first direction is a word line transverse extension direction; the second signal address line is a bit line, and the second direction is a bit line transverse extension direction.

In the above scheme, the first address line material layer is a bottom address line material layer;

forming a second address line material layer on the etched first phase change structure body, including: forming a second address line material layer having a thickness greater than a thickness of the first address line material layer.

In the above scheme, the method further comprises:

forming an n +1 address line material layer on the nth phase change structure;

etching the n +1 address line material layer and the n phase-change memory stack layer into an n +1 address line and a plurality of column-shaped n phase-change memory units which are independent from each other and vertical to the surface of the substrate respectively in the direction intersecting with the transverse extension direction of the n address line;

wherein n is a positive integer greater than or equal to 2.

In the above scheme, the n +1 th address line material layer is a top address line material layer;

the forming of the n +1 th address line material layer on the nth phase change structure body includes: forming an n +1 address line material layer having a thickness less than a thickness of the second address line material layer.

In the above scheme, the first phase change memory cell is formed to include a stacked phase change memory element, a selector, and a plurality of electrodes.

The embodiment of the invention provides a three-dimensional phase change memory, which comprises:

a substrate;

a first layer of address lines on the substrate, the first layer of address lines being first signal address lines extending in a first direction;

a first phase change memory cell on the first layer of address lines, the first phase change memory cell having a pillar structure perpendicular to the substrate surface;

a second layer of address lines on the first phase change memory cell, the second layer of address lines being second signal address lines; the second signal address line extends in a second direction intersecting the first direction;

a second phase change memory cell on the second layer of address lines, the second phase change memory cell having a pillar structure perpendicular to the substrate surface;

wherein sidewalls of the second phase change memory cells, the second layer address lines, and the first phase change memory cells extending in the second direction are aligned sequentially from top to bottom.

In the above scheme, the bottom end of the second phase change memory cell has a first size along the first direction, the top end of the first phase change memory cell has a second size along the first direction, and the first size is smaller than the second size.

In the foregoing scheme, the bottom end of the second phase change memory cell has a third size along the second direction, the top end of the first phase change memory cell has a fourth size along the second direction, and the third size is larger than the fourth size.

In the above scheme, the method further comprises:

a third layer of address lines on the second phase change memory unit, the third layer of address lines being first signal address lines extending along the first direction;

a third phase change memory cell on the third layer of address lines, the third phase change memory cell having a pillar structure perpendicular to the substrate surface;

the third phase change memory unit, the third layer of address lines and the side walls of the second phase change memory unit extending along the first direction are sequentially aligned from top to bottom; sidewalls of the third phase change memory cell and the second phase change memory cell extending in the second direction are not coplanar.

In the above solution, the second layer address line is a common address line of the first phase change memory cell and the second phase change memory cell; the three-dimensional phase change memory further includes: a third layer of address lines on the second phase change memory unit, the third layer of address lines being first signal address lines extending along the first direction;

the first phase change memory cell operates based on signals transmitted by the first layer address line and the second layer address line; the second phase change memory unit works based on signals transmitted by the third layer address line and the second layer address line.

In the above scheme, the first layer address line is a bottom layer address line; the second layer of address lines has a thickness greater than a thickness of the first layer of address lines.

In the above scheme, the method further comprises:

a top layer address line; the thickness of the top layer address line is less than the thickness of the second layer address line.

In the above scheme, the first phase change memory cell and the second phase change memory cell each include a stacked phase change memory element, a selector, and a plurality of electrodes, respectively.

The embodiment of the invention provides a preparation method of a three-dimensional phase change memory and the three-dimensional phase change memory, wherein the method comprises the following steps: forming a first address line material layer, and forming a first phase change memory stack layer on the first address line material layer; etching the first phase change memory stack layer and the first address line material layer in a first direction into a plurality of first phase change structure bodies and first address lines extending along the first direction respectively; wherein the first layer of address lines are first signal address lines; forming a second address line material layer on the etched first phase change structure body, and forming a second phase change memory stack layer on the second address line material layer; etching the second phase change memory stack layer and the second address line material layer into a plurality of second phase change structure bodies and second address lines extending along a second direction in the second direction which is intersected with the first direction, and etching the first phase change structure bodies into a plurality of columnar first phase change memory units which are independent of each other and vertical to the surface of the substrate; wherein the second layer address line is a second signal address line. Therefore, the second phase change structure body (to be formed into a second phase change memory unit in the subsequent process), the second layer address wire and the side wall of the first phase change memory unit extending along the second direction are formed in the same etching procedure, so that the number of mask layers is reduced, and the cost of the photoetching process is saved; and the formed second phase change memory cell and the first phase change memory cell can be self-aligned with the second layer of address line, so that the problem that the two memory cells are not aligned with the second layer of address line is avoided, and the working stability of the device is improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIGS. 1 a-1 b show perspective views of exemplary 3D XPoint memory during fabrication;

FIG. 2 is an electron micrograph of two adjacent layers of memory cells in an exemplary 3D XPoint memory during fabrication;

FIG. 3 is a schematic flow chart illustrating a method for fabricating a three-dimensional phase change memory according to an embodiment of the invention;

fig. 4a to 4h are perspective views illustrating a three-dimensional phase change memory according to an embodiment of the invention during a manufacturing process;

fig. 5a and 5b, fig. 6a and 6b, fig. 7a and 7b, fig. 8a and 8b, fig. 9a and 9b, and fig. 10a and 10b are detailed cross-sectional views of a three-dimensional phase change memory according to an embodiment of the present invention in a second direction and in a first direction, respectively, during different processes;

fig. 11 is an electron microscope image of two adjacent layers of memory cells in the three-dimensional phase change memory according to the embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used in the following description, the term "three-dimensional memory" refers to a semiconductor device having the following memory cells: the memory cells are arranged vertically on a laterally oriented substrate such that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.

Three-dimensional phase change memories include three-dimensional cross-point (3D XPoint) memories that store data based on a change in resistance of a bulk material property (e.g., in a high resistance state or a low resistance state), in combination with a stackable cross-point data access array to enable bit addressing. For example, FIG. 1b shows a perspective view of the structure of an exemplary 3D XPoint memory 100. According to some embodiments, 3D XPoint memory 100 has a transistorless crosspoint architecture that places memory cells at the intersections of vertical conductors; the vertical conductor here includes a Word Line (WL) and a Bit Line (BL) that perpendicularly intersect each other, and the WL and BL are generally formed of a line/space (L/S) of a 20nm/20nm uniform width formed after a patterning process. The 3D XPoint memory 100 includes a plurality of lower bit lines 111 parallel to each other in the same plane and a plurality of upper bit lines 121 parallel to each other in the same plane above the lower bit lines 111. The 3D XPoint memory 100 further includes a plurality of lower and upper word lines 112 and 122 parallel to each other in the same plane between the lower and

upper bit lines

111 and 121 in a vertical direction. As shown in fig. 1b, each lower bitline 111 and each upper bitline 121 extends laterally in a bitline direction in a top plan view (parallel to the wafer plane), and each lower wordline 112 and upper wordline 122 extends laterally in a wordline direction in a top plan view, each lower wordline 112 and upper wordline 122 being perpendicular to each lower bitline 111 and each upper bitline 121.

As shown in FIG. 1b, 3D XPoint memory 100 includes a plurality of lower memory cells 110 and a plurality of upper memory cells 120, each lower memory cell 110 disposed at an intersection of a lower bitline 111 and a corresponding lower wordline 112, and each upper memory cell 120 disposed at an intersection of an upper bitline 121 and a corresponding upper wordline 122. Each memory cell 110/120 includes at least a vertically stacked PCM element and a selector. Each memory cell 110/120 stores a single bit of data and can be written to or read from each memory cell 110/120 by varying the voltage applied to a corresponding selector (which replaces the need for a transistor). Each memory cell 110/120 can be individually accessed by applying currents through the top and bottom conductors (e.g., the respective lower or

upper word line

112 or 122 and lower or upper bit line 111 or 121) that are in contact with each memory cell 110/120. The memory cells 110/120 in the 3D XPoint memory 100 are arranged in a memory array.

The general fabrication process of 3D XPoint memory can be generally understood by combining FIG. 1a and FIG. 1 b. First, the lower memory cell 110 and the corresponding lower bit line 111 and lower word line 112 are formed. Specifically, a lower bit line material layer may be formed on a substrate (not shown), on which a lower phase change memory stack layer is formed; etching the lower phase change memory stack layer and the lower bit line material layer in the bit line direction to form the lower bit line material layer into a lower bit line 111 extending transversely in the bit line direction, wherein the lower phase change memory stack layer is formed into a lower phase change structure body extending in the bit line direction and vertical to the surface of the substrate; forming a lower word line material layer on the lower phase change structure; the lower word line material layer and the lower phase change structure are etched in the word line direction, so that the lower word line material layer is formed as a lower word line 112 extending laterally in the word line direction, and the lower phase change structure is etched again in the word line direction (twice etching: first etching in the bit line direction and then etching in the word line direction) to form a pillar-shaped lower memory cell 110. With further reference to FIG. 1b, an upper memory cell 120 and its corresponding upper word line 122 and upper bit line 121 are formed on the lower memory cell 110 based on similar steps. Here, the two etching directions are opposite to the order of forming the lower memory cell 110, i.e., etching is performed first in the word line direction and then in the bit line direction, so as to be engaged with the lower word line 112 of the lower memory cell 110.

In the 3D XPoint memory obtained through the above fabrication process, two layers of word lines, a lower word line 112 and an upper word line 122, formed through a two-step etching process, exist between the lower memory cell 110 and the upper memory cell 120, and the lower word line 112 and the upper word line 122 are overlapped together to form a common word line. However, bending and/or positional deviation of the finally formed word line shape may be caused due to photolithography alignment problems and problems of actual processes and stress, etc., resulting in the generation of a deviation problem between both the lower word line 112 and the upper word line 122. FIG. 2 shows an electron micrograph of two adjacent layers of memory cells; the circular dotted line frame in the figure guides the connection position of the upper word line layer and the lower word line layer, and the problem of deviation is obvious. This will result in increased contact resistance and will affect the stability of the device operation. In addition, the lower memory cell and the upper memory cell both need to define the pillar structure by two mask patterns in the BL and WL directions, and there are many photolithography steps, which results in an increase in process time and an increase in process cost.

Based on this, the embodiment of the invention provides a preparation method of a three-dimensional phase change memory; please refer to fig. 3. As shown, the method comprises the steps of:

step 301, forming a first address line material layer, and forming a first phase change memory stack layer on the first address line material layer;

step 302, etching the first phase change memory stack layer and the first address line material layer in a first direction into a plurality of first phase change structures and first address lines extending along the first direction respectively;

wherein the first layer of address lines are first signal address lines;

step 303, forming a second address line material layer on the etched first phase change structure, and forming a second phase change memory stack layer on the second address line material layer;

step 304, etching the second phase change memory stack layer and the second address line material layer into a plurality of second phase change structures and second address lines extending along a second direction in the second direction intersecting the first direction, and etching the first phase change structures into a plurality of first phase change memory cells which are independent of each other and are in a column shape perpendicular to the surface of the substrate;

wherein the second layer address line is a second signal address line.

In the method, the second phase change structure body (to be formed into the second phase change memory unit in the subsequent process), the second layer address wire and the side wall of the first phase change memory unit extending along the second direction are formed in the same etching procedure, so that the number of mask layers is reduced, and the cost of the photoetching process is saved; and the formed second phase change memory cell and the first phase change memory cell can be self-aligned with the second layer of address line, so that the problem that the two memory cells are not aligned with the second layer of address line is avoided, and the working stability of the device is improved.

Next, referring to the perspective structural views of the three-dimensional phase change memory in the manufacturing process in fig. 4a to 4h, the three-dimensional phase change memory and the manufacturing method thereof provided by the embodiment of the invention will be further described in detail.

The method begins at step 301 by forming a first address line material layer 411', forming a first phase change memory stack layer 410 ″ over the first address line material layer 411'.

In an actual process, a substrate may be provided first, and the substrate is located below a process-performing surface, so as to provide a supporting function for the process.

Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate is a silicon wafer.

The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction, ignoring the flatness of the top and bottom surfaces. Here, the third direction is also a stacking direction in which the respective layer structures are subsequently deposited on the substrate. Defining a first direction and a second direction which are intersected with each other on the top surface and the bottom surface of the substrate, namely the plane direction of the substrate; a planar direction of the substrate may be determined based on the first direction and the second direction. The first direction and the second direction are, for example, two directions perpendicular to each other. Further, the first direction, the second direction and the third direction are perpendicular to each other.

For clarity of illustrating details of some aspects, reference may be made herein to fig. 5a and 5b, wherein fig. 5a is a cross-sectional view in a second direction and fig. 5b is a cross-sectional view in a first direction. As shown, a substrate 400 is provided, a first address line material layer 411 'is formed on the substrate 400, and a first phase change memory stack layer 410 ″ is formed on the first address line material layer 411'.

It should be understood that other material layers may also be included between the substrate and the first address line material layer. For example, a dielectric layer is further included under the first address line material layer; the dielectric layer may be an oxide layer, and the material may be specifically silicon oxide.

In the perspective view of the structure shown in fig. 4a, the structural layer under the first address line material layer 411' is not particularly limited, and may be an oxide layer, a substrate or other material layers, and thus, no specific reference numeral is given here.

The first address line material layer is used for forming bit lines or word lines after being patterned. The material of the first address line material layer may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The materials of other address line material layers (such as the nth address line material layer, n is a positive integer greater than or equal to 2) involved in the subsequent process steps can be selected from the materials; thus, the material of each first signal address line and/or each second signal address line may be formed of at least one of the materials described above. In some embodiments, each of the first and second signal address lines comprises a metal, such as tungsten.

The first phase change memory stack layer may include a stacked PCM material layer, a selection device material layer, and a plurality of electrode material layers; specifically, referring to fig. 4a, for example, a first conductor material layer 401 ", a selection material layer 402", a second conductor material layer 403 ", a PCM material layer 404" and a third conductor material layer 405 "are sequentially stacked.

Here, each of the first, second, and third conductor material layers may include a conductive material including, but not limited to, W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the first, second, and third layers of conductor material includes carbon, such as amorphous carbon (a-C). The material of the select device material layer may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_yOr Si_xAs_yTe_zAnd the like. The material of the PCM material layer comprises a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material.

It should be understood that the structure, configuration, and materials of the first phase change memory stack layer are not limited to the example in fig. 4a, and may include any suitable structure, configuration, and materials.

The structure, configuration and material of other phase change memory stack layers (e.g., the nth phase change memory stack layer, where n is a positive integer greater than or equal to 2) involved in subsequent process steps may be the same as those of the first phase change memory stack layer; and will not be described in detail later. Thus, each phase change memory cell formed also has a structure, configuration, and material corresponding thereto.

The above layers are formed using one or more thin film deposition processes; specifically, the formation process of each layer structure includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Referring to fig. 4a, in an embodiment, step 301 may further include: forming a nitride (Nit) -based material layer 415 'on the first phase change memory stack layer 410'; the layer 415 ″ of nitride (Nit) -based material serves, for example, as a hard mask layer in a subsequent photolithography process.

It should be understood that some structures may be omitted from the drawings in order to emphasize certain features. For example, the nitride (Nit) -based material layer and the like may be omitted in a partial sectional view.

Next, please refer to fig. 4 b; executing step 302, etching the first phase change memory stack layer and the first address line material layer in a first direction into a plurality of first phase change structure bodies 410' extending along the first direction and a plurality of first address lines 411 respectively; the first layer address line 411 is a first signal address line.

In an actual process, the first phase change memory stack layer and the first address line material layer are etched in a first direction to form the first address line material layer as a first layer address line 411 extending along the first direction, and the first phase change memory stack layer is formed as a first phase change structure body 410' extending along the first direction and perpendicular to the surface of the substrate 400. In other words, the first layer address line 411 and the first phase change structure 410' are formed in the same etching process.

Specifically, a photoresist mask (not shown) may be formed on the first phase change memory stack layer, and the photoresist mask may be patterned by exposure and development. And etching the first phase change storage stack layer and the first address line material layer based on the photoresist mask or a hard mask patterned based on the photoresist mask.

And forming grooves in the first phase change storage stacking layer through etching, and separating the first phase change structure body through two adjacent grooves. With further reference to fig. 6a and 6b, since first phase change structure 410' and first layer address line 411 are formed in the same etching process, the resulting sidewalls of the first phase change memory cell and the first layer address line extending in the first direction are aligned from top to bottom in the final device. In addition, due to the etching process, the formed groove can have an inverted trapezoidal section structure with a large upper opening and a small lower opening; in this way, in the final fabricated device, the size of the resulting first phase change memory cell in the second direction increases from top to bottom. The size of the bottom end of the first phase change memory cell along the second direction is smaller than the width of the first layer address line.

Next, please refer to fig. 4 c; step 303 is performed to form a second address line material layer 422' on the etched first phase change structure 410', and a second phase change memory stack layer 420 ″ is formed on the second address line material layer 422 '.

The second address line material layer should have a greater thickness, considering that it may act as an etch stop layer for the etch back in subsequent steps. Here, further reference may be made to fig. 7a and 7b, which are a cross-sectional view of the three-dimensional phase change memory structure along the second direction and a cross-sectional view along the first direction after forming the second phase change memory stack layer 420 ″; as shown, the second address line material layer 422' may have a greater thickness. In one embodiment, the first address line material layer 411' is a bottom address line material layer (refer to the first address line layer 411 in the figure); the forming of the second address line material layer 422 'on the first phase change structure body 410' includes: a second address line material layer 422 'is formed to a thickness greater than the thickness of the first address line material layer 411'. The thickness of the second address line material layer 422 'is, for example, 1.7 times or more the thickness of the first address line material layer 411'. In a specific application, the thickness of the first address line material layer 411 '(i.e., the thickness of the first layer address line 411) is, for example, 37nm, and the thickness of the second address line material layer 422' (i.e., the thickness of the subsequently formed second layer address line 422) is, for example, greater than 64 nm.

In actual preparation, before performing the step 303, the method may further include: the trenches formed in two adjacent first phase change structure bodies 410' are filled with a filling material (as shown in fig. 4c and 7 a). The filler material may be a dielectric material, such as an oxide material, and may specifically be silicon oxide. The fill material is formed using one or more thin film deposition processes, such as ALD processes, into the trench; a planarization process, such as CMP and/or etching, may then follow such that the upper surface of the fill material is coplanar with the upper surface of the first phase change structure 410 'and the fill material exposes the upper surface of the first phase change structure 410'. Then, the second address line material layer 422 'and the second phase change memory stack layer 420 ″ are formed on the first phase change structure body 410' and the filler material.

The second address line material layer is used for forming word lines or bit lines after being patterned; the signal lines formed after the second address line material layer is patterned and the signal lines formed after the first address line material layer is patterned operate based on different signals (word line signals or bit line signals).

The specific layer structure in the second phase change memory stack layer may be the same as the first phase change memory stack layer.

Next, please refer to fig. 4 d; executing step 304, etching the second phase change memory stack layer and the second address line material layer in a second direction intersecting the first direction into a plurality of second phase change structures 420' and second address lines 422 extending along the second direction, and etching the first phase change structures into a plurality of pillar-shaped first phase change memory cells 410 independent from each other and perpendicular to the surface of the substrate; wherein the second layer address lines 422 are second signal address lines.

In an actual process, etching the second phase change memory stack layer, the second address line material layer and the first phase change structure body in a second direction, wherein the etching is performed from the second phase change memory stack layer to penetrate through the first phase change structure body; in this way, the first phase change structure body is formed into a columnar first phase change memory cell perpendicular to the surface of the substrate, the second address line material layer is formed into a second address line layer extending in the second direction, and the second phase change memory stack layer is formed into a second phase change structure body extending in the second direction and perpendicular to the surface of the substrate. The second phase change structure, the second layer address line and the first phase change memory unit are formed in the same etching process.

Specifically, a photoresist mask (not shown) may be formed on the second phase change memory stack layer, and the photoresist mask may be patterned by exposure and development. And etching the second phase change storage stack layer, the second address line material layer and the first phase change structural body based on the photoresist mask or the hard mask patterned based on the photoresist mask.

Although only one second phase change structure is schematically illustrated in fig. 4d, it should be understood that in actual production, a plurality (two or more) of discretely arranged second phase change structures may be formed. In order to illustrate the trenches formed by this etching process, fig. 8b shows the case of two second phase change structure bodies 420', the trenches extending downward from the upper surface of the second phase change memory stack layer, through the second address line material layer and the first phase change memory stack layer, until the first address line 411 is exposed.

As can be understood in conjunction with fig. 8a and 8b, since the second phase change structure body 420', the second layer of address lines 422 and the first phase change memory cell 410 are formed in the same etching process, the second phase change memory cell formed by etching the second phase change memory stack layer, the second layer of address lines and the sidewalls of the first phase change memory cell extending in the second direction are sequentially aligned from top to bottom in the final fabricated device.

In addition, due to the etching process, the sizes of the obtained second phase change memory unit, the second layer address line and the first phase change memory unit along the first direction are increased from top to bottom in the finally prepared device. Specifically, the bottom end of the second phase change memory cell has, for example, a first dimension along the first direction, and the top end of the first phase change memory cell has, for example, a second dimension along the first direction, then the first dimension is smaller than the second dimension. The size of the second phase change memory unit along the first direction is smaller than the width of the second layer address line; the first phase change memory cell has a dimension in the first direction that is greater than a width of the second layer of address lines.

Next, please refer to fig. 4e to 4 f; the method may further comprise: forming a third address line material layer 431' on the etched second phase change structure body 420', and forming a stacked third phase change memory stack layer 430 ″ on the third address line material layer 431 '; etching the third phase change memory stack layer 430 ″ and the third address line material layer 431 'in the first direction into a plurality of third phase change structure bodies 430' and a third layer address line 431 'extending along the first direction, respectively, and etching the second phase change structure body 420' into a plurality of second phase change memory cells 420 independent from each other and having a pillar shape perpendicular to a surface of the substrate; wherein the third layer address line 431 is the first signal address line.

It should be appreciated that in actual fabrication, prior to forming the third layer of address line material, the method may further include: filling the groove formed in the previous etching process by using a filling material; a planarization process, such as CMP and/or etching, may then follow such that an upper surface of the filler material is coplanar with an upper surface of the second phase change structure and the filler material exposes the upper surface of the second phase change structure. Then, the third address line material layer and the third phase change memory stack layer are formed on the second phase change structure body and the filler material.

The specific layer structure of the third phase change memory stack layer may be the same as that of the first phase change memory stack layer.

The etching process may specifically include: a photoresist mask (not shown) is formed over the third phase change memory stack layer and patterned by exposure and development. And etching the third phase change storage stack layer, the third address line material layer and the second phase change structure body based on the photoresist mask or the hard mask patterned based on the photoresist mask.

In an actual process, etching the third phase change memory stack layer, the third address line material layer and the second phase change structure body in the first direction, wherein the etching is performed from the third phase change memory stack layer to penetrate through the second phase change structure body; in this way, the second phase change structure body is formed as a columnar second phase change memory cell perpendicular to the surface of the substrate, the third address line material layer is formed as a third layer address line extending in the first direction, and the third phase change memory stack layer is formed as a third phase change structure body extending in the first direction and perpendicular to the surface of the substrate. The third phase change structure, the third layer address line and the second phase change memory unit are formed in the same etching process.

In the etching procedure, the second layer address line can be used as an etching stop layer; during the actual etching process, the upper surface of the second layer address line may be slightly lost.

Referring to fig. 4f, the third layer address line 431 and the first layer address line 411 are the same first signal address line, i.e. both are bit lines or both are word lines.

As can be understood from fig. 9a and 9b, since the third phase change structure body 430', the third layer address line 431, and the second phase change memory cell 420 are formed in the same etching process, in the final fabricated device, the third phase change memory cell formed by etching the third phase change memory stack layer, the third layer address line, and the second phase change memory cell are sequentially aligned from top to bottom with sidewalls extending in the first direction. Sidewalls of the second phase change memory cell and the first phase change memory cell extending in the first direction are not coplanar.

In addition, due to the etching process, the sizes of the obtained third phase change memory unit, the third layer address line and the second phase change memory unit in the second direction are increased from top to bottom in the finally prepared device. The bottom end of the second phase change memory cell is located at the deepest part of the etching process, so that a finally prepared device has the following structure: the bottom end of the second phase change memory cell has a third dimension along the second direction, the top end of the first phase change memory cell has a fourth dimension along the second direction, and the third dimension is greater than the fourth dimension. In addition, the bottom end of the third phase change memory cell has, for example, a fifth dimension in the second direction, and the top end of the second phase change memory cell has, for example, a sixth dimension in the second direction, then the fifth dimension is smaller than the sixth dimension.

It should be understood that the method provided by the embodiment of the present invention may further include: forming an n +1 address line material layer on the nth phase change structure; etching the n +1 address line material layer and the n phase-change memory stack layer into an n +1 address line and a plurality of column-shaped n phase-change memory units which are independent from each other and vertical to the surface of the substrate respectively in the direction intersecting with the transverse extension direction of the n address line; wherein n is a positive integer greater than or equal to 2.

In this manner, a three-dimensional phase change memory having any number of stacked phase change memory cells may be formed.

Wherein the n +1 address line material layer is a top address line material layer; the forming of the n +1 th address line material layer on the nth phase change structure body includes: forming an n +1 address line material layer having a thickness less than a thickness of the second address line material layer.

Here, the thickness of the top address line material layer (top address line) may be equal to the thickness of the bottom address line material layer (bottom address line); both having a thickness of, for example, 37 nm. In other embodiments, the thickness of the top layer address line material layer (top address line) may also be less than the thickness of the bottom layer address line material layer (bottom address line). The thickness of other address line material layers (other layer address lines) between the top layer address line material layer (top layer address line) and the bottom layer address line material layer (bottom layer address line) should be larger than the thickness of either the top layer address line material layer (top layer address line) or the bottom layer address line material layer (bottom layer address line); the thickness of the other address line material layer (other layer address lines) can be more than 1.7 times that of any one of the top layer address line material layer (top layer address lines) and the bottom layer address line material layer (bottom layer address lines); the thickness of the other address line material layer (other layer address line) is specifically, for example, greater than 64 nm.

Please specifically refer to fig. 4g to 4 h; next, a fourth address line material layer 442 'is formed on the etched third phase change structure body 430'; etching the fourth address line material layer 442 'and the third phase change structure body 430' in a second direction into a fourth address line 442 and a plurality of column-shaped third phase change memory cells 430 which are independent from each other and perpendicular to the surface of the substrate, respectively; wherein the fourth layer address line 442 is a second signal address line.

Here, the fourth address line material layer is a top address line material layer; the forming a fourth address line material layer on the third phase change structure body includes: forming a fourth address line material layer having a thickness less than the thickness of the second address line material layer.

It should be appreciated that in actual fabrication, prior to forming the fourth address line material layer, the method may further include: filling the groove formed in the previous etching process by using a filling material; a planarization process, such as CMP and/or etching, may then follow such that an upper surface of the filler material is coplanar with an upper surface of the third phase change structure and the filler material exposes the upper surface of the third phase change structure. Then, the fourth address line material layer is formed on the third phase change structure body and the filling material.

The etching process may specifically include: a photoresist mask (not shown) is first formed over the top address line material layer (e.g., the fourth address line material layer), and the photoresist mask is patterned by exposure and development. And etching the top address line material layer and the nth phase change storage stack layer (such as a third phase change storage stack layer) based on the photoresist mask or a hard mask patterned based on the photoresist mask.

And forming a groove extending along the second direction in the nth phase change memory stack layer (such as the third phase change memory stack layer) by etching.

As can be understood from fig. 10a and 10b, since the fourth layer of address lines 442 and the third phase change memory cells 430 are formed in the same etching process, the sidewalls of the resulting fourth layer of address lines 442 and third phase change memory cells 430 extending in the second direction are aligned from top to bottom in the final device. In addition, due to the etching process, in the final manufactured device, the width of the obtained fourth layer address line 442 is smaller than the width of the third phase change memory unit 430 which is immediately below the fourth layer address line along the first direction; the size of the third phase change memory cell 430 in the first direction increases from top to bottom.

Sidewalls of the third phase change memory cell 430 and the second phase change memory cell 420 extending in the second direction are not coplanar. The width of the bottom end of the third phase change memory cell 430 in the first direction is greater than the width of the top end of the second phase change memory cell 420 in the first direction.

It should be appreciated that in actual fabrication, after forming a top phase change memory cell (e.g., the third phase change memory cell) and a top address line (e.g., the fourth address line 442), the method may further include: filling the groove formed in the previous etching process by using a filling material; a planarization process such as CMP and/or etching may then follow such that an upper surface of the fill material is coplanar with an upper surface of a top-level phase change memory cell (e.g., the third phase change memory cell) and the fill material exposes the upper surface of the top-level phase change memory cell (e.g., the third phase change memory cell).

Here, the drawings only schematically show a preparation method of a three-layer phase change memory cell stack structure and a three-dimensional phase change memory structure prepared by the method; it should be understood that the present invention is not limited thereto, and the method for fabricating a three-dimensional phase change memory provided by the embodiment of the present invention may be applied to form a three-dimensional phase change memory having a two-layer stacked phase change memory cell structure without forming a stacked third phase change memory stack layer on the third address line material layer; in the case where the formation of the stacked third phase change memory stack layer on the third address line material layer is performed, a three-dimensional phase change memory having a more-layer stacked phase change memory cell structure may also be formed through the same steps. Furthermore, the first phase change memory cell and the second phase change memory cell (or including the third phase change memory cell) in the embodiment of the invention may be any two layers (or three layers) in a three-dimensional phase change memory having a multi-layer stacked phase change memory cell structure.

Regardless of which implementation forms the second phase change memory stack layer as a second phase change memory cell, the second layer address line conductively couples the first phase change memory cell and the second phase change memory cell to form a second signal address line that is common to the first phase change memory cell and the second phase change memory cell. The first phase change memory cell operates based on signals transmitted by the first layer address line and the second layer address line.

Similarly, the third layer of address lines is conductively coupled to the second phase change memory cells and the third phase change memory cells to form first signal address lines that are common to the second phase change memory cells and the third phase change memory cells. The second phase change memory unit works based on signals transmitted by the third layer address line and the second layer address line. The three-dimensional phase change memory further includes: a fourth layer of address lines on the third phase change memory unit, the fourth layer of address lines being second signal address lines extending along the second direction; the third phase change memory unit works based on signals transmitted by the third layer address wire and the fourth layer address wire.

In an embodiment of the present application, the first signal address line is a bit line, and the first direction is a bit line lateral extension direction; the second signal address line is a word line, and the second direction is a word line transverse extension direction; or, the first signal address line is a word line, and the first direction is a word line transverse extension direction; the second signal address line is a bit line, and the second direction is a bit line transverse extension direction.

An embodiment of the present invention further provides a three-dimensional phase change memory, including:

a substrate;

Here, sidewalls of the second phase change memory cell and the first phase change memory cell extending in the first direction are not coplanar.

It should be appreciated that embodiments of the present invention provide a three-dimensional phase change memory including a plurality of first signal address lines extending in a first direction and spaced apart from each other. The first phase change memory cell may be a first phase change memory cell located on each of the first signal address lines. Correspondingly, the three-dimensional phase change memory comprises a plurality of first phase change memory cells which are independent from each other and are in a column shape perpendicular to the surface of the substrate.

In one embodiment, the bottom end of the second phase change memory cell has a first dimension along the first direction, and the top end of the first phase change memory cell has a second dimension along the first direction, the first dimension being smaller than the second dimension.

In one embodiment, the bottom end of the second phase change memory cell has a third dimension along the second direction, the top end of the first phase change memory cell has a fourth dimension along the second direction, and the third dimension is greater than the fourth dimension.

The three-dimensional phase change memory may further include: a third layer of address lines on the second phase change memory unit, the third layer of address lines being first signal address lines extending along the first direction; a third phase change memory cell on the third layer of address lines, the third phase change memory cell having a pillar structure perpendicular to the substrate surface; the third phase change memory unit, the third layer of address lines and the side walls of the second phase change memory unit extending along the first direction are sequentially aligned from top to bottom; sidewalls of the third phase change memory cell and the second phase change memory cell extending in the second direction are not coplanar.

Here, the first signal address line is a bit line, and the first direction is a bit line lateral extension direction; the second signal address line is a word line, and the second direction is a word line transverse extension direction; or, the first signal address line is a word line, and the first direction is a word line transverse extension direction; the second signal address line is a bit line, and the second direction is a bit line transverse extension direction.

The second layer address line is a common address line of the first phase change memory unit and the second phase change memory unit; the first phase change memory cell operates based on signals transmitted by the first layer address line and the second layer address line; the second phase change memory unit works based on signals transmitted by the third layer address line and the second layer address line.

In one embodiment, the first layer of address lines are underlying address lines; the second layer of address lines has a thickness greater than a thickness of the first layer of address lines.

The three-dimensional phase change memory may further include: a top layer address line; the thickness of the top layer address line is less than the thickness of the second layer address line.

In a particular embodiment, the first phase change memory cell and the second phase change memory cell each include a stacked phase change memory element, a selector, and a plurality of electrodes, respectively.

This is understood below in conjunction with fig. 10a and 10 b. A three-dimensional phase change memory comprising: a substrate 400; a first layer of address lines 411 on the substrate 400; a first phase change memory cell 410 located on the first layer address line 411, where the first phase change memory cell 410 has a pillar structure perpendicular to the substrate surface, and the first phase change memory cell 410 may include a stacked phase change memory element, a selector, and a plurality of electrodes, and the specific structure thereof may refer to the above preparation method embodiment, and is not described herein again; a second layer address line 422 on the first phase change memory cell 410; a second phase change memory cell 420 located on the second layer address line 422, the second phase change memory cell 420 also having a pillar structure perpendicular to the substrate surface; the specific structure of the second phase change memory cell 420 may be the same as the first phase change memory cell 410. In addition, taking a phase change memory cell with a three-layer stack as an example, the three-dimensional phase change memory may further include: a third layer address line 431 located on the second phase change memory unit 420, wherein an extending direction of the third layer address line 431 is the same as an extending direction of the first layer address line 411, and intersects (may be vertical) an extending direction of the second layer address line 422; a third phase change memory cell 430 located on the third layer address line 431, wherein the third phase change memory cell 430 also has a pillar structure perpendicular to the substrate surface, and the specific structure thereof may be the same as that of the first phase change memory cell 410; a fourth layer of address lines 442 located on the third phase change memory unit 430, wherein the fourth layer of address lines 442 extends in the same direction as the second layer of address lines 422.

In a specific example in which the three-dimensional phase change memory includes only three stacked phase change memory cells, the first phase change memory cell 410, the second phase change memory cell 420, and the third phase change memory cell 430 may be referred to as a Bottom phase change memory cell (BC), a Middle phase change memory cell (Middle cell, MC), and a Top phase change memory cell (Top cell, TC), respectively; the first layer address lines are, for example, bit lines, so 411 in the figure may be referred to as BC BL; the 422 can be called BC/MC WL in the figure corresponding to the first layer address lines being bit lines and the second layer address lines being word lines; the third layer address line is a bit line, and 431 in the figure can be called as MC/TC BL; the fourth layer of address lines are word lines, and 442 may be referred to as TC WL.

FIG. 11 is a schematic diagram illustrating an electron microscope of two adjacent layers of memory cells in a three-dimensional phase change memory according to an embodiment of the invention; as can be seen from the figure, the adjacent two layers of memory cells are self-aligned with the common address line between the two layers, and the side wall has no misalignment problem at all. Compared with two adjacent layers of memory cells in fig. 2, the technical scheme provided by the embodiment of the application solves the problem of increased contact resistance, avoids the deviation of the connection position of the upper word line layer and the lower word line layer, and improves the working stability of the three-dimensional phase change memory.

It should be noted that the embodiment of the three-dimensional phase change memory provided by the invention and the embodiment of the preparation method of the three-dimensional phase change memory belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims

1. A preparation method of a three-dimensional phase change memory is characterized by comprising the following steps:

etching the second phase change memory stack layer and the second address line material layer into a plurality of second phase change structure bodies and second address lines extending along a second direction in the second direction which is intersected with the first direction, and etching the first phase change structure bodies into a plurality of columnar first phase change memory units which are independent of each other and vertical to the surface of the substrate; wherein the second layer address line is a second signal address line;

the first address line material layer is a bottom address line material layer; the thickness of the second address line material layer is more than 1.7 times of the thickness of the first address line material layer.

2. The method of fabricating a three-dimensional phase change memory according to claim 1, further comprising: forming the second phase change structure into a second phase change memory cell;

3. The method of fabricating a three-dimensional phase change memory according to claim 1, further comprising:

4. The method of manufacturing a three-dimensional phase change memory according to claim 1,

the first signal address line is a bit line, and the first direction is a bit line transverse extension direction; the second signal address line is a word line, and the second direction is a word line transverse extension direction; alternatively, the first and second electrodes may be,

5. The method of fabricating a three-dimensional phase change memory according to claim 1, further comprising:

forming an n +1 address line material layer on the nth phase change structure;

wherein n is a positive integer greater than or equal to 2.

6. The method for manufacturing the three-dimensional phase-change memory according to claim 5, wherein the n +1 address line material layer is a top address line material layer;

7. The method of claim 1, wherein the first phase change memory cell is formed to include a stacked phase change memory element, a selector, and a plurality of electrodes.

8. A three-dimensional phase change memory, comprising:

a substrate;

wherein sidewalls of the second phase change memory cells, the second layer of address lines, and the first phase change memory cells extending in the second direction are aligned sequentially from top to bottom;

the first layer of address lines are bottom layer address lines; the thickness of the second layer address line is more than 1.7 times of the thickness of the first layer address line.

9. The three-dimensional phase change memory of claim 8, wherein a bottom end of the second phase change memory cell has a first dimension along the first direction, and a top end of the first phase change memory cell has a second dimension along the first direction, the first dimension being smaller than the second dimension.

10. The three-dimensional phase change memory of claim 8, wherein a bottom end of the second phase change memory cell has a third dimension along the second direction, and a top end of the first phase change memory cell has a fourth dimension along the second direction, the third dimension being greater than the fourth dimension.

11. The three-dimensional phase change memory according to claim 8, further comprising:

12. The three-dimensional phase change memory according to claim 8 or 11,

13. The three-dimensional phase change memory of claim 8, wherein the second layer of address lines are common address lines for the first phase change memory cell and the second phase change memory cell; the three-dimensional phase change memory further includes: a third layer of address lines on the second phase change memory unit, the third layer of address lines being first signal address lines extending along the first direction;

14. The three-dimensional phase change memory according to claim 8, further comprising:

15. The three-dimensional phase change memory according to claim 8, wherein the first phase change memory cell and the second phase change memory cell each include a stacked phase change memory element, a selector, and a plurality of electrodes, respectively.