CN111711444B - Special baud rate generator and communication method - Google Patents

Special baud rate generator and communication method Download PDF

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Publication number
CN111711444B
CN111711444B CN201910203353.4A CN201910203353A CN111711444B CN 111711444 B CN111711444 B CN 111711444B CN 201910203353 A CN201910203353 A CN 201910203353A CN 111711444 B CN111711444 B CN 111711444B
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baud rate
clock
communication protocol
value
reload
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CN111711444A (en
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叶焱枭
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Xiaohua Semiconductor Co ltd
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Xiaohua Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses

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Abstract

According to the present invention, there is providedA baud rate generator, said dedicated baud rate generator comprising a baud rate generator register for setting a reload value corresponding to a baud rate of a current communication protocol according to said baud rate; and a reload counter for dividing the clock corresponding to the current communication protocol according to the reload value to obtain the special baud rate corresponding to the current communication protocol. The current communication protocol comprises UART protocol, SPI protocol and I 2 One of the C protocols.

Description

Special baud rate generator and communication method
Technical Field
The present invention relates to the field of communications, and in particular, to a dedicated baud rate generator and method, and a communication method.
Background
In the field of communications, single function communication interfaces are commonly used, such as universal asynchronous receiver and transmitter (Universal Asynchronous Receiver/Transmitter (UART)), serial peripheral interface (Serial Peripheral Interface (SPI)), integrated circuit bus (Inter-Integrated Circuit (I) 2 C) And the like. When the communication interface is needed to be used, only a plurality of communication interfaces fixed therein can be used, and the flexibility is low.
Disclosure of Invention
An object of the present invention is to provide a dedicated baud rate generator and method and a communication method.
According to an aspect of the present invention, there is provided a dedicated baud rate generator, wherein said dedicated baud rate generator comprises a baud rate generator register for setting a reload value corresponding to a baud rate of a current communication protocol according to said baud rate; and a reload counter for dividing the clock corresponding to the current communication protocol according to the reload value to obtain the special baud rate corresponding to the current communication protocol.
A dedicated baud rate generator according to the above aspect of the invention, wherein said reload counter divides the clock corresponding to the current communication protocol according to said dedicated baud rate.
A dedicated baud rate generator according to the above aspect of the present invention, wherein the current communication protocol includes UART protocol, SPI protocol and I 2 One of the C protocols.
According to the special baud rate generator of the above aspect of the present invention, the baud rate generator register is configured to set the reload value corresponding to a baud rate obtained by dividing an internal clock according to a UART communication protocol, and the reload counter is configured to obtain a special baud rate corresponding to the UART communication protocol according to the reload value and divide the internal clock according to the special baud rate.
According to the special baud rate generator of the above aspect of the present invention, the baud rate generator register is configured to set the reload value corresponding to a baud rate obtained by dividing an external clock according to a UART communication protocol, and the reload counter is configured to obtain a special baud rate corresponding to the UART communication protocol according to the reload value and divide the external clock according to the special baud rate.
A dedicated baud rate generator according to the above aspect of the present invention, wherein the baud rate generator register is configured to set the reload value corresponding to a baud rate obtained by dividing an internal clock according to an SPI communication protocol in a host operation mode, and the reload counter is configured to obtain a dedicated baud rate corresponding to the SPI communication protocol according to the reload value and divide the internal clock according to the dedicated baud rate.
A dedicated baud rate generator according to the above aspect of the invention, wherein said baud rate generator register is adapted to disable said dedicated baud rate in a slave mode of operation.
A dedicated baud rate generator according to the above aspect of the invention, wherein said baud rate generator register is adapted to set said reload value, said reload value being equal to the value according to I 2 The C protocol corresponds to the baud rate obtained by dividing the internal clock, and the reload counter is used for obtaining the corresponding I according to the reload value 2 And C, the special baud rate of the communication protocol, and dividing the frequency of the internal clock according to the special baud rate.
A dedicated baud rate generator according to the above aspect of the invention, wherein said baud rate generator is configured to divide a clock corresponding to said current communication protocol according to said dedicated baud rate to obtain a serial clock frequency.
The special baud rate generator according to the above aspect of the present invention further comprises a first multiplexer for multiplexing an external clock and/or a system clock according to a counter external clock selection bit set in the baud rate generator register and selectively transmitting to the reload counter.
The special baud rate transmitter according to the above aspect of the invention further comprises a first baud rate count comparator for comparing the baud rate comparator count value with the 1/2 baud rate coefficient to generate a first comparison value; a second baud rate count comparator for comparing the baud rate comparator count value with 0 to generate a second comparison value and returning the reload baud rate coefficient value to the reload counter; and a controller for causing the transmission clock when the first comparison value indicates that the baud rate comparator count value is equal to 1/2 baud rate coefficient And according to the frequency division clock with the reload value, when the second comparison value indicates that the counter value of the baud rate comparator is equal to 0, enabling the transmission clock to be equal to the serial clock inversion bit.
The dedicated baud rate generator according to the above aspect of the invention further comprises a second multiplexer for multiplexing the transmission clock and/or the system clock from the controller to provide a clock corresponding to the current communication protocol.
According to yet another aspect of the present invention, there is provided a method comprising setting a reload value corresponding to a baud rate corresponding to a current communication protocol according to the baud rate; and dividing the clock corresponding to the current communication protocol according to the reload value to obtain the special baud rate corresponding to the current communication protocol.
The method according to the above aspect of the invention, wherein the clock corresponding to the current communication protocol is divided according to the dedicated baud rate.
The method according to the above aspect of the present invention, wherein the current communication protocol includes UART protocol, SPI protocol and I 2 One of the C protocols.
The method according to the above aspect of the present invention further includes setting the reload value corresponding to a baud rate obtained by dividing the internal clock according to the UART communication protocol; and obtaining a dedicated baud rate corresponding to the UART communication protocol according to the reload value, and dividing the internal clock according to the dedicated baud rate.
The method according to the above aspect of the present invention further includes setting the reload value corresponding to a baud rate obtained by dividing an external clock according to a UART communication protocol; and obtaining a dedicated baud rate corresponding to the UART communication protocol according to the reload value, and dividing the external clock according to the dedicated baud rate.
The method according to the above aspect of the present invention further comprises setting the reload value corresponding to a baud rate obtained by dividing the internal clock according to the SPI communication protocol in the host operation mode; and obtaining a dedicated baud rate corresponding to the SPI communication protocol according to the reload value, and dividing the internal clock according to the dedicated baud rate.
The method according to the above aspect of the present invention further comprises disabling the dedicated baud rate in a slave mode of operation of the SPI communication protocol.
The method according to the above aspect of the invention further comprises setting the reload value, the reload value being equal to the value according to I 2 The protocol C corresponds to the baud rate obtained by dividing the internal clock; and obtaining a value corresponding to the I according to the reload value 2 And C, the special baud rate of the communication protocol, and dividing the frequency of the internal clock according to the special baud rate.
The method according to the above aspect of the invention further comprises dividing the clock corresponding to the current communication protocol according to the dedicated baud rate to obtain a serial clock frequency.
The method according to the above aspect of the invention further comprises multiplexing the external clock and/or the system clock according to the counter external clock selection bits.
The method according to the above aspect of the present invention further comprises comparing the baud rate comparator count value with a 1/2 baud rate coefficient to generate a first comparison value; comparing the baud rate comparator count value with 0 to generate a second comparison value; returning the reload baud rate coefficient value to a reload counter; and when the first comparison value indicates that the baud rate comparator count value is equal to 1/2 baud rate coefficient, enabling the transmission clockAnd according to the frequency division clock with the reload value, when the second comparison value indicates that the counted value of the baud rate comparator is equal to 0, making the transmission clock equal to the serial clock inversion bit.
The method according to the above aspect of the invention further comprises multiplexing the transmission clock and/or the system clock to provide a clock corresponding to the current communication protocol.
According to one aspect of the present invention, there is provided a communication method including setting an interface mode consistent with a master Central Processing Unit (CPU) in a slave CPU based on a current communication protocol; receiving data from the main control CPU; and sending response data to the main control CPU.
The method according to the above aspect of the present invention, wherein the current communication protocol comprises a UART protocol, and the interface mode comprises a UART interface mode.
The method according to any of the above aspects of the invention, wherein the current communication protocol comprises an SPI protocol and the interface mode comprises an SPI interface mode.
According to the method of any one of the above aspects of the present invention, wherein the slave CPU determines whether to receive the data from the master CPU according to a flag bit determination, and reads and processes the data in response to the data being received according to the flag bit determination.
The method according to any one of the above aspects of the present invention, further comprising setting a master input and slave output pin of the slave CPU as serial data input, setting 7 or 8 as data bit and setting 1 or 2 as stop bit in accordance with the setting of the master CPU.
The method according to any one of the above aspects of the present invention, further comprising enabling a receiving and transmitting operation of the slave CPU.
The method according to any one of the above aspects of the present invention, further comprising receiving address data from a master CPU, and initiating communication with the master CPU by determining that an address in the address data is the same as an allocated address of the slave CPU.
The method according to any one of the above aspects of the present invention, further comprising setting a master output of the slave CPU to be a serial data output from an input pin in response to determining that an address in the address data is the same as an allocated address of the slave CPU.
The method according to any of the above aspects of the present invention, further comprising communicating with the master CPU using the master output slave input pins.
Drawings
FIG. 1 is a schematic block diagram of a multifunction serial protocol controller in accordance with one embodiment of the invention;
FIG. 2 is a schematic block diagram of a dedicated baud rate generator according to one embodiment of the invention;
FIG. 3 is a schematic diagram of a bi-directional communication connection in UART operational mode 0 according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of a bi-directional communication connection in UART operational mode 0 according to one embodiment of the present invention;
FIG. 5 is a schematic diagram of a bi-directional communication flow according to one embodiment of the invention;
FIG. 6 is a schematic diagram of a master/slave communication connection on a UART according to one embodiment of the present invention;
FIG. 7 is a schematic flow chart diagram of master/slave communication in accordance with one embodiment of the present invention;
FIG. 8 is a schematic block diagram of a bi-directional communicating SPI interface connection, in accordance with one embodiment of the present invention;
FIG. 9 is a schematic flow chart diagram of bi-directional communication in SPI mode of operation in accordance with one embodiment of the present invention;
FIG. 10 is a diagram of I in accordance with one embodiment of the present invention 2 Schematic diagram of starting conditions of the C bus;
FIG. 11 is a diagram of I in accordance with one embodiment of the present invention 2 Schematic diagram of stop condition of C bus;
FIG. 12 is a diagram of I in accordance with one embodiment of the present invention 2 Schematic diagram of repeated starting conditions of the C bus;
FIG. 13 is a diagram of I in accordance with one embodiment of the present invention 2 Schematic diagram of one example of communication flow;
FIG. 14 is a diagram of I in accordance with one embodiment of the present invention 2 Schematic diagram of one example of communication flow; and
FIG. 15 is a diagram of I in accordance with one embodiment of the present invention 2 Schematic diagram of one example of communication flow.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
According to one embodiment of the present invention, the multifunctional serial communication interface may select any one of the following communication modes according to the setting of the operation mode:
(1) UART0 (asynchronous standard serial interface)
(2) UART1 (asynchronous multiprocessor interface)
(3) SPI (serial peripheral interface/clock synchronous communication)
(4)I 2 C(I 2 C bus interface)
(5) The special baud rate module generates clock and baud rate of serial port
(6) 1-3 latency times can be inserted between the reception and transmission of continuous data in SPI
Table 1 shows an example of interface mode switching, according to one embodiment of the present invention. In the case of communication through each serial communication interface, the interface operation mode may be set using a serial mode register (Serial Mode Register (SMR)) shown in table 1 before communication is started.
TABLE 1
Fig. 1 shows a schematic block diagram of one example of a multi-function serial interface 100 in accordance with one embodiment of the invention. As shown in FIG. 1, the multifunction serial interface 100 may include a multifunction serial protocol controller 110 for selecting an interface operation mode from one or more interface operation modes, such as those described in Table 1 above, and an Input/Output (I/O) interface 130 for data transmission to and from the multifunction serial protocol controller 130 the multifunction serial protocol (UART/SPI/I 2 C) The controller 108 may include a chip select output, such as an SPI.
The multifunction serial protocol controller 110 includes a bus interface 102, a multifunction configuration register 104, a baud rate controller 106, a parallel input output controller 108, a serial transmission protocol state machine 112, a serial output control 114, a serial input control 116, a UART module 118, an SPI module 120, and/or an I 2 And a C module 122. For example, the baud rate controller 106 may include a dedicated baud rate generator. Although UART controller 118, SPI controller 120, I are shown in FIG. 1 2 The C controller 122, in other embodiments, may also include a control module based on other communication protocols. The serial output control 114 and serial input control 116 may include chip select outputs of the SPI.
Referring to fig. 1, a bus interface 102 may be used to connect inputs and/or outputs of a bus and/or other modules. The multifunction configuration register 104 may be used to select the current communication protocol according to table 1 above, for example, the multifunction configuration register 104 may provide an enable signal and/or a configuration signal corresponding to the selected communication protocol to the selected control module, UART controller 118, SPI controller 120, or I 2 And a C controller 122. According to one embodiment, the enable signal and the configuration signal may refer to the following related UART operation/SPI operation/I 2 Description of C operation.
Fig. 2 illustrates an example of the dedicated baud rate generator 106 of fig. 1, according to one embodiment of the invention. According to one embodiment of the invention, the dedicated baud rate generator 106 may include a baud rate generator register 202, a first multiplexer 206, a reload counter 208, first and second baud rate count comparators 210 and 212, a controller 214, and/or a second multiplexer 216. For example, the baud rate generator register 202 may include a first register BRS1 and a second register BRS0. The baud rate generator register 202 may be coupled to an advanced peripheral bus (Advanced Peripheral Bus (APB)).
The first multiplexer 206 may multiplex an external clock (peripheralclock (PCLK)) and a System Clock (SCLK) according to a counter external clock select bit (e.g., brs1. Ext) set in the baud rate generator register 202 and selectively pass to the reload counter 208. The reload counter 208 may take the clock clk (e.g., an external clock or an internal clock) from the first multiplexer 206 as an operating clock. The reload counter 208 may receive the baud rate coefficient 204 (timer reload value) from the baud rate generator register 202. The reload counter 208 may include a first counter register BGR1 and a second counter register BGR0 for dividing the operation clock clk of the first multiplexer 206 according to the setting values (e.g., reload values) in the baud rate generator registers (BRS 1 and BRS 0) and outputting the division results to the first and second baud rate count comparators 210 and 212, respectively.
According to an embodiment, the first baud rate count comparator 210 may comprise a 1/2 baud rate count comparator. The second baud rate count comparator 212 may comprise a baud rate count comparator. The first baud rate count comparator 210 may compare the baud rate comparator count value (cnt data) with the 1/2 baud rate coefficient and generate a first comparison value Sel1 according to the comparison result. For example, if the baud rate comparator count cnt_data is equal to 1/2 baud rate coefficient, the first comparison value Sel1 may be a logic "1". The second baud rate count comparator 212 may compare the baud rate comparator count value (cnt data) with 0 and generate a second comparison value Sel0 according to the comparison result. For example, if the baud rate comparator count value cnt_data=0, the second comparison value Sel0 may be a logical "1". The first and second baud rate count comparators 210 and 212 may output a first comparison value Sel1 and a second comparison value Sel0, respectively, to the controller 214. The second baud rate count comparator 212 may return the reload baud rate coefficient value to the reload counter 208.
The controller 214 may invert the transmit clock (tclk) to tclk (e.g., the input clock to generate a divided clock according to the reload value as described below) when sel1=1 (e.g., cnt data=1/2 baud rate coefficient), and tclk=cinv (serial clock inversion bit) when sel0=1 (e.g., cnt data=0). The controller 214 may transfer the obtained clock tclk to the second multiplexer 216, and then the second multiplexer 216 multiplexes the transfer clock tclk or the system clock sclk to be transferred to the serial protocol state machine 112 as t1 as shown in fig. 1. According to one embodiment, in UART mode, the dedicated baud rate generator 106 (e.g., the override counter 208) may set the baud rate obtained by dividing the internal clock to a 15-bit override value in the baud rate generator register 202 (e.g., BRS1, BRS 0) to select the baud rate. Each reload counter 208 may divide the internal clock by the set value. A clock source may be provided in the baud rate generator register 202 to select an internal clock (e.g., BRS1: ext=0).
For example, the dedicated baud rate generator 106 (e.g., the reload counter 208) may use the external clock as a clock source for the reload counter 208 for the baud rate obtained by dividing the external clock. The external clock is input from a System Clock (SCLK) 232. After setting the 15-bit reload value in the baud rate generator registers 202 (BRS 1 and BRS 0), the baud rate may be selected. Each reload counter 208 divides the external clock by the set value. The clock source is set and the external clock and the baud rate generator clock are selected for use (e.g., BRS1: ext=1).
According to another embodiment, in the SPI mode, the setting method of the dedicated baud rate generator in the master mode and the slave mode may be different for the baud rate selection of the SPI.
For example, in the host mode of operation, the internal clock frequency is divided using dedicated baud rate generator 106 and the division is selectively output. The dedicated baud rate generator 106 may provide, for example, two reload counters 208 for generating serial clocks for receive and transmit operations, respectively. The 15-bit reload value may be set by configuring the baud rate generator registers 202 (BRS 1 and BRS 0). The internal clock frequency may be divided by the set reload value to obtain a serial clock and output the serial clock to the serial protocol state machine 112 via the second multiplexer 216. For the slave mode of operation, the dedicated baud rate is disabled in the slave mode (e.g., CR: mss=1), the external clock may be directly input through the clock input pin SCK, and/or as an output to the serial protocol state machine 112 via the second multiplexer 216.
According to another embodiment, at I 2 In the C-mode, the dedicated baud rate generator 106 (reload counter 208) may divide the baud rate obtained by the internal clock, using the first and second baud rate generator registers (BRS 1 and BRS 0) to set the 15-bit reload value to select the baud rate. The reload counter 208 may divide the internal clock by the set value.
As shown in fig. 1, a parallel input output controller 108 may be connected to the bus interface 102 to obtain transmitted data and received data.
The serial transport protocol state machine 112 may obtain control logic behavior to serially output the transport data obtained by the parallel input output controller 108 and chip select output of the SPI according to the currently selected communication protocol.
The serial output control 114 and the serial input control 116 are used to obtain serial output data and serial input data, respectively, to input data and clock control outputs to the I/O port 130, respectively, and to control whether the output inputs are inverted.
UART controller 118, SPI controller 120 and I 2 The C controller 122 may receive respective enable signals and/or configuration signals from the multifunction configuration registers 104 to obtain control logic behavior.
As shown in fig. 1, in one embodiment, the multifunction configuration register 104 can selectively provide communication protocol data corresponding to a current communication protocol of the multifunction serial communication interface 100. The multifunction serial communication protocol controller 110 can control the multifunction serial communication interface 100 to communicate according to the current communication protocol according to the communication protocol data from the multifunction configuration register 104.
In one embodiment, the dedicated baud rate generator 106 is configured to divide a clock (internal clock or external clock) corresponding to the current communication protocol according to the communication protocol data from the multifunction configuration register 104 to generate a clock divided baud rate corresponding to the current communication protocol.
According to one embodiment, the UART controller 118, the SPI controller 120, and the I 2 The controller corresponding to the current communication protocol among the C controllers may perform serial interface control corresponding to the current communication protocol according to the communication protocol data from the multifunction configuration register 104.
In one embodiment, the multifunction configuration register 104 can provide an enable signal and a configuration signal corresponding to a current communication protocol to a controller of the plurality of controllers 118, 120, and 122 corresponding to the current communication protocol to cause the controller to initiate the serial interface control corresponding to the current communication protocol.
In one embodiment, the dedicated baud rate generator 106 may set a reload value corresponding to the current communication protocol according to the clock-divided baud rate, and select a dedicated baud rate according to the reload value.
In one embodiment, the dedicated baud rate generator 106 may divide the clock corresponding to the current communication protocol according to the selected dedicated baud rate to obtain a serial clock.
In one embodiment, the serial protocol state machine 112 may obtain serial transmission data and/or chip select transmission data of the SPI corresponding to the parallel transmission data according to the current communication protocol according to serial interface control performed by the controller corresponding to the current communication protocol.
In one embodiment, the parallel input output controller 108 may be used to obtain parallel transmission data.
In one embodiment, the serial output controller 116 and the serial input controller 114 may control the output/input of one or more of the serial transmission data, the chip select transmission data of the SPI, and the serial clock, respectively, and may control the inversion of the output/input.
In one embodiment, the reload counter 208 may divide the clock corresponding to the current communication protocol according to the reload value set by the dedicated baud rate generator to obtain a dedicated baud rate.
In UART operation, one or more (asynchronous serial interface) functions may be implemented as shown in table 2 below.
TABLE 2
In one embodiment, in UART mode, the UART register list described in Table 3 below may be used.
TABLE 3 Table 3
In one embodiment, dedicated baud rate generator 106 may operate as follows. For example, the clock source of UART transmit/receive may select an internal clock of the dedicated baud rate generator 106 (reload counter 208) or an external clock input to the dedicated baud rate generator 106 (reload counter 208). The dedicated baud rate generator 106 may select the baud rate as follows.
In one example, dedicated baud rate generator 106 (reload counter 208) may divide the internal clock to obtain the baud rate. For example, a 15-bit reload value may be set in the first and second baud rate generator registers BRS1 and BRS0 to select the baud rate. Each reload counter 208 (e.g., first counter register BGR1 and second counter register BGR 0) may divide the internal clock by the set value to obtain the baud rate. The clock source may be set to select an internal clock (e.g., brs1:ext=0).
In another example, the dedicated baud rate generator 106 (reload counter 208) may divide the external clock to obtain the baud rate. For example, an external clock may be used as the clock source for the reload counter 208. For example, an external clock may be input from SCLK 232. A 15-bit reload value may be set in the first and second baud rate generator registers BRS1 and BRS0 to select the baud rate. Each reload counter 208 (e.g., first and second counter registers BGR1 and BGR 0) may divide the external clock by the set value to obtain the baud rate. The clock source may be set to select the use of an external clock and a baud rate generator clock (e.g., BRS1: ext=1). In one embodiment, the mode may be used in the case of a non-standard frequency oscillator.
If the external clock is selected (BRS 1: ext=1), the reload counter 208 may be suspended (BGR 1/0=15' h 00). If an external clock (BRS 1: ext=1) is selected, its HIGH (HIGH) and LOW (LOW) levels may have a width of at least two bus clocks.
According to one embodiment, dedicated baud rate generator 106 may calculate the baud rate as follows. For example, the baud rate generator registers 202 (BRS 1 and BRS 0) may be used to set a 15-bit reload counter.
In one embodiment, the reload value may be represented by the following formula (1):
v=φ/b-1 type (1)
Where V represents the reload value, b represents the baud rate, and φ represents the bus clock frequency or the external clock frequency.
For example, if the bus clock is a 16MHz internal clock, the baud rate is set to 19200bps and the reload value may be set to: v= (16 x 1000000)/19200-1=832, the actual (current) baud rate is: baud rate (calculated) = (16×1000000)/(832+1) = 19218 (bps).
If a bus clock of 20MHz and a baud rate of 153600bps are set, the reload value may be set to: v= (20×1000000)/153600-1=129, the baud rate (calculated value) = (20×1000000)/(129+1) = 153846 (bps).
The baud rate error can be calculated as follows (2):
Error (%) = (count value-target value)/target value×100 (2)
In one embodiment, if the reload value is set to "0", the reload counter is stopped. In another embodiment, if the reload value is even, the LOW level "L" is wider than the HIGH level ("H") for one period of the receive serial clock. If the reload value is odd, the HIGH level and LOW level of the serial clock are the same width.
In one embodiment, the reload value may be greater than 3, but in some embodiments, the data may not be received properly due to baud rate errors and the setting of the reload value. If the reload value is set to less than 3, the baud rate compensation function can be used to improve the transmission. For example, if the system frequency is 32KHz, for a baud rate of 9.6K, the baud rate compensation function may be matched to achieve accuracy in transceiving data.
In yet another embodiment, in case of a heavy load value greater than 3, the baud rate compensation function may be combined to obtain a more accurate baud rate.
Table 4 below shows the corresponding reload values and baud rates for each bus clock frequency (where reload values are the BRS1/0 register settings (decimal), and errors are baud rate errors (%):
TABLE 4 Table 4
Fig. 3 shows an example of interconnection by two central processing units (Central Processing Unit (CPUs)) according to one embodiment of the invention. In one embodiment, the multifunctional serial communication interface may implement CPU-to-CPU connection in UART mode 0 (asynchronous normal mode) of operation. In UART mode 0, for example, two-way communication may be selected.
As shown in fig. 3, the first CPU 310 and the second CPU 320 may perform bidirectional communication in UART operation mode 0. The first CPU 310 may include one or more pins or ports, such as a serial output (Serial Output Terminal (SOT)) 312, a serial input (SerialInput (SIN)) 314, and/or a System Clock (SCK) 316. The second CPU 320 may include a SOT 322, a SIN 324, and/or an SCK 326. In one embodiment, the first CPU 310 may be a master CPU and the second CPU 320 may be a slave CPU, or vice versa.
The master CPU 310 may send data to the SIN pin 324 of the slave CPU 320 via the SOT pin 312. The slave CPU 320 may send data to the master CPU 310 via the SOT pin 312, and the master CPU 310 may receive data from the slave CPU 320 via the SIN pin 314.
One example of a CPU pin is shown in FIG. 3, and other embodiments may include other pin arrangements. Further, other embodiments may include multiple master CPUs and/or multiple slave CPUs.
In one embodiment, the bi-directional communication connection disables flow control in UART mode of operation 0 shown in fig. 3. FIG. 4 illustrates an example of a bi-directional communication connection in UART mode 0 of operation with flow control according to one embodiment of the present invention.
As shown in fig. 4, the first CPU 410 and the second CPU 430 may perform bidirectional communication in UART operation mode 0. The first CPU 410 and the second CPU 430 may include one or more pins or ports, such as a master-output-slave input (master output slave input (MOSI)), a master-input-slave output (master input slave output (MISO)), SCK, clear-to-Send (CTS), and/or Request-to-Send (RTS). In one embodiment, the first CPU 410 may be a master CPU and the second CPU 420 may be a slave CPU, or vice versa.
As shown in fig. 4, master CPU 410 may send data to slave CPU 430 via MOSI pin 412 and receive data from slave CPU 430 via MISO pin 414. Master CPU 410 may send data to CTS pin 438 of slave CPU 430 via RTS pin 420 and receive data from slave CPU 430 via CTS pin 418. Similarly, slave CPU 430 may send data to master CPU 410 via MOSI pin 432 and receive data from master CPU 410 via MISO pin 434. Slave CPU 430 may send data to CTS pin 418 of master CPU 410 via RTS pin 440 and receive data from master CPU 410 via CTS pin 438.
One example of a CPU pin is shown in FIG. 4, and other embodiments may include other pin arrangements.
FIG. 5 illustrates an example of bi-directional communication in UART mode 0 according to one embodiment of the present invention. For example, the flow chart shown in FIG. 5 may utilize an example of a bi-directional communication connection in UART mode 0 shown in FIG. 3 or 4.
As shown in fig. 5, at block 502, the first CPU of the transmitting end may set an operation mode, such as UART mode 0. At block 512, the second CPU of the receiving end may set the corresponding operation mode so that its operation mode matches the setting of the transmission test, e.g., the second CPU may set the operation mode to UART mode 0.
At block 504, the first CPU may set first data, e.g., 1 byte, in a transmit data register (TXDR) and initiate a communication to transmit the first data to the second CPU. If the first data sent by the first CPU from the transmitting side is received, the second CPU of the receiving side may determine that RDEF is equal to 1 (decision block 514). If the second CPU determines that the received data is full flag bit (RDFF) =1, the received first data is read and processed (block 516). At block 518, the second CPU sends, for example, 1 byte of second data (ANS) to the first CPU and returns to decision block 514 to determine whether data from the first CPU was received via RDFF. Conversely, if the second CPU determines at decision block 514 that RDFF is not equal to 1 (the first data from the first CPU is not received), the second CPU continues to determine at decision block 514 whether RDFF is equal to 1 until the first data is received.
At decision block 506, if the second data is received from the second CPU, the first CPU reads and processes the received second data (block 508) and returns to block 504 to continue sending data to the second CPU.
Conversely, if it is determined at decision block 506 that RDFF is not equal to 1, e.g., no second data (ANS) is received from the second CPU, the first CPU continues the determination of RDFF at decision block 906 until it is determined that rdff=1 (second data is received from the second CPU).
FIG. 6 illustrates an example of a communication connection in UART mode 1 of operation (asynchronous multiprocessing mode) according to an embodiment of the invention. For example, in the master/slave communications shown in fig. 6, the communications system may be configured with first and second common communications lines 630 and 640 to connect with a master CPU 610 and one or more slave CPUs 620A/620B, etc. In one embodiment, the UART may be used as a master or slave.
Master CPU 610 may send data from first common communication line 630 via MOSI pin 312 to MISO pins 624A/624B of slave CPUs 620A/620B, respectively. Slave CPUs 620A/620B may send data from the second common communication line 640 to master CPU 610 via MOSI pins 622A/622B, respectively, and master CPU 610 may receive data from slave CPUs 620A/620B via MISO pin 614.
One example of a CPU pin is shown in FIG. 6, other embodiments may include other pin arrangements. Further, other embodiments may include multiple master CPUs and/or multiple slave CPUs.
In one embodiment, in UART mode 1 of operation, the master/slave function selection may be performed as described in table 5. Table 5 shows selected communication function selections in master/slave communications, such as operating mode and/or data transmission system selections.
TABLE 5
In one embodiment, in UART mode of operation 1, transmit/receive data (TXDR/RXDR) is operated in a word access mode.
FIG. 7 illustrates an example of communication in UART operational mode 1 (multiprocessor mode) according to an embodiment of the present invention. In one embodiment, the communication is initiated when the host CPU sends address data. The address data is a data set with D8 bit being 1, and is used for selecting the slave CPU for communication. Each slave CPU determines an address according to fig. 7, and if the address matches the assigned address, communicates with the host CPU.
As shown in fig. 7, at block 702, the master CPU may set an operation mode, such as UART mode 1. At block 732, the slave CPU may set the corresponding operating mode to match its operating mode to that of the master CPU, e.g., the slave CPU may set the operating mode to UART mode 1.
At block 704, the master CPU may set the MISO pin to a serial data input and the MOSI pin to a serial data output. At block 706, the master CPU may set 7 or 8 bits of data and set 1 or 2 bits of stop bits. At block 708, the master CPU may set the D8 bit to "1". At block 710, the master CPU may enable transmit/receive operations. At block 712, the master CPU may transmit the slave address to the slave CPU.
At block 734, the slave CPU may set the MISO pin to the serial data input. At block 736, the slave CPU may set 7 or 8 bits of data and set 1 or 2 bits of stop bits. At block 738, the slave CPU enables transmit/receive operations. At block 740, the slave CPU receives the byte sent by the master CPU and determines at decision block 742 whether the D8 bit of the received byte is 1. If the slave CPU determines that the D8 bit is "1", then at decision block 744 it is determined whether the slave address from the master CPU matches its assigned address. Conversely, if the slave CPU determines at decision block 742 that the D8 bit is not "1", the slave CPU returns to block 740 to continue receiving slave addresses from the master CPU and determines at decision block 744 if the slave addresses match. If it is determined at decision block 744 that the slave address from the master CPU matches its assigned address, the slave CPU sets the MOSI pin to a serial data output at block 746. Otherwise, the slave CPU returns to block 738.
After transmitting the slave address, the master CPU may set D8 to "0" at block 714. At block 716, the master CPU communicates with the address-matched slave CPU. Accordingly, at block 748 the slave CPU communicates with the master CPU. Until it is determined at decision blocks 718 and 750 that the communication is complete. If the communication is not complete, the master CPU and slave CPU return to blocks 716 and 748, respectively, to continue the communication.
If the master CPU determines at decision block 718 that communication with the slave CPU is complete, the master CPU determines at decision block 720 whether the master CPU is in communication with other slave CPUs. If a determination is made to communicate with other slave CPUs, the master CPU disables transmit/receive operations at block 722 and returns to block 702 for communication with other slave CPUs. In contrast, if the master CPU determines not to communicate with other slave CPUs at decision block 720, the master CPU ends the operation, thereby completing the communication.
According to another embodiment of the present invention, the multifunctional serial communication interface may implement SPI operation. Table 6 shows an example of the SPI function.
TABLE 6
Table 7 shows one example of an SPI register list, according to one embodiment.
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TABLE 7
In one embodiment, the dedicated baud rate generator in SPI mode of operation is only active in host mode. For SPI baud rate selection, the method of setting dedicated baud rate generators in master mode is different from that in slave mode.
In one example, in a host mode of operation, the internal clock frequency may be divided using dedicated baud rate generator 106 and the division selected output.
The dedicated baud rate generator 106 may provide two reload counters 208 to generate serial clocks for receive and transmit operations, respectively. The 15-bit reload value may be set by configuring the baud rate generator registers (BRS 1 and BRS 0). The internal clock frequency can be divided by the set reload value to obtain the serial clock frequency.
In another example, in the slave mode of operation, the dedicated baud rate is inactive in the slave mode (CR: mss=1) (e.g., the external clock may be directly input through clock input pin SCK).
In accordance with one embodiment of the present invention, in SPI mode, two 15-bit reload counters 208 are set by the baud rate generation registers (BRS 1 and BRS 0).
In one embodiment, the reload value may be represented by the following formula (3):
v=φ/b-1 type (3)
Where V represents the reload value, b represents the baud rate, and φ represents the bus frequency.
For example, if the bus clock is a 16MHz internal clock, the baud rate is set to 19200bps and the reload value may be set to: v= (16 x 1000000)/19200-1=832, the actual baud rate is: baud rate (calculated) = (16×1000000)/(832+1) = 19218 (bps).
If a bus clock of 20MHz and a baud rate of 153600bps are set, the reload value may be set to: v= (20×1000000)/153600-1=129, the baud rate (calculated value) = (20×1000000)/(129+1) = 153846 (bps).
The baud rate error can be calculated as follows (4):
error (%) = (count value-target value)/target value×100 (4)
In one embodiment, if the reload value is set to "0", the reload counter is stopped. In another embodiment, if the reload value is even, the width of the low level "L" and the width of the high level "H" of the serial clock are related to the settings of MR: CINV and CR: SPIMODE. If the reload value is odd, the width of the high level "H" and the width of the low level "L" of the serial clock are the same.
In the chip-free transmission mode (e.g., CR: spimode=0) and the serial clock detection level is high level "H" (MR: cinv=0), or in the chip-free transmission mode (CR: spimode=1) and the serial clock detection level is low level "L" (MR: cinv=1), the width of the high level "H" of the serial clock will be longer than the width of the low level "L" by 1 bus clock cycle.
In the chip-free transmission mode (CR: spimode=0) and the serial clock detection level is a low level "L" (MR: cinv=1), or in the chip-free transmission mode (CR: spimode=1) and the serial clock detection level is a high level "H" (MR: cinv=0), the width of the low level "L" of the serial clock will be longer than the width of the high level "H" by 1 bus clock cycle.
In another embodiment, the reload value is set to 3 or more. Table 8 shows reload values and baud rates corresponding to each bus clock frequency in SPI mode, according to one embodiment of the invention.
TABLE 8
FIG. 8 illustrates an example of a SPI interface for bi-directional communication, in accordance with one embodiment of the present invention. Master CPU 810 and slave CPU 820 may communicate bi-directionally in the SPI mode of operation as shown in fig. 8. For example, master CPU 810 may send data to slave CPU 820 via MOSI pin 812 and receive data from slave CPU 820 via MISO pin 814. Master CPU 810 may send clock signal 830 via SCK pin 816 to SCK pin 826 of slave CPU 820.
The master CPU 310 may send data to the SIN pin 324 of the slave CPU 320 via the SOT pin 312. The slave CPU 320 may send data to the master CPU 310 via the SOT pin 312, and the master CPU 310 may receive data from the slave CPU 320 via the SIN pin 314.
One example of a CPU pin is shown in FIG. 8, other embodiments may include other pin arrangements. Further, other embodiments may include multiple master CPUs and/or multiple slave CPUs.
Fig. 9 shows an example of bi-directional communication in SPI mode according to one embodiment of the invention. As shown in fig. 9, at block 902, the host-side master CPU may set an operating mode, such as SPI mode. At block 912, the slave CPU on the slave side may set the corresponding mode of operation to coincide with the mode of operation on the master side. For example, the slave CPU may set the operation mode to the SPI mode.
At block 904, the master CPU may write the first byte of data in a transmit data register (TXDR) and the communication begins. The master CPU sends the first byte data to the slave CPU. If the first byte data sent from the master CPU is received, the slave CPU may determine that RDEF is equal to 1 (decision block 914). If the slave CPU determines rdff=1, the received first byte data is read and processed (block 916). At block 918, the slave CPU sends, for example, 1 byte of second data (ANS) to the master CPU and returns to decision block 914 to determine whether data is received from the master CPU via RDFF.
In contrast, if the slave CPU determines at decision block 914 that RDFF is not equal to 1 (the first byte data from the master CPU is not received), the slave CPU continues to determine at decision block 914 whether RDFF is equal to 1 until the first byte data is received.
At decision block 906, if second data is received from the slave CPU, the master CPU determines rdff=1 to read and process the second data from the slave CPU at block 908 and returns to block 904 to continue sending data to the slave CPU.
In contrast, if it is determined at decision block 906 that RDFF is not equal to 1, for example, the second data (ANS) from the slave CPU is not received, the master CPU continues the determination of RDFF at decision block 906 until rdff=1 is determined (the second data from the slave CPU is received).
According to a further embodiment of the invention, the multifunctional serial communication interface may implement I 2 And C, operating. Table 9 below shows I in accordance with one embodiment of the present invention 2 One example of a C function.
TABLE 9
Table 10 below shows I, according to one embodiment of the invention 2 An example of a list of C registers.
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Table 10
According to one embodiment of the invention, a dedicated baud rate generator 106 may be used to set the serial clock frequency. For example, the baud rate may be selected using a baud rate obtained by dividing the internal clock by the dedicated baud rate generator 106 (reload counter 208).
The 15-bit reload value may be set using the first and second baud rate generator registers 1 and 0 (BRS 1/BRS 0) to select the baud rate. The reload counter 208 may divide the internal clock by a set value.
In one embodiment, two registers (BRS 1 and BRS 0) may be utilized to set the baud rate setting of the 15-bit reload counter. For example, the reload value is calculated according to the following formula (5):
v=φ/b-1 type (5)
Where V represents the reload value, b represents the baud rate, and φ represents the bus clock frequency. In one embodiment, if at I 2 And if the rising edge time of the signal of the C bus does not generate the preset baud rate, adjusting the reloading value.
If the bus clock is 16MHz, the reload value at 400bps is: v= (16 x 1000000)/400000-1=39, the actual baud rate is: b= (16×1000000)/(39+1) =400 (bps).
For example, the baud rate generator register 1 and the baud rate generator register 0 (BRS 1, BRS 0) are write-accessed in units of 16 bits. The baud rate generator register is set when the slave mask enable bit (SAMSK: EN) of the slave address mask register (SAMSK) is "0". At I 2 In the C mode, the bus clock is not lower than 8MHz, and setting of a wave exceeding 400kbps is prohibitedAnd a specific rate generator. And when the reload value is 0, stopping the working of the reload counter.
Table 11 shows the reload values and baud rates corresponding to the individual bus clock frequencies.
TABLE 11
As shown in Table 11, the values are I 2 When the serial clock line (Serial Clock Line (SCL)) of the C bus rises to 0 s. I 2 When the serial clock line SCL of the C bus rises for delay, the baud rate is delayed from the above value. If not, it can be set with reference to equation (5).
In one embodiment, I 2 The C-bus may include a Serial Data line (SDA)) and a Serial clock line SCL. FIGS. 10-12 illustrate I in accordance with one embodiment of the invention 2 Examples of C bus operations. FIG. 10 shows I 2 An example of a startup condition for the C bus. As shown in fig. 10, if the serial data line 1010 transitions from a high level to a low level (block 1030) while the serial clock line 1020 is high, I 2 And C, starting the bus.
FIG. 11 shows I 2 An example of a stop condition for the C bus. As shown in FIG. 11, if the serial data line 1010 transitions from a low to a high level (block 1130) while the serial clock line 1020 is high, I 2 The C bus stops.
FIG. 12 shows I 2 An example of a repeated start condition of the C bus. As shown in fig. 12, after serial clock line 1020 issues an acknowledgement signal (ACK 1240) and serial clock line 1020 transitions high, if serial data line 1010 transitions from high to low (block 1230), then I 2 And C, repeatedly starting the bus.
FIG. 13 shows an example of I in accordance with another embodiment of the present invention 2 An example of an operational flow. The CPU may perform I using the flow shown in FIG. 13 2 C bus operation. For example, fig. 13 may be applicable to the master mode.
As shown in FIG. 13, at block 1302, the CPU may perform initial settings, such as Baud Rate (BRS), slave Address (SA), slave mask settings (SAMSK), and/or I 2 C enable (SAMSK: en=1), and the like. At decision block 1304, the CPU may determine whether it is in master mode. If it is determined at decision block 1304 that the master mode is not, flow may proceed to a slave mode (1400), such as that shown in FIG. 14.
Conversely, if it is determined at decision block 1304 that the master mode is selected, then transmit data (TXDR) is written at block 1306 and/or the master mode is set (e.g., master select bit BCR: mss=1). At decision block 1308, the CPU may determine whether the interrupt flag clears zero (BCR: INTF) is 1. If it is determined at decision block 1308 that BCR: INTF is not 1, flow returns to decision block 1308. Conversely, if it is determined at decision block 1308 that BCR: intf=1, flow proceeds to decision block 1310. Referring to fig. 13, 14 and 15, the flow of fig. 14 or 15 may proceed from circle a (1420) to decision block 1308 shown in fig. 13.
At decision block 1310, the CPU may determine whether the bus error bit (BCR: BERF) is zero. If it is determined at decision block 1310 that BCR-BERF is not zero, flow proceeds to block 1312. At block 1312, the CPU performs bus error processing, and the process ends. Conversely, if it is determined at decision block 1310 that BCR: berf=0, flow proceeds to decision block 1314 to determine whether the repeated start settings bit (BCR: OFITS) is 1. At decision block 1314, if the CPU determines that BCR: OFITS is not 1, flow proceeds to block 1316 to perform arbitration loss processing, and flow ends. Conversely, if it is determined at decision block 1314 that BCR: ofits=1, then flow proceeds to decision block 1318.
At decision block 1318, the CPU may determine whether the master slave select bit (BCR: MSS) is 1. If it is determined at decision block 1318 that BCR: MSS is not 1, then flow proceeds to slave mode (1400). In contrast, if it is determined at decision block 1318 that BCR: mss=1, flow proceeds to decision block 1320. At decision block 1320, the CPU may determine whether the reserved address detection bit (IBSR: RAD) is zero. If it is determined at decision block 1320 that IBSR RAD is not 0, flow proceeds to block 1322 to preserve the address. Conversely, if it is determined at decision block 1320 that IBSR: rad=0, flow proceeds to decision block 1324.
At decision block 1324, the CPU may determine whether the answer flag bit (IBSR: ACKF) is 0. If it is determined at decision block 1324 that IBSR: ACKF is not 0, flow proceeds to decision block 1342 to determine whether to perform a repeat start. Conversely, if at decision block 1324 it is determined that IBSR: ackf=0, flow proceeds to decision block 1326. At decision block 1326, the CPU may determine whether the data direction bit (IBSR: TRX) is 1. If it is determined at decision block 1326 that IBSR: TRX is not 1, then flow proceeds to decision block 1332 to determine whether the repeat start condition flag (BS: FBB) is 0. Conversely, if it is determined at decision block 1326 that IBSR: trx=0, flow proceeds to decision block 1328.
At decision block 1328, the CPU may determine whether the transmission is complete. If it is determined at decision block 1328 that the transmission is not complete, flow proceeds to decision block 1342 to determine whether to perform a repeat start. Conversely, if it is determined at decision block 1328 that the transmission is complete, flow proceeds to block 1330. At block 1330, the cpu may perform write transmit data (TXDR), wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: ACKE), and/or interrupt flag clearing (BCR: intf=0). Flow may then return to decision block 1308.
At decision block 1332, the CPU may determine whether the repeat start condition bit (BS: FBB) is 0. If it is determined at decision block 1332 that the BS: FBB is not 0, then flow proceeds to decision block 1336. Conversely, if it is determined at decision block 1332 that BS: fbb=0, the CPU may read the received data (RXDR) at block 1334. At decision block 1336, the CPU may determine whether the reception is complete. If it is determined at decision block 1336 that the reception is not complete, the CPU may perform a wait setting (BCR: wtsel=1), an acknowledge ACK setting (BCR: acke=1), and/or an interrupt flag clear (BCR: intf=0) at block 1338. Flow then returns to decision block 1308. Conversely, if it is determined at decision block 1336 that reception is complete (no acknowledgement (NACK) acknowledgement), flow proceeds to block 1340.
At block 1340, the cpu may perform a wait setting (BCR: WTSEL) and/or an acknowledge ACK setting (BCR: acke=0). Flow then proceeds to decision block 1342. Referring to fig. 13 and 15, the flow of fig. 15 may proceed from circle B (1530) shown in fig. 15 to decision block 1342 shown in fig. 13. At decision block 1342, the CPU may determine whether to repeatedly start. If it is determined at decision block 1342 that no repeated startup is performed, flow proceeds to block 1346. At block 1346, the cpu may perform a stop setting (BCR: mss=0), an acknowledge ACK setting (BCR: ACKE), and/or an interrupt flag clear (BCR: intf=0). Then, the flow ends. Conversely, if it is determined at decision block 1342 that a repeat start is performed, flow proceeds to block 1344. At block 1344, the cpu may perform writing of transmit data, repeated start settings (BCR: mss=ofits=1), acknowledgement ACK settings (BCR: ACKE), and/or interrupt flag clearing (BCR: intf=0). Flow then returns to decision block 1308.
FIG. 14 shows I in accordance with another embodiment of the invention 2 An example of an operational flow. The CPU may perform I using the flow shown in FIG. 14 2 C bus operation. For example, fig. 14 may be applied to the driven mode of the CPU.
As shown in fig. 14, at block 1402, the cpu may execute a slave mode. At decision block 1404, the CPU may determine whether the reserved address detection bit (BSR: RAD) is zero. If it is determined at decision block 1404 that the BSR, RAD, is not zero, flow proceeds to decision block 1422. Conversely, if it is determined at decision block 1404 that BSR: fbb=1, flow proceeds to decision block 1406.
At decision block 1406, the CPU may determine whether the data direction bit (BSR: TRX) is equal to 0. If it is determined at decision block 1406 that the BSR is not TRX 0, flow proceeds to decision block 1414. Conversely, if it is determined at decision block 1406 that BSR: trx=0, flow proceeds to decision block 1408.
At decision block 1408, the CPU may determine whether the repeat start condition flag (BSR: FBB) is 0, and if at decision block 1408 it is determined that BSR: FBB is not 0, flow proceeds to block 1412. Conversely, if it is determined at decision block 1408 that BSR: fbb=0, flow proceeds to block 1410 to read the received data in the received data register (RXDR). Flow then proceeds to block 1412. At block 1412, the cpu may perform a wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: ACKE), and/or clear the interrupt flag (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
At decision block 1414, the CPU may determine whether the answer flag bit (BSR: ACKF) is 0. If it is determined at decision block 1414 that the BSR: ACKF is not 0, flow proceeds to block 1418. At block 1418, the cpu may execute an interrupt flag clear (BCR: intf=0). Then, the flow ends. Conversely, if it is determined at decision block 1414 that BSR: ackf=0, flow proceeds to block 1416. At block 1416, the cpu may write execution transmit data (transmit data register (TXDR)), wait setting (BCR: WTSEL), and/or interrupt flag clear (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
At decision block 1422, the CPU may determine whether the repeat start condition flag (BSR: FBB) is 1, and if it is determined at decision block 1422 that BSR: FBB is not 1, flow proceeds to decision block 1426. In contrast, if it is determined at decision block 1422 that BSR: fbb=1, flow proceeds to block 1424 to read the received data in the received data register (RXDR). Flow then proceeds to decision block 1426.
At decision block 1426, the CPU may determine whether to perform a slave operation. If it is determined at decision block 1426 that no driven operation is to be performed, flow proceeds to block 1430 to perform an acknowledge ACK setting (BCR: acke=0) and/or interrupt flag clearing (BCR: intf=0). Then, the flow ends. Conversely, if it is determined at decision block 1426 that a driven operation is performed, flow proceeds to decision block 1428.
At decision block 1428, the CPU may determine whether the data direction bit (BSR: TRX) is 1. If it is determined at decision block 1428 that the BSR: TRX is not 1, flow proceeds to decision block 1434. Conversely, if it is determined at decision block 1428 that BSR: trx=1, flow proceeds to block 1432. At block 1432, the cpu may perform write transmit data (TXDR), wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: acke=0), and/or interrupt flag clearing (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
At decision block 1434, the CPU may determine whether the repeat start condition flag bit (BSR: FBB) is 1, and if it is determined at decision block 1434 that BSR: FBB is not 1, flow proceeds to block 1436 to read the received data in the received data register (RXDR). Conversely, if it is determined at decision block 1434 that BSR: fbb=1, flow proceeds to block 1438. At block 1438, the cpu may perform a wait setting (BCR: WTSEL), an acknowledge ACK setting (BCR: acke=1), and/or an interrupt flag clear (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
FIG. 15 shows I in accordance with another embodiment of the invention 2 An example of an operational flow. The CPU may perform I using the flow shown in FIG. 15 2 C bus operation. For example, fig. 15 may be applicable to a reserved address operation.
As shown in fig. 15, at block 1502, the cpu may perform a reserved address operation. At decision block 1504, the CPU may determine whether the repeat start condition flag (BSR: FBB) is 1. If it is determined at decision block 1504 that the BSR is not 1, flow proceeds to decision block 1512. Conversely, if it is determined at decision block 1504 that BSR: fbb=1, flow proceeds to decision block 1506.
At decision block 1506, the CPU may determine whether there are multiple master CPUs. If it is determined at decision block 1506 that there are not multiple master CPUs, then flow proceeds to block 1510. At block 1510, the cpu may perform read receive data (RXDR), wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: ACKE), and/or interrupt flag clearing (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13. Conversely, if it is determined at decision block 1506 that there are multiple master CPUs, then flow proceeds to block 1508. At block 1508, the cpu may perform reading the received data (RXDR), waiting for a setting (BCR: WTSEL), acknowledge an ACK setting (BCR: acke=1), and/or clearing an interrupt flag (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
At decision block 1512, the CPU may determine whether the data direction bit (BSR: TRX) is 1. If it is determined at decision block 1512 that the BSR is not TRX 1, flow proceeds to block 1524. Conversely, if it is determined at decision block 1512 that BSR: trx=1, flow proceeds to decision block 1514.
At decision block 1514, the CPU may determine whether the received data full flag (SSR: RDFF) is 1, and if it is determined at decision block 1514 that SSR: RDFF is not 1, flow proceeds to decision block 1518. In contrast, if it is determined at decision block 1514 that BSR rdff=1, flow proceeds to block 1516. At decision block 1516, the CPU may read the received data. Then, the flow proceeds to a decision block 1518.
At decision block 1518, the CPU may determine whether the receive acknowledgement flag bit (BSR: RACK) is 0. If it is determined at decision block 1518 that the BSR: RACK is not 0, flow proceeds to circle A (1420) to perform the corresponding operations as shown in FIG. 13. Conversely, if it is determined at decision block 1518 that BSR: rack=0, then flow proceeds to decision block 1520.
At decision block 1520, the CPU may determine whether the transmission is complete. If it is determined at decision block 1520 that the transmission is complete, then flow proceeds to circle B (1530) to perform the corresponding operations as shown in FIG. 13. Conversely, if it is determined at decision block 1518 that the transmission is not complete, flow proceeds to block 1522. At block 1522, the cpu may perform write transmit data (TXDR), wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: acke=0), and/or interrupt flag clearing (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
At block 1524, the cpu may read the received data (RXDR). Then, the flow proceeds to decision block 1526. At decision block 1526, the CPU may determine whether the transmission is complete. If it is determined at decision block 1526 that the transmission is complete (e.g., a No Acknowledgement (NACK) response is received), flow proceeds to block 1528 to perform a wait setting (BCR: WTSEL) and/or an acknowledgement ACK setting (BCR: acke=0). Then, the flow proceeds to circle B (1530) to perform the corresponding operations as shown in fig. 13. Conversely, if it is determined at decision block 1526 that the transmission is not complete, flow proceeds to block 1532 to perform a wait setting (BCR: wtsel=1), an acknowledge ACK setting (BCR: acke=1), and/or an interrupt flag clear (BCR: intf=0). Then, the flow proceeds to circle a (1420) to perform the corresponding operation as shown in fig. 13.
The flow chart of FIGS. 13-15 shows I 2 Examples of operation settings in the C-mode, in other embodiments, error handling, etc. may be considered in conjunction with appropriate application needs.
According to an embodiment of the present invention, the multifunctional serial communication interface 100 may enable UART, SPI and I to be integrated 2 The C serial communication shares the same control logic and register settings. UART, SPI and I can be used at the same time 2 And C, a serial port communication mode, so that serial port communication setting of the chip is more flexible.

Claims (11)

1. A dedicated baud rate generator, characterized in that said dedicated baud rate generator comprises:
a baud rate generator register for setting a reload value corresponding to a baud rate corresponding to a current communication protocol according to the baud rate;
a reload counter for dividing the frequency of the clock corresponding to the current communication protocol according to the reload value to obtain the special baud rate corresponding to the current communication protocol;
a first multiplexer for multiplexing an external clock and/or a system clock according to a counter external clock selection bit set in the baud rate generator register and selectively transmitting to the reload counter;
a first baud rate count comparator for comparing the baud rate comparator count value with the 1/2 baud rate coefficient to generate a first comparison value;
a second baud rate count comparator for comparing the baud rate comparator count value with 0 to generate a second comparison value and/or returning a reload baud rate coefficient value to the reload counter;
a controller for making the transmission clock when the first comparison value indicates that the baud rate comparator count value is equal to 1/2 baud rate coefficientAccording to the frequency division clock of the reloading value, when the second comparison value indicates that the counted value of the baud rate comparator is equal to 0, the transmission clock is enabled to be equal to the serial clock inversion bit;
A second multiplexer for multiplexing the transmission clock and/or the system clock from the controller to provide a clock corresponding to the current communication protocol.
2. The dedicated baud rate generator of claim 1, wherein said reload counter divides a clock corresponding to a current communication protocol according to said dedicated baud rate.
3. As claimed in claim 1 or 2Is characterized in that the current communication protocol comprises UART protocol, SPI protocol and I 2 One of the C protocols.
4. The special baud rate generator according to claim 3, characterized in that said baud rate generator register is adapted to set said reload value corresponding to a baud rate obtained by dividing an internal clock according to a UART communication protocol, said reload value being adapted to obtain a special baud rate corresponding to said UART communication protocol according to said reload value and to divide said internal clock according to said special baud rate, and/or said baud rate generator register is adapted to set said reload value corresponding to a baud rate obtained by dividing an external clock according to a UART communication protocol, said reload value being adapted to obtain a special baud rate corresponding to said UART communication protocol according to said reload value and to divide said external clock according to said special baud rate, and/or said baud rate generator register is adapted to set said special baud rate corresponding to said internal clock frequency division according to an SPI communication protocol, said reload value being adapted to obtain said special baud rate corresponding to said special baud rate according to said UART communication protocol, said reload value being adapted to said special baud rate, said special baud rate generator is adapted to said special baud rate obtained by dividing an internal clock according to said UART communication protocol, and/or said baud rate is adapted to said special baud rate generator is adapted to set said special baud rate according to an SPI communication protocol 2 The C communication protocol corresponds to the baud rate obtained by dividing the internal clock, and the reload counter is used for obtaining the corresponding I according to the reload value 2 And C, the special baud rate of the communication protocol, and dividing the frequency of the internal clock according to the special baud rate.
5. The special baud rate generator of claim 4, wherein said baud rate generator is configured to divide a clock corresponding to said current communication protocol according to said special baud rate to obtain a serial clock frequency.
6. A method, the method comprising:
setting a reload value corresponding to the baud rate according to the baud rate corresponding to the current communication protocol; and
dividing the clock corresponding to the current communication protocol according to the reload value to obtain a special baud rate corresponding to the current communication protocol, wherein the step of setting the reload value comprises:
setting the reload value, the reload value corresponding to a baud rate obtained by dividing an internal clock according to a UART communication protocol, and obtaining a dedicated baud rate corresponding to the UART communication protocol according to the reload value, and dividing the internal clock according to the dedicated baud rate; or setting the reload value corresponding to a baud rate obtained by dividing an external clock according to a UART communication protocol, and obtaining a dedicated baud rate corresponding to the UART communication protocol according to the reload value, and dividing the external clock according to the dedicated baud rate;
Setting the reload value corresponding to a baud rate obtained by dividing an internal clock according to an SPI communication protocol in a host operation mode, obtaining a dedicated baud rate corresponding to the SPI communication protocol according to the reload value, and dividing the internal clock according to the dedicated baud rate; or (b)
In a slave mode of operation of the SPI communication protocol, disabling the dedicated baud rate, or setting the reload value, which reload value is equal to the value according to I 2 The protocol C corresponds to the baud rate obtained by dividing the internal clock; and obtaining a value corresponding to the I according to the reload value 2 The special baud rate of the communication protocol is C, the internal clock is divided according to the special baud rate, or the clock corresponding to the current communication protocol is divided according to the special baud rate, so that the serial clock frequency is obtained;
multiplexing the external clock and/or the system clock according to the counter external clock selection bit;
comparing the baud rate comparator count value with the 1/2 baud rate coefficient to generate a first comparison value;
comparing the baud rate comparator count value with 0 to generate a second comparison value; returning the reload baud rate coefficient value to a reload counter;
When the first comparison value indicates that the baud rate comparator count value is equal to 1/2 baud rate coefficient, the transmission clock is enabledAccording to the frequency division clock of the reloading value and/or when the second comparison value indicates that the baud rate comparator count value is equal to 0, making the transmission clock equal to the serial clock inversion bit;
the transmit clock and/or the system clock are multiplexed to provide a clock corresponding to the current communication protocol.
7. The method of claim 6, wherein the current communication protocol includes UART protocol, SPI protocol, and I 2 One of the C protocols.
8. A communication method employing the method of claim 6, comprising setting an interface mode in a slave Central Processing Unit (CPU) consistent with a master CPU based on a current communication protocol; receiving data from the main control CPU; and sending response data to the main control CPU.
9. The communication method of claim 8, wherein:
the current communication protocol comprises a UART protocol, and the interface mode comprises a UART interface mode; and/or
The current communication protocol includes an SPI protocol, and the interface mode includes an SPI interface mode.
10. The communication method according to claim 8 or 9, wherein the slave CPU determines whether to receive the data from the master CPU based on a determination of a flag bit, and reads and processes the data in response to the determination of the receipt of the data based on the flag bit.
11. The communication method as set forth in claim 10, further comprising:
the main input and the auxiliary output pins of the driven CPU are set to be serial data input, 7 or 8 is set to be a data bit, and 1 or 2 is set to be a stop bit; and/or
Enabling the receiving and transmitting operations of the slave CPU; and/or receiving address data from a master CPU, initiating communication with the master CPU by determining that an address in the address data is the same as an assigned address of the slave CPU; and/or setting a master output slave input pin of the slave CPU as serial data output in response to determining that an address in the address data is the same as an allocated address of the slave CPU; and/or further comprising communicating with the master CPU using the master output slave input pins.
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