CN111707908B - Multi-load loop series fault arc detection method and device and storage medium - Google Patents
Multi-load loop series fault arc detection method and device and storage medium Download PDFInfo
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- G01R31/081—Locating faults in cables, transmission lines, or networks according to type of conductors
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Abstract
The application discloses a method and a device for detecting multi-load loop series fault arc and a storage medium, wherein the method for detecting the multi-load loop series fault arc comprises the following steps: collecting main circuit current signals in a multi-load circuit; performing wavelet transformation on the main circuit current signal to obtain a wavelet coefficient; processing the wavelet coefficient to obtain at least two fault indication characteristics; wherein the fault indication characteristic satisfies: when a fault arc is generated, the fault indication characteristic is not interfered by a non-fault branch circuit and can be used for judging whether the fault branch circuit has a fault or not; and if the at least two fault indication characteristics meet the preset judgment condition, judging that the fault electric arc occurs in the multi-load loop. The method and the device aim to solve the problem that in the prior art, only fault arcs in a single load loop can be detected, but fault arc detection cannot be carried out on multiple load loops.
Description
Technical Field
The invention relates to the field of arc detection, in particular to a method and a device for detecting arc of series fault of a multi-load loop and a storage medium.
Background
Arcing is a luminous discharge through an insulating medium, usually accompanied by partial volatilization of the electrodes, while a fault arc is an "unintentional arcing condition in the circuit". The core temperature of the arc is as high as 5000K to 15000K, which is highly likely to cause a fire if there is flammable material around it.
In a power distribution system of a family residence, an office building, a large market and the like, due to the reasons of wire aging, poor contact and the like, series fault arcs often occur, and then an electrical fire is caused, so that inestimable loss is brought to a user. Currently, the research on series fault arcs mostly focuses on a certain single load loop. However, in a real power network, the lines are very complicated, the loads are diversified, some lines are even very hidden, and it is difficult to ensure that a fault arc detector is installed in each load loop.
In addition, when a fault arc occurs on a branch circuit, especially when the load power of the circuit is relatively small, the fault current is not obviously changed, and the current distortion caused by the fault arc is easily submerged by the large current and background noise of other circuits, which greatly increases the difficulty of detecting the fault arc.
Disclosure of Invention
The embodiment of the application aims to solve the problem that only fault arcs in a single load loop can be detected but fault arc detection cannot be performed on multiple load loops in the prior art by providing a method, a device and a storage medium for detecting fault arcs in series connection of multiple load loops.
The embodiment of the application provides a method for detecting a multi-load loop series fault arc, which comprises the following steps:
collecting main circuit current signals in a multi-load circuit;
performing wavelet transformation on the main circuit current signal to obtain a wavelet coefficient;
processing the wavelet coefficient to obtain at least two fault indication characteristics; wherein the fault indication characteristic satisfies: when a fault arc is generated, the fault indication characteristic is not interfered by a non-fault branch circuit and can be used for judging whether the fault branch circuit has a fault or not;
and if the at least two fault indication characteristics meet the preset judgment condition, judging that the fault electric arc occurs in the multi-load loop.
In some embodiments, a neural network model is used to determine whether the at least two fault indication features satisfy a preset determination condition; wherein the neural network model takes the at least two fault indication features as input and takes whether an arc fault occurs as output.
In some embodiments, the method further comprises the step of training the neural network model, including:
building a multi-load loop series fault arc simulation model;
generating training data according to an application scene based on the multi-load loop series fault arc simulation model; the characteristics contained in the training data correspond to the at least two fault indication characteristics and are provided with corresponding fault labels;
and training the neural network model by adopting the training data.
In some embodiments, the step of performing wavelet transform on the main current signal to obtain wavelet coefficients includes:
performing four-layer decomposition on the main line current signal by using a db4 wavelet function in a multi-besy wavelet series as a basis function to obtain wavelet coefficients of each layer, wherein in some embodiments, the processing the wavelet coefficients to obtain at least two fault indication features includes:
computing
Obtaining the first fault indication characteristic, calculating
Determining a second fault indication characteristic, where xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In some embodiments, the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Calculating the first fault indication characteristic to calculate sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficient, σiIs the standard deviation of the wavelet coefficients.
In some embodiments, the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Calculating a second fault indication characteristic, and calculating sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In some embodiments, the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Obtaining the first fault indication characteristic, calculating
Calculating a second fault indication characteristic, and calculating sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
The present application further provides a series fault arc detection apparatus, which includes a current detection apparatus, a processor communicatively coupled to the current detection apparatus, a memory, and a series fault arc detection program stored on the memory and operable on the processor, wherein the series fault arc detection program implements the steps of the multi-load-loop series fault arc detection method when executed by the processor.
The present application also contemplates a computer readable storage medium having one or more programs stored thereon that are executable by one or more processors to implement the steps in the multi-load loop series fault arc detection method.
According to the method and the device, the trunk circuit current of the multi-load circuit is collected, wavelet transformation is carried out on the trunk circuit current, a wavelet coefficient is obtained, the wavelet coefficient is processed to obtain at least two fault indication characteristics, the fault indication characteristics are not interfered by non-fault branches, so that interference of other high-power branch circuit currents in the multi-load circuit can be avoided, whether at least two fault indication characteristics meet preset judgment conditions is tested, and a detection result is obtained. The present application thus more reliably extracts and identifies series fault arcs occurring in any branch from the main circuit current of the multi-load circuit. The embodiment can overcome the defect that the existing method can only detect the fault electric arc for a single load loop, is suitable for being placed at the power distribution inlet wire of a household residence, an office building and a large-scale market power utilization network with complex circuits and diversified or even concealed circuits, does not need to configure a fault electric arc detector for each load in the circuits, plays a role in saving the cost of the fault electric arc detector, and can effectively prevent the occurrence of fire caused by the fault electric arc.
Drawings
FIG. 1 is a schematic hardware configuration diagram of an embodiment of a series fault arc detection apparatus according to the present application;
FIG. 2 is a block flow diagram of a first embodiment of a multi-load loop series fault arc detection method of the present application;
FIG. 3 is a schematic structural diagram of a multi-load loop series fault arc simulation model constructed in a simulation platform MATLAD;
FIG. 4 is a graph showing a first layer of wavelet coefficients of the main circuit current when the circuit of FIG. 3 is connected to different numbers of loads;
FIG. 5 is a block flow diagram of at least two fault indication features of a first embodiment of a multi-load-loop series fault arc detection method of the present application being a first fault indication feature and a second fault indication feature;
FIG. 6 is a graph showing a comparison of a first fault indication characteristic in wavelet coefficients of each layer with normal parameters in a normal state after four-layer wavelet decomposition is performed on a trunk current with a db4 wavelet function as a basis function when a faulty arc is generated;
FIG. 7 is a graph showing a comparison of a second fault indication characteristic in wavelet coefficients of each layer with normal parameters in a normal state after four-layer wavelet decomposition is performed on a trunk current with a db4 wavelet function as a basis function when a faulty arc is generated;
FIG. 8 is a block flow diagram of a second embodiment of a multi-load loop series fault arc detection method of the present application;
FIG. 9 is a diagram showing a comparison of a third fault indication characteristic in wavelet coefficients of each layer with normal parameters in a normal state after four-layer wavelet decomposition is performed on a main circuit current by using a db4 wavelet function as a basis function when a fault arc is generated;
FIG. 10 is a block flow diagram of a third embodiment of a multiple load loop series fault arc detection method of the present application;
fig. 11 is a block flow diagram of a fourth embodiment of a multiple load loop series fault arc detection method according to the present application.
Detailed Description
For a better understanding of the above technical solutions, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In a power distribution system of a family residence, an office building, a large market and the like, due to the reasons of wire aging, poor contact and the like, series fault arcs often occur, and then an electrical fire is caused, so that inestimable loss is brought to a user. Currently, the research on series fault arcs focuses on a certain single load loop. However, in a real power network, the lines are very complicated, the loads are diversified, some lines are even very hidden, and it is difficult to ensure that a fault arc detector is installed in each load loop. Therefore, fault arc detectors are often placed at the customer electrical distribution inlet.
When a fault arc occurs on a branch circuit, especially when the load power of the circuit is relatively small, the fault current does not change obviously, and the current distortion caused by the fault arc is easily submerged by the large current and background noise of other circuits, which greatly increases the difficulty of detecting the fault arc. Therefore, when a series fault arc occurs, how to identify the fault signal from the current signal measured at the power distribution inlet becomes the key to the fault arc detection technique. In view of the above, the present application provides a method, an apparatus and a storage medium for detecting a series fault arc in a multi-load loop.
Referring to fig. 1, an embodiment of the present application provides a series fault arc detection apparatus, including: a current detection device 104, a processor 101, a memory 102, and a communication bus 103. Wherein a communication bus 103 is used for enabling the connection communication between these components.
The current detection device 104 is arranged on a trunk of the multi-load loop and used for collecting current of the trunk. The current detecting device 104 may be any of various commercially available ac current detecting devices.
The processor 101 may be a Central Processing Unit (CPU), which may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 102 may be a high-speed RAM memory or a non-volatile memory (e.g., a disk memory). As shown in fig. 1, a series fault arc detection program may be included in memory 103 as a type of computer storage medium; and processor 101 may be configured to invoke a series fault arc detection program stored in memory 102 and perform the following operations:
in one embodiment, the processor 101 may be configured to invoke a series fault arc detection program stored in the memory 102 and perform the following operations:
judging whether the at least two fault indication characteristics meet preset judgment conditions or not by adopting a neural network model; wherein the neural network model takes the at least two fault indication features as input and takes whether an arc fault occurs as output.
In one embodiment, the processor 101 may be configured to invoke a series fault arc detection program stored in the memory 102 and perform the following operations:
the method also comprises a step of training to obtain the neural network model, which comprises the following steps: building a multi-load loop series fault arc simulation model; based on the simulation model, carrying out simulation according to an application scene and acquiring training data; the training data comprises characteristics corresponding to the at least two fault indication characteristics and corresponding fault labels; and training the neural network model by adopting the training data.
In one embodiment, the processor 101 may be configured to invoke a series fault arc detection program stored in the memory 102 and perform the following operations:
the step of performing wavelet transform on the main circuit current signal to obtain a wavelet coefficient comprises the following steps:
performing four-layer decomposition on the main current signal by using a db4 wavelet function in the multi-bayesian wavelet series as a basis function to obtain wavelet coefficients of each layer in an embodiment, the processor 101 may be configured to call a series fault arc detection program stored in the memory 102, and perform the following operations:
the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Obtaining the first fault indication characteristic, calculating
Determining a second fault indication characteristic, where xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In one embodiment, the processor 101 may be configured to invoke a series fault arc detection program stored in the memory 102 and perform the following operations:
the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Calculating the first fault indication characteristic to calculate sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In one embodiment, the processor 101 may be configured to invoke a series fault arc detection program stored in the memory 102 and perform the following operations: the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Calculating a second fault indication characteristic, and calculating sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In one embodiment, the processor 101 may be configured to invoke a series fault arc detection program stored in the memory 102 and perform the following operations: the step of processing the wavelet coefficients to obtain at least two fault indication features comprises:
computing
Obtaining the first fault indication characteristic, calculating
Calculating a second fault indication characteristic, and calculating sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is smallMean value of wave coefficient, σiIs the standard deviation of the wavelet coefficients.
In the embodiment, the trunk current of the multi-load loop is collected, the trunk current is subjected to wavelet transformation to obtain a wavelet coefficient, the wavelet coefficient is processed to obtain at least two fault indication characteristics, and the fault indication characteristics are not interfered by non-fault branches, so that the interference of other high-power branch currents in the multi-load loop can be avoided, and whether the at least two fault indication characteristics meet the preset judgment condition is tested, so that the detection result is obtained. The present application thus more reliably extracts and identifies series fault arcs occurring in any branch from the main circuit current of the multi-load circuit. The embodiment can overcome the defect that the existing method can only detect the fault electric arc for a single load loop, is suitable for being placed at the power distribution inlet wire of a household residence, an office building and a large-scale market power utilization network with complex circuits and diversified or even concealed circuits, does not need to configure a fault electric arc detector for each load in the circuits, plays a role in saving the cost of the fault electric arc detector, and can effectively prevent the occurrence of fire caused by the fault electric arc.
Based on the hardware architecture of the series fault arc detection device, the embodiment of the multi-load-loop series fault arc detection method is provided.
Referring to fig. 2, fig. 2 is a first embodiment of the multiple-load-loop series fault arc detection method according to the present application, where the multiple-load-loop series fault arc detection method includes the following steps:
s110, collecting main circuit current signals in a multi-load circuit;
the main circuit current is detected by arranging the current detection device 104 in the main circuit of the multi-load circuit, and in practical application, the current detection device 104 is usually arranged at a power distribution inlet wire of a user to realize the detection of the main circuit current. It should be noted that, since the relationship between the loads of a plurality of multi-load circuits is parallel, the term "main circuit" herein refers to a circuit of the overlapped part of the circuits through which all the load currents pass. In other words, a circuit directly connected to the power supply.
S120, performing wavelet transformation on the main circuit current signal to obtain a wavelet coefficient;
as described in the background art, the lines in the real environment are very complex and the loads are diversified, when a fault arc occurs on a certain line loop, especially when the load power of the loop is relatively small, the fault current change is not obvious, and the current distortion caused by the fault arc is easily submerged by the large current and background noise of other loops, which results in an increase in the difficulty of detecting the fault arc. It is therefore desirable to find a "relative stability quantity" that is not affected by the branch circuits of the multi-load circuit, which is the basis for fault arc determination. By utilizing MATLAD to carry out fault arc simulation on a multi-load loop, the applicant finds that the wavelet coefficient of the main circuit current is basically not influenced by other high-power branch circuit currents. Therefore, in the application, the main circuit current signal is subjected to wavelet transformation, a wavelet coefficient is obtained, and then subsequent fault arc judgment is carried out.
Specifically, four-layer decomposition is performed on the main circuit current signal by taking a db4 wavelet function in a multi-Behcet wavelet series as a basis function, and wavelet coefficients of each layer are obtained. The applicant finds out in multiple experiments that when the basic function of the wavelet transform is db4 wavelet function and four-layer decomposition is performed, the wavelet coefficient which is not interfered by other load branches and can obviously distinguish the fault state from the normal state can be obtained, so that db4 wavelet function is selected as the basic function in the application to perform four-layer wavelet transform on the main line current.
Referring to fig. 3, a plurality of different loads (i.e., resistive loads, resistive-inductive loads, and resistive-capacitive loads in the figure) are built in a simulation platform MATLAD and connected in parallel to form a multi-load loop, a fault arc generation module is connected to any one of the loads, the fault arc generation module is used for generating a fault arc, and a current detection device is arranged on a trunk line to detect a trunk line current. The resistive load refers to a single resistive load, the resistive-inductive load refers to a combined load formed by serially connecting a resistor and an inductor, and the resistive-capacitive load refers to a combined load formed by serially connecting a resistor and a capacitor. Fig. 4 shows the case of the first layer wavelet coefficients of the mains current when the circuit in fig. 3 is connected to different numbers of loads. For example, when only one resistive load exists in the circuit, the arc generation module and the resistive load are connected in series to form a single load loop; on the basis of the single load loop, a resistance-inductance load is connected in parallel to form a double load loop; on the basis of the double-load loop, a resistance-capacitance load is connected in parallel to form a three-load loop; the composition principle of the multi-load circuit with more than three load circuits can be analogized.
As can be seen from fig. 4, the waveform of the wavelet coefficients of the single-load loop is nearly the same as the waveform of the wavelet coefficients of the dual-load loop and the waveform of the wavelet coefficients of the triple-load loop. That is, the wavelet coefficient obtained by wavelet transforming the main line current is not affected by the number of loads connected in parallel in practice, that is, the wavelet coefficient of the main line current is not affected by other high-power branch currents (i.e., non-fault branches) basically. Therefore, the wavelet coefficient of the main circuit current can be used as the research basis of the fault arc.
Under the condition of finding the wavelet coefficient which is not influenced by other high-power branch current in the multi-load circuit, the fault indication characteristic for distinguishing the fault arc generation state from the normal state is found through the wavelet coefficient, so that the judgment basis for judging whether the fault arc occurs in the circuit can be obtained, and the fault arc judgment in the multi-load circuit is realized.
S130, processing the wavelet coefficient to obtain at least two fault indication characteristics; wherein the fault indication characteristic satisfies: when a fault arc is generated, the fault indication feature is not interfered by a non-fault branch circuit and can be used for judging whether the fault branch circuit has a fault or not.
It should be noted that, since the wavelet coefficient is not affected by the currents of other high-power branches, the fault indication characteristic obtained by the wavelet coefficient is not necessarily affected by the currents of other high-power branches (non-fault branches). It will be understood that the above-mentioned "not influenced" does not absolutely have any influence, but means that the influence is of a very slight degree, essentially negligible.
In this embodiment, referring to fig. 5, the wavelet coefficients are processed to obtainThe step of characterizing at least two faults includes: s131, calculating
Obtaining the first fault indication characteristic, calculating
Determining a second fault indication characteristic, where xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients. It is worth mentioning that the first fault indication feature is referred to as kurtosis in the time domain analysis. In the embodiment, a kurtosis concept in a time domain method is introduced, the time domain method is organically combined with a time-frequency method based on wavelet transformation, the kurtosis of wavelet coefficients of each layer of a main circuit current signal is obtained, and the kurtosis of the wavelet coefficients is used as a fault parameter for distinguishing a fault arc generation state from a normal state.
Specifically, referring to fig. 6, fig. 6 is a diagram showing a comparison between the first fault indication characteristic in the wavelet coefficient of each layer and the normal parameter in the normal state after four-layer wavelet decomposition is performed on the main circuit current by using db4 wavelet function as the basis function when the fault arc is generated. Wherein the abscissa represents the experimental group and the ordinate represents the numerical value of the first fault indication feature. a1 shows a comparison of the first failure indication characteristic of the first layer wavelet coefficients with normal parameters in the normal state, and the meanings of a2 to a4 can be analogized.
By observing fig. 6, it can be found that, when a fault arc is generated, after four-layer wavelet decomposition is performed on the main circuit current by taking a db4 wavelet function as a basis function, the first fault indication feature in each layer of wavelet coefficient is obviously different from a normal parameter, and further observation can find that the numerical values of the first fault indication feature obtained from the first layer wavelet coefficient to the fourth layer of wavelet coefficient are all above 10, and the normal parameter is all near 0.
It should be noted that, because the first fault indication feature of the first layer wavelet coefficient has strong volatility and is not stable enough, in practice, the first fault indication features of the second layer wavelet coefficient to the fourth layer wavelet coefficient may be obtained to perform the fault arc verification. It can be understood that the first failure indication features of any one of the second-layer wavelet coefficients to the fourth-layer wavelet coefficients may be obtained, or the first failure indication features of any two layers of the first failure indication features of any one of the second-layer wavelet coefficients to the fourth-layer wavelet coefficients may be obtained, and the more the first failure indication features of the number of layers where the wavelet coefficients are located are obtained, the more sufficient and more convincing the verification of the experimental result.
In addition, calculate
Determining a second fault indication characteristic, where xiAnd N is the number of wavelet coefficients. In the embodiment, a second fault indication characteristic which is approximate to the peak factor in the time domain in the wavelet coefficient is constructed by referring to the concept of the peak factor in the time domain, and the second fault indication characteristic is adopted as a fault parameter for distinguishing a fault arc generation state from a normal state.
Specifically, referring to fig. 7, fig. 7 is a diagram showing a comparison between the second fault indication characteristic in the wavelet coefficient of each layer and the normal parameter in the normal state after four-layer wavelet decomposition is performed on the main circuit current by using db4 wavelet function as the basis function when the fault arc is generated. Wherein the abscissa represents the experimental group and the ordinate represents the numerical value of the second fault indication characteristic. a1 shows a comparison of the second failure indication characteristic of the first layer wavelet coefficients with normal parameters in the normal state, and the meanings of a2 to a4 can be analogized.
By observing fig. 7, it can be found that, when a fault arc is generated, after four-layer wavelet decomposition is performed on the main circuit current by taking the db4 wavelet function as the basis function, the second fault indication characteristic in each layer of wavelet coefficient has a significant difference from the normal parameter, and further, by observing that the numerical values of the second fault indication characteristic obtained from the first layer wavelet coefficient to the fourth layer of wavelet coefficient are all above 10, and the normal parameters are all in the interval of [0, 10 ].
Similarly, because the second fault indication characteristic of the first layer wavelet coefficient has stronger volatility and is not stable enough, in practice, the second fault indication characteristics of the second layer wavelet coefficient to the fourth layer wavelet coefficient can be obtained for fault arc verification. It can be understood that the second failure indication features of any one of the second-layer wavelet coefficients to the fourth-layer wavelet coefficients may be obtained, or the second failure indication features of any two layers of the second-layer wavelet coefficients to the fourth-layer wavelet coefficients may be obtained, and the more the second failure indication features of the wavelet coefficients of each layer of the trunk circuit current are obtained, the more sufficient and more convincing the verification of the experimental result.
And S140, if the at least two fault indication characteristics meet the preset judgment condition, judging that the fault electric arc occurs in the multi-load loop.
In this embodiment, a neural network model is adopted to determine whether the at least two fault indication features satisfy a preset determination condition; wherein the neural network model takes the first fault indication characteristic and the second fault indication characteristic as input and takes whether fault electric arc is generated as output.
Further, this embodiment further includes a step of training to obtain the neural network model, which includes: building a multi-load loop series fault arc simulation model; generating training data according to an application scene based on the multi-load loop series fault arc simulation model; the training data comprises characteristics corresponding to the at least two fault indication characteristics and corresponding fault labels; and training the neural network model by adopting the training data. It will be appreciated that the multi-load circuit model is built in the step of building the circuit model. And inputting fault arc data and normal data, calibrating the fault arc data and the normal data, and obtaining more reliable training data through a large amount of iterative operations. And the features included in the training data correspond to the at least two fault indication features and have corresponding fault labels.
For example, in some embodiments, after the training of the neural network model, the training data of the first fault feature is 10, the training data of the second fault feature is 10, when the input first fault feature is greater than or equal to 10 and the second fault feature is greater than or equal to 10, it is determined that the fault arc is generated, and the neural network model outputs a signal for generating the fault arc.
Thus, the first fault indication characteristic and the second fault indication characteristic are input into the neural network model, and the neural network model can obtain an output signal for generating a fault arc and inform the detected multi-loop load of the fault arc.
In addition, the reliability of the detection result can be improved by obtaining the first fault indication characteristic and the second fault indication characteristic as a double-characteristic combination and inputting the double-characteristic combination into the neural network for detection.
It should be noted that the detection of the series fault arc in the multi-load circuit can be achieved by using a single first fault indication feature or a single second fault indication feature. In the embodiment, the first fault indication characteristic and the second fault indication characteristic are combined to detect the multi-load circuit series fault arc, so that the accuracy and the reliability of the multi-load circuit fault arc detection are improved.
In the embodiment, the trunk current of the multi-load loop is collected, the wavelet transform is performed on the trunk current to obtain the wavelet coefficient, the wavelet coefficient is processed to obtain at least two fault indication characteristics, and the fault indication characteristics are not interfered by non-fault branches, so that the interference of currents of other high-power branches in the multi-load loop can be avoided, and whether the at least two fault indication characteristics meet the preset judgment condition or not is tested, so that the detection result is obtained. The present application thus more reliably extracts and identifies series fault arcs occurring in any branch from the main circuit of the multi-load circuit. The embodiment can overcome the defect that the existing method can only detect the fault electric arc for a single load loop, is suitable for being placed at the power distribution inlet wire of a household residence, an office building and a large-scale market power utilization network with complex circuits and diversified or even concealed circuits, does not need to configure a fault electric arc detector for each load in the circuits, plays a role in saving the cost of the fault electric arc detector, and can effectively prevent the occurrence of fire caused by the fault electric arc.
Referring to fig. 8, fig. 8 is a second embodiment of the multi-load circuit series fault arc detection method of the present application, which includes the following steps:
s210, collecting main circuit current signals in a multi-load circuit;
s220, performing wavelet transformation on the main circuit current signal to obtain a wavelet coefficient;
s230, calculating
Calculating the first fault indication characteristic to calculate sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
Specifically, referring to fig. 9, fig. 9 is a diagram showing a comparison between the third fault indication characteristic in the wavelet coefficient of each layer and the normal parameter in the normal state after four-layer wavelet decomposition is performed on the main circuit current by using db4 wavelet function as the basis function when the fault arc is generated. Wherein the abscissa represents the experimental group and the ordinate represents the numerical value of the third fault indication characteristic. a1 shows a comparison of the third failure indication characteristic of the first layer wavelet coefficients with the normal parameters in the normal state, and the meanings of a2 to a4 can be analogized.
By observing fig. 9, it can be found that, when a fault arc is generated, after four-layer wavelet decomposition is performed on the main circuit current by using a db4 wavelet function as a basis function, the third fault indication characteristic in each layer of wavelet coefficient is obviously different from the normal parameter, and further, by observing that the numerical values of the third fault indication characteristic obtained from the first-layer wavelet coefficient to the fourth-layer wavelet coefficient are all below 9, and the normal parameter is all around 10.
It should be noted that, because the third fault indication characteristic of the first-layer wavelet coefficient has strong volatility and is not stable enough, in practice, the third fault indication characteristics of the second-layer wavelet coefficient to the fourth-layer wavelet coefficient can be obtained to verify the fault arc. It can be understood that the third failure indication feature of any one of the second-layer wavelet coefficient to the fourth-layer wavelet coefficient may be obtained, or the third failure indication features of any two layers of the third failure indication features of any one of the second-layer wavelet coefficient to the fourth-layer wavelet coefficient may be obtained, and the more the third failure indication features of the layer number where the wavelet coefficient is located are obtained, the more sufficient and more convincing the verification of the experimental result.
S240, if the first fault indication characteristic and the third fault indication characteristic meet a preset judgment condition, judging that the fault arc occurs in the multi-load loop.
In this embodiment, a neural network model is adopted to determine whether the at least two fault indication features satisfy a preset determination condition; wherein the neural network model takes the first fault indication characteristic and the third fault indication characteristic as input and takes whether fault electric arc is generated as output.
For example, in some embodiments, after the training of the neural network model, the training data of the first fault feature is 10, the training data of the third fault indication feature is 9, when the input first fault feature is greater than or equal to 10 and the third fault feature is less than or equal to 9, it is determined that the fault arc is generated, and the neural network model outputs a signal for generating the fault arc.
In the embodiment, the reliability of the detection result can be improved by obtaining the first fault indication characteristic and the third fault indication characteristic and inputting the first fault indication characteristic and the third fault indication characteristic into the neural network as the double-characteristic combination for detection.
In the embodiment, the trunk current of the multi-load loop is collected, the trunk current is subjected to wavelet transformation to obtain a wavelet coefficient, the wavelet coefficient is processed to obtain at least two fault indication characteristics, and the fault indication characteristics are not interfered by non-fault branches, so that the interference of other high-power branch currents in the multi-load loop can be avoided, and whether the at least two fault indication characteristics meet the preset judgment condition is tested, so that the detection result is obtained. The present application thus more reliably extracts and identifies series fault arcs occurring in any branch from the main circuit current of the multi-load circuit. The embodiment can overcome the defect that the existing method can only detect the fault electric arc for a single load loop, is suitable for being placed at the power distribution inlet wire of a household residence, an office building and a large-scale market power utilization network with complex circuits and diversified or even concealed circuits, does not need to configure a fault electric arc detector for each load in the circuits, plays a role in saving the cost of the fault electric arc detector, and can effectively prevent the occurrence of fire caused by the fault electric arc.
Referring to fig. 10, fig. 10 is a third embodiment of the multi-load circuit series fault arc detection method of the present application, which includes the following steps:
s310, collecting main circuit current signals in a multi-load circuit;
s320, performing wavelet transformation on the main circuit current signal to obtain a wavelet coefficient;
s330, calculating
Calculating a second fault indication characteristic, and calculating sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In the embodiment, the second fault indication feature and the third fault indication feature are used as a dual-feature combination, and referring to fig. 7 and 9, when a fault arc is generated, after four-layer wavelet decomposition is performed on the trunk current by using a db4 wavelet function as a basis function, the second fault indication feature and the third fault indication feature in wavelet coefficients of each layer are obviously different from normal parameters. By using the second fault indication characteristic and the third fault indication characteristic as a dual-characteristic combined input neural network for detection, the reliability of the detection result can be improved.
And S340, if the second fault indication characteristic and the third fault indication characteristic meet a preset judgment condition, judging that the fault arc occurs in the multi-load loop.
In the embodiment, the trunk current of the multi-load loop is collected, the trunk current is subjected to wavelet transformation to obtain a wavelet coefficient, the wavelet coefficient is processed to obtain at least two fault indication characteristics, and the fault indication characteristics are not interfered by non-fault branches, so that the interference of other high-power branch currents in the multi-load loop can be avoided, and whether the at least two fault indication characteristics meet the preset judgment condition is tested, so that the detection result is obtained. The present application thus more reliably extracts and identifies series fault arcs occurring in any branch from the main circuit current of the multi-load circuit. The embodiment can overcome the defect that the existing method can only detect the fault electric arc for a single load loop, is suitable for being placed at the power distribution inlet wire of a household residence, an office building and a large-scale market power utilization network with complex circuits and diversified or even concealed circuits, does not need to configure a fault electric arc detector for each load in the circuits, plays a role in saving the cost of the fault electric arc detector, and can effectively prevent the occurrence of fire caused by the fault electric arc.
Referring to fig. 11, fig. 11 is a fourth embodiment of the multi-load circuit series fault arc detection method of the present application, which includes the following steps:
s410, collecting main circuit current signals in a multi-load circuit;
s420, performing wavelet transformation on the main circuit current signal to obtain a wavelet coefficient;
s430, calculating
Obtaining the first fault indication characteristic, calculating
Calculating a second fault indication characteristic, and calculating sigma PilogPiObtaining a third fault indication characteristic, wherein
E(i)＝(|xi|)2，xiRepresenting wavelet coefficients, N being the number of wavelet coefficients,
is the mean value of the wavelet coefficients, σiIs the standard deviation of the wavelet coefficients.
In the present embodiment, the first fault indication feature, the second fault indication feature, and the third fault indication feature are used as a combination of three features, and referring to fig. 6, fig. 7, and fig. 9, when a fault arc is generated, after four-layer wavelet decomposition is performed on a trunk current by using a multiple-bayesian wavelet function as a basis function, there is a significant difference between the first fault indication feature, the second fault indication feature, and the third fault indication feature in each layer of wavelet coefficient and a normal parameter. By using the first fault indication feature, the second fault indication feature and the third fault indication feature as three feature combinations and inputting the three feature combinations into the neural network for detection, the reliability of the detection result is further improved compared with the use of double feature combinations.
And S440, if the first fault indication characteristic, the second fault indication characteristic and the third fault indication characteristic meet preset judgment conditions, judging that the fault electric arc occurs in the multi-load loop.
In the embodiment, the trunk current of the multi-load loop is collected, the trunk current is subjected to wavelet transformation to obtain a wavelet coefficient, the wavelet coefficient is processed to obtain at least two fault indication characteristics, and the fault indication characteristics are not interfered by non-fault branches, so that the interference of other high-power branch currents in the multi-load loop can be avoided, and whether the at least two fault indication characteristics meet the preset judgment condition is tested, so that the detection result is obtained. The present application thus more reliably extracts and identifies series fault arcs occurring in any branch from the main circuit current of the multi-load circuit. The embodiment can overcome the defect that the existing method can only detect the fault electric arc for a single load loop, is suitable for being placed at the power distribution inlet wire of a household residence, an office building and a large-scale market power utilization network with complex circuits and diversified or even concealed circuits, does not need to configure a fault electric arc detector for each load in the circuits, plays a role in saving the cost of the fault electric arc detector, and can effectively prevent the occurrence of fire caused by the fault electric arc.
The present application also contemplates a computer readable storage medium having one or more programs stored thereon that are executable by one or more processors to implement the steps in the multi-load loop series fault arc detection method.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A multi-load loop series fault arc detection method, comprising:
collecting main circuit current signals in a multi-load circuit;
performing four-layer decomposition on the main circuit current signal by taking a db4 wavelet function in a multi-Behcet wavelet series as a basis function to obtain wavelet coefficients of each layer;
processing the wavelet coefficient to obtain at least two fault indication characteristics; wherein the fault indication features comprise at least a first fault indication feature, a second fault indication feature, and a third fault indication feature; the first fault indication characteristic is calculated by
The second fault indication characteristic is calculated by
The third fault indication characteristic is calculated by
Wherein
，
，
The wavelet coefficients are represented by a number of wavelet coefficients,n is the number of wavelet coefficients,
is the average value of the wavelet coefficients and,
is the standard deviation of the wavelet coefficients; wherein the fault indication characteristic satisfies: when a fault arc is generated, the fault indication characteristic is not interfered by a non-fault branch circuit and can be used for judging whether the fault branch circuit has a fault or not;
and if the at least two fault indication characteristics meet the preset judgment condition, judging that the fault electric arc occurs in the multi-load loop.
2. The multi-load loop series fault arc detection method of claim 1, wherein a neural network model is used to determine whether the at least two fault indication features satisfy a preset determination condition; wherein the neural network model takes the at least two fault indication features as input and takes whether an arc fault occurs as output.
3. The method of claim 2, further comprising the step of training the neural network model to obtain the fault arc detection, including:
building a multi-load loop series fault arc simulation model;
generating training data according to an application scene based on the multi-load loop series fault arc simulation model; the training data comprises characteristics corresponding to the at least two fault indication characteristics and corresponding fault labels;
and training the neural network model by adopting the training data.
4. The multi-load loop series fault arc detection method according to claim 1, wherein the step of processing the wavelet coefficients to obtain at least two fault indication features specifically comprises:
computing
Obtaining the first fault indication characteristic, calculating
Obtaining a second fault indication characteristic, wherein
Representing wavelet coefficients, N being the number of wavelet coefficients,
is the average value of the wavelet coefficients and,
is the standard deviation of the wavelet coefficients.
5. The multi-load loop series fault arc detection method according to claim 1, wherein the step of processing the wavelet coefficients to obtain at least two fault indication features specifically comprises:
computing
Obtaining the first fault indication characteristic, calculating
Obtaining a third fault indication characteristic, wherein
，
，
Representing wavelet coefficients, N being the number of wavelet coefficients,
is the average value of the wavelet coefficients and,
is the standard deviation of the wavelet coefficients.
6. The multi-load loop series fault arc detection method according to claim 1, wherein the step of processing the wavelet coefficients to obtain at least two fault indication features specifically comprises:
computing
Obtaining a second fault indication characteristic, calculating
Obtaining a third fault indication characteristic, wherein
，
，
Representing wavelet coefficients, N being the number of wavelet coefficients,
is the average value of the wavelet coefficients and,
is the standard deviation of the wavelet coefficients.
7. The multi-load loop series fault arc detection method according to claim 1, wherein processing the wavelet coefficients to obtain at least two fault indication features specifically is:
computing
Obtaining the first fault indication characteristic, calculating
Obtaining a second fault indication characteristic, calculating
Obtaining a third fault indication characteristic, wherein
，
，
Representing wavelet coefficients, N being the number of wavelet coefficients,
is the average value of the wavelet coefficients and,
is the standard deviation of the wavelet coefficients.
8. A series fault arc detection apparatus, comprising a current detection apparatus, a processor communicatively connected to the current detection apparatus, a memory, and a series fault arc detection program stored on the memory and executable on the processor, the series fault arc detection program when executed by the processor implementing the steps of the multi-load loop series fault arc detection method of any of claims 1 to 7.
9. A computer readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to perform the steps in the multi-load loop series fault arc detection method as claimed in any one of claims 1 to 7.
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| CN113311227B (en) * | 2021-06-10 | 2022-06-24 | 中国科学技术大学先进技术研究院 | Current signal noise reduction method for fault arc diagnosis technology |
| CN113514724A (en) * | 2021-07-15 | 2021-10-19 | 阳光电源股份有限公司 | Photovoltaic system and arc detection method and device thereof |
| CN113468704B (en) * | 2021-07-23 | 2024-02-02 | 南方电网科学研究院有限责任公司 | Intermittent arc fault detection method and related device |
| CN114236203B (en) * | 2021-11-29 | 2023-10-24 | 国网北京市电力公司 | Load control system, method, storage medium and electronic device |
| CN115616364B (en) * | 2022-12-16 | 2023-03-17 | 中国科学技术大学先进技术研究院 | Fault arc detection method, device, equipment and storage medium |
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