CN111704105B - Preparation method of semiconductor/superconductor heterojunction nanowire network - Google Patents
Preparation method of semiconductor/superconductor heterojunction nanowire network Download PDFInfo
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- CN111704105B CN111704105B CN202010583153.9A CN202010583153A CN111704105B CN 111704105 B CN111704105 B CN 111704105B CN 202010583153 A CN202010583153 A CN 202010583153A CN 111704105 B CN111704105 B CN 111704105B
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Abstract
The invention provides a preparation method of a semiconductor/superconductor heterojunction nanowire network. The preparation method comprises the steps of preparing a vertical semiconductor nano sheet on a first substrate; in-situ extending a superconductor on the semiconductor nanosheet to obtain the superconductor-extended semiconductor nanosheet; transferring the superconductor-extended semiconductor nanosheets to a second substrate; and processing the superconductor in situ epitaxy on the semiconductor nano-chip into a nanowire network by utilizing micro-nano processing to obtain the semiconductor/superconductor heterojunction nanowire network.
Description
Technical Field
The invention relates to a semiconductor material preparation technology, in particular to a preparation method of a semiconductor/superconductor heterojunction nanowire network.
Background
Fault-tolerant topological quantum computing based on Majorana fermi is a scheme proposed and approved in recent years to solve the problem of quantum computer error correction, and the detection and finding of Majorana fermi is the key for fault-tolerant topological quantum computing. The Sarma group of university of maryland [ phys.rev.lett., 104(2010)040502] and the Oreg group of the weizmann institute of science [ phys.rev.lett., 105(2010)077001] theoretically predict: in a strong magnetic field, a superconductor and a narrow bandgap semiconductor (InAs or InSb) nanowire are used for forming a P-wave superconducting chain, and due to the close proximity effect of the superconductor, an effective P-wave pairing mechanism can be formed on the nanowire, and Majorana binding states exist at two ends of the nanowire. Experimentally, the Kouwenhoven professor group of Delov's science realizes a hard superconducting energy gap in an InSb/Al nanowire system for the first time, and particularly observes a quantized conductance platform. And a solid foundation is laid for the topological quantum computation based on the narrow-bandgap semiconductor/superconductor nanowire system.
The Majorana fermi is protected by the system topology and is therefore robust against environmental disturbances. With the Majorana fermi that satisfies non-abelian exchange statistics, a logical operation, i.e., a weaving operation, may be implemented by exchanging the positions of two Majorana fermi. However, single nanowire devices are not suitable for performing the braiding operation. Recently, theoretical results show that the braiding operation can be realized on the narrow-bandgap semiconductor/superconductor heterojunction nanowire network.
At present, two methods are mainly used for preparing the narrow bandgap semiconductor/superconductor heterojunction nanowire network. The first method is a bottom-up method, namely: the narrow-band gap semiconductor nanowire network is grown by a bottom-up method, and then a superconductor is extended on the narrow-band gap semiconductor nanowire network in an epitaxial mode, so that the narrow-band gap semiconductor/superconductor heterojunction nanowire network is obtained. For example, Bakkers professor of dalton theory of dalf theory, utilizes MOCVD to prepare InSb nanowire networks by adjusting the growth position and direction of nanowires. Later, in cooperation with the subject of professor Palmstrom of division of Palmstrom in Santa Bombara, California, Al [ Nature 548(2017)434] was epitaxially grown on the InSb nanowire network by using MBE technology, and an InSb/Al heterojunction nanowire network was obtained. In the preparation method of the heterojunction nanowire network, the yield of the cross structure depends heavily on the treatment process of the substrate and the position control of the catalyst lattice. The second method is a top-down selective area epitaxy method, namely: the narrow-band gap semiconductor nanowire network is extended in a plane selection area on a III-V group semiconductor substrate by utilizing micro-nano processing, and then a superconductor is extended on the narrow-band gap semiconductor nanowire network, so that the narrow-band gap semiconductor/superconductor heterojunction nanowire network is obtained. For example, professor Krogstrup and co-workers at copenhagen university prepared InSb/a1 heterojunction nanowire networks [ phys. rev. lett., 121(2018)147701] on InP substrates using MBE selective area epitaxy. Bakkers professor group of Dawlett packard university prepared InSb/Al heterojunction nanowire networks on InP substrates by MOCVD selective zone epitaxy [ Communication Physics, 3(2020)59 ]. In the process of preparing planar InAs and InSb nanowire networks by using selective epitaxy, because of great lattice mismatch between InAs and InSb nanowires and III-V group semiconductor substrates, a great amount of stacking faults and twin crystal defects appear in the InAs and InSb nanowire networks, and finally a high-quality semiconductor/superconductor heterojunction interface is difficult to obtain.
Therefore, exploring new ways to prepare high-quality narrow-bandgap semiconductor/superconductor heterojunction nanowire networks for developing scalable multiple-topology qubit bearing systems is an important issue that needs to be solved in the current system topology quantum computing.
Disclosure of Invention
Technical problem to be solved
In view of the difficulty in obtaining a high-quality semiconductor/superconductor heterojunction nanowire network by the conventional preparation method, the invention provides the preparation method of the semiconductor/superconductor heterojunction nanowire network, and the high-quality semiconductor/superconductor heterojunction nanowire network can be obtained.
(II) technical scheme
In order to achieve the above object, the present invention provides a method for preparing a semiconductor/superconductor heterojunction nanowire network, comprising: preparing a vertical semiconductor nano sheet on a first substrate;
in-situ extending a superconductor on the semiconductor nanosheet to obtain a superconductor-extended semiconductor nanosheet; transferring the superconductor-extended semiconductor nanoplatelets to a second substrate; and processing the superconductor in situ epitaxy on the semiconductor nano-chip into a nanowire network by utilizing micro-nano processing to obtain the semiconductor/superconductor heterojunction nanowire network.
Optionally, the vertical type includes one of the semiconductor nanoplate being perpendicular or tilted to the first substrate.
Optionally, the in-situ epitaxy includes epitaxy of the superconductor on the surface of the semiconductor nanosheet under a preset vacuum condition.
Optionally, the transferring comprises one of dry transferring or wet transferring.
Optionally, the preparation method of the semiconductor nanosheet includes performing epitaxy on the first substrate and performing epitaxy on the first substrate in an axial direction of the one-dimensional semiconductor nanowire by adopting a source-changing growth process.
Optionally, the material of the first substrate or the second substrate includes one of a semiconductor, a metal, and an oxide.
Optionally, the material of the semiconductor nanoplatelets comprises a compound semiconductor.
Optionally, the material of the superconductor comprises one of an elemental superconductor, an alloy superconductor, a compound superconductor.
Optionally, the thickness of the semiconductor nanosheet is on the order of hundreds of nanometers or less, and the length and width are on the order of nanometers to micrometers and more.
Optionally, the superconducting nanowire network has a thickness below the order of hundreds of nanometers and a length and width on the order of nanometers to micrometers.
Optionally, the semiconductor nanoplatelets comprise group III-V semiconductor nanoplatelets, and the method of making the group III-V semiconductor nanoplatelets and the superconductor comprises one of molecular beam epitaxy, metalorganic chemical vapor deposition, or chemical beam epitaxy.
Optionally, the micro-nano processing includes electron beam exposure, lithography, and etching.
(III) advantageous effects
(1) In the preparation method, the semiconductor/superconductor heterojunction interface can reach atomic level flatness, and the semiconductor/superconductor heterojunction nanowire network also has the advantages of high crystal quality, good size controllability, easy material stripping and transferring from the substrate and easy subsequent device processing.
(2) In the process of processing the superconductor into the nanowire network by utilizing micro-nano processing, the size and the shape of the nanowire network can be changed by changing micro-nano processing technological parameters according to actual requirements, and the difficulty that the size and the shape of the nanowire network are difficult to change by utilizing a traditional selective area epitaxy mode can be overcome.
(3) The method is easy to realize the mass production of the vertical semiconductor/superconductor heterojunction nanowire network, and can greatly save the material and device processing cost.
Drawings
Fig. 1 schematically shows a flow diagram of a method of preparing a semiconductor/superconductor heterojunction nanowire network according to an embodiment of the invention.
Fig. 2 schematically illustrates a schematic view of the vertical positional relationship of a first substrate and a semiconductor nanoplate according to an embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
Fig. 1 schematically shows a flow diagram of a method of preparing a semiconductor/superconductor heterojunction nanowire network according to an embodiment of the invention. The semiconductor/superconductor heterojunction is formed by combining two different materials, namely a semiconductor and a superconductor, and forming a heterojunction at the interface.
As shown in fig. 1, the method for preparing the semiconductor/superconductor heterojunction nanowire network may include the following operations (a) to (d).
(a) A vertical semiconductor nanosheet 11 is prepared on a first substrate 10.
According to an embodiment of the present invention, the material of the first substrate 10 includes, but is not limited to, a semiconductor (e.g., Si, GaAs), a metal (e.g., Mo), an oxide (e.g., SiO)x) (ii) a The material of the semiconductor nanosheet 11 includes, but is not limited to, a compound semiconductor (e.g., InAs, GaAs, InP, GaP, InSb, or GaSb).
According to the embodiment of the invention, the semiconductor nanosheet 11 is prepared by means of, but not limited to, epitaxy directly on the first substrate 10 and epitaxial growth on the first substrate 10 in the axial direction of the one-dimensional semiconductor nanowire by using a source-changing growth process.
According to the embodiment of the present invention, the thickness of the semiconductor nanosheet 11 may be on the order of, without limitation, a few nanometers to a hundred nanometers, and the length and width may be on the order of, without limitation, micrometers and above nanometers.
According to the embodiment of the present invention, the vertical type may be a vertical positional relationship of the semiconductor nano-sheet 11 and the first substrate 10 as in fig. 2 or an inclined positional relationship of the semiconductor nano-sheet 11 and the first substrate 10 as in (a) in fig. 1. The vertical semiconductor nanosheet has the advantages that the semiconductor/superconductor heterojunction nanowire network prepared subsequently is enabled to be very easy to peel off and transfer from the substrate, and the difficulty in subsequent device processing is greatly reduced.
(b) And (3) in-situ extending the superconductor 12 on the semiconductor nanosheet 11 to obtain the semiconductor nanosheet 11 with the superconductor 12 extended.
According to the embodiment of the invention, in-situ epitaxy refers to the epitaxy of the superconductor 12 on the surface of the semiconductor nanosheet 11 under a preset vacuum condition. For example, the pressure of the predetermined vacuum condition may be 1X 10-6Pa. The superconductor 12 is in-situ epitaxial on the vertical semiconductor nanosheet 11, which is a precondition and basis for preparing a high-quality semiconductor/superconductor heterojunction nanowire network with a flat interface atomic level; and the stress caused by the lattice mismatch of the semiconductor/superconductor can be effectively released, so that a high-quality heterojunction sample is obtained. Because the semiconductor/superconductor heterojunction is obtained by adopting an in-situ epitaxial mode, the interface of the heterojunction can reach the level of atoms.
According to embodiments of the present invention, the material of superconductor 12 includes, without limitation, elemental superconductors, alloy superconductors, and compound superconductors.
According to embodiments of the present invention, methods of preparing group III-V semiconductor nanoplates 11 and superconductors 12 include, without limitation, molecular beam epitaxy, metalorganic chemical vapor deposition, or chemical beam epitaxy.
(c) The semiconductor nanoplatelets 11, to which the superconductors 12 are epitaxial, are transferred onto a second substrate 13.
According to an embodiment of the present invention, the material of the second substrate 13 includes, but is not limited to, semiconductors (e.g., Si, GaAs), metals (e.g., Mo), oxides (e.g., SiO)x) The second substrate 13 may be used as a back gate for a device in subsequent device processing.
According to embodiments of the present invention, the manner of transfer includes, but is not limited to, dry transfer and wet transfer. Wherein, dry transfer refers to transfer in which the sample is not in contact with any liquid during transfer; wet transfer refers to transfer in which a sample is dispersed in a solution and then the sample is dispersed on a substrate.
(d) And processing the superconductor 12 extending in situ on the semiconductor nanosheet 11 into a nanowire network 14 by micro-nano processing to obtain the semiconductor/superconductor heterojunction nanowire network.
According to embodiments of the present invention, micro-nano processing includes, but is not limited to, electron beam exposure, lithography, etching, and the like. In the process of processing the superconductor 12 in situ epitaxy on the semiconductor nanosheet 11 into the nanowire network 14, the size and the shape of the nanowire network can be changed by changing micro-nano processing technological parameters according to actual needs, and the difficulty that the size and the shape of the nanowire network are difficult to change by using a traditional selective area epitaxy mode can be overcome.
According to embodiments of the present invention, the thickness of superconducting nanowire network 14 may be on the order of, without limitation, a few nanometers to a hundred nanometers, and the length and width may be on the order of, without limitation, nanometers to micrometers.
Fig. 2 schematically illustrates a schematic view of the vertical positional relationship of a first substrate and a semiconductor nanoplate according to an embodiment of the present invention. In the position relationship, the description of the steps of the preparation method of the semiconductor/superconductor heterojunction nanowire network may refer to the description in fig. 1, and will not be repeated herein.
While specific embodiments are provided in accordance with the embodiments of the present invention, it should be noted that the description of these specific embodiments is merely exemplary and is not intended to limit the scope of the invention.
For example, a method for preparing an InSb/Al heterojunction nanowire network includes the following operations (1) to (4).
(1) InAs nanowires are grown on a Si (111) substrate by utilizing molecular beam epitaxy equipment and Ag as a catalyst. The InAs nanowire growth temperature is 380-530 ℃, and the As/In beam current ratio is 30-50. The diameter of the InAs nanowire is from several nanometers to about 100 nanometers; and finishing the growth of the InAs nanowire, setting the substrate temperature to be 480-520 ℃, and setting the Sb/In beam current ratio to be 20-80. Switching an As source to an Sb source, and growing InSb nanosheets in the axial direction of the InAs nanowire.
(2) And after the growth of the InSb nanosheets is finished, reducing the temperature of the substrate to 77-273K, and carrying out in-situ epitaxy on the InSb nanosheets to obtain InSb/Al heterojunction nanosheets.
(3) InSb/A1 heterojunction nanosheets transferred to Si/SiO by dry transfer2On a substrate.
(4) And processing the in-situ epitaxial Al on the InSb nano-chip into a nano-wire network by utilizing micro-nano processing, wherein the size and the number of the nano-wire network can be adjusted through the technological parameters of electron beam exposure, so that the InSb/Al heterojunction nano-wire network is obtained.
The above-mentioned preparation method and specific embodiment of the semiconductor/superconductor heterojunction nanowire network further describe the objects, technical solutions and beneficial effects of the present invention in detail, it should be understood that the above-mentioned preparation method and specific embodiment of the present invention do not limit the present invention, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A preparation method of a semiconductor/superconductor heterojunction nanowire network is applied to topological quantum computation, and comprises the following steps:
preparing a vertical semiconductor nanosheet on a first substrate, wherein the vertical type comprises one of the semiconductor nanosheet being perpendicular to or inclined to the first substrate;
in-situ extending a superconductor on the semiconductor nanosheet to obtain a superconductor-extended semiconductor nanosheet, wherein the semiconductor nanosheet is a narrow bandgap semiconductor nanosheet;
transferring the superconductor-extended semiconductor nanoplatelets to a second substrate;
and processing the superconductor in situ epitaxy on the semiconductor nano-chip into a nanowire network by utilizing micro-nano processing to obtain the narrow-bandgap semiconductor/superconductor heterojunction nanowire network, wherein the narrow-bandgap semiconductor/superconductor heterojunction nanowire network is used for developing a plurality of extensible topological qubits.
2. The production method according to claim 1, wherein:
the in-situ epitaxy comprises the step of carrying out epitaxy on the superconductor on the surface of the semiconductor nanosheet under the preset vacuum condition.
3. The production method according to claim 1, wherein:
the transfer includes one of dry transfer or wet transfer.
4. The production method according to claim 1, wherein:
the preparation method of the semiconductor nano sheet comprises the steps of extending on the first substrate and extending on the first substrate in the axial direction of the one-dimensional semiconductor nano line by adopting a source-changing growth process.
5. The production method according to claim 1, wherein:
the material of the first substrate or the second substrate comprises one of a semiconductor, a metal and an oxide;
the material of the semiconductor nanosheet comprises a compound semiconductor;
the material of the superconductor comprises one of an element superconductor, an alloy superconductor and a compound superconductor.
6. The production method according to claim 1, wherein:
the thickness of the semiconductor nano sheet is below hundred nanometers, and the length and the width of the semiconductor nano sheet are from nanometer to micrometer and above.
7. The production method according to claim 1, wherein:
the thickness of the superconducting nanowire network is below hundred nanometers, and the length and the width of the superconducting nanowire network are in nanometer to micrometer magnitude.
8. The production method according to claim 1, wherein:
the semiconductor nanoplates comprise group III-V semiconductor nanoplates, and methods of making the group III-V semiconductor nanoplates and the superconductor comprise one of molecular beam epitaxy, metalorganic chemical vapor deposition, or chemical beam epitaxy.
9. The production method according to claim 1, wherein:
the micro-nano processing comprises electron beam exposure, photoetching and corrosion.
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