CN111682006A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN111682006A CN111682006A CN202010658821.XA CN202010658821A CN111682006A CN 111682006 A CN111682006 A CN 111682006A CN 202010658821 A CN202010658821 A CN 202010658821A CN 111682006 A CN111682006 A CN 111682006A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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Abstract
The invention belongs to the technical field of semiconductor packaging, and discloses a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure comprises: a semiconductor substrate provided with a chip pad; the polymer bump layer is formed on the chip welding pad, and a plurality of through holes capable of exposing the chip welding pad are formed in the polymer bump layer; the metal bonding layer is formed on the polymer bump layer and comprises a plurality of columnar bodies positioned on the inner side of the through hole and connected to the chip welding pad and a plane part connected with the columnar bodies and positioned at the top of the polymer bump layer; a solder bump connected to the planar portion of the metal adhesive layer; in conclusion, the distance between the electrode terminal and the metal bonding layer can be effectively reduced based on the arrangement of the polymer bump layer, and micro-space connection is realized; this shortens the moving distance of the electric signal and reduces the size of the semiconductor package, which is advantageous for the high-speed and small-sized semiconductor chip.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.
Background
Generally, in a semiconductor package manufactured by wire bonding, since electrode terminals of a printed circuit board and pads of a semiconductor chip are electrically connected by conductive wires, the size of the semiconductor package is larger than that of the semiconductor chip, and a wire bonding process takes a long time and is limited in miniaturization and mass production. Currently, with the high integration, high performance, and high speed of the semiconductor chip, various methods are being tried to realize the miniaturization and mass production of the semiconductor package. For example, a semiconductor package in which electrical connection is directly made between a semiconductor chip pad and an electrode terminal of a printed circuit board by a solder material or a metal solder bump formed on the semiconductor chip pad.
The semiconductor package using the solder bumps is typically a Flip Chip Ball Grid Array (FCBGA) or a wafer level chip size/scale package (WLCSP) type; a typical semiconductor package using the metal solder bump is a chip on glass/tape carrier package.
The flip chip ball grid array approach electrically connects the solder bumps contacting the pads on the semiconductor chip to the pads on the substrate and performs underfill to protect the solder bumps from environmental or mechanical problems. Solder balls are attached to the back surface of the substrate, which is in contact with the semiconductor chip, and the solder balls are electrically connected to electrode terminals on the printed circuit board. Wafer level chip scale/scale packaging, for the sake of product light weight, thin and short, through rewiring and metal solder bump, can realize the same package size as chip size.
In the chip on glass method, a metal solder bump is formed on a pad of a semiconductor chip, and an electrode terminal of a printed circuit board and a polymer containing anisotropic conductive particles are thermally pressed and cured as a medium, so that the semiconductor chip pad and the electrode terminal of the printed circuit board are electrically connected through the metal solder bump.
Fig. 1 and 2 are cross-sectional views of a conventional semiconductor package, which, according to the drawings, includes: a semiconductor chip 20 provided with a chip pad 10; a protective film 30 formed on the surface of the semiconductor chip 20 to selectively expose the chip pads; a metal adhesive layer 50 formed on the upper portion of the chip pad 10 and extending from the upper portion of the chip pad 10 to the upper portion of the protective film 30 around the chip pad 10; a metal solder bump 60 formed on the upper portion of the metal adhesive layer 50; and a printed circuit board 80 provided with electrode terminals 70 in contact with the surface of the metal solder bump 60.
As described above, after the wafer-level chip scale package re-wiring process, the metal solder bumps 60 are formed, and then the electrode terminals 70 of the printed circuit board 80 and the metal solder bumps 60 are aligned and electrically connected by heating.
Compared with the semiconductor package manufactured by the traditional wire bonding mode, the mode can shorten the moving distance of an electric signal, is favorable for high speed, can reduce the size of the semiconductor package and is favorable for miniaturization of products. On the other hand, the above-described semiconductor chip 20 may apply a semiconductor process, and thus, the pitches between the chip pads 10 and between the metal solder bumps 60 may be minimized.
However, the above-described printed circuit board 80 cannot apply a semiconductor process, and thus has a limitation in reducing the pitch between the wiring and the electrode terminal 70. Also, for the multi-functionality of the chip, the pitch between adjacent metal solder bumps 60 tends to decrease with the increase of the number of leads in the same area.
Further, the thermal expansion coefficients of the metal solder bump 60 and the electrode terminal 70 are thus different, so that the stress to which the metal solder bump 60 is subjected is increased; at the same time, intermetallic compounds are generated between the metal solder bump 60 and the metal adhesive layer 50, which lowers the bonding reliability of the package.
Disclosure of Invention
In view of the above, the present invention is directed to a semiconductor package and a method for fabricating the same.
In order to achieve the purpose, the invention provides the following technical scheme:
a semiconductor package structure, comprising:
a semiconductor substrate provided with a chip pad;
the polymer bump layer is formed on the chip welding pad, and a plurality of through holes capable of exposing the chip welding pad are formed in the polymer bump layer;
the metal bonding layer is formed on the polymer bump layer and comprises a plurality of columnar bodies positioned on the inner side of the through hole and connected to the chip welding pad, and a plane part connected with the plurality of columnar bodies and positioned at the top of the polymer bump layer;
and the welding lug is connected with the plane part of the metal bonding layer.
Preferably, the semiconductor package structure further includes a porous protection film formed on the semiconductor substrate, the protection film is used for partially covering the chip bonding pad, and the holes of the protection film correspond to the through holes one to one. Specifically, the aperture of the protective film is not smaller than the aperture of the through hole.
Preferably, the metal adhesion layer is characterized in that:
at least comprises a single-layer structure;
the thickness is 100 Å -20000 Å;
the material is at least one of titanium or titanium alloy, nickel or nickel alloy, copper or copper alloy, chromium or chromium alloy, gold or gold alloy, and aluminum or aluminum alloy with good wet performance.
Preferably, the polymer bump layer is characterized in that:
is prepared by mixing organic materials and inorganic materials; wherein the organic material comprises photosensitive or non-photosensitive polyimide, benzocyclobutene, epoxy resin and silicon resin;
is made of a material with a dielectric constant larger than 1.
Preferably, the columnar body is characterized in that:
the device comprises a first cylinder and second cylinders, wherein the first cylinder is formed in the middle, the second cylinders are uniformly distributed around the first cylinder in an annular array mode, and the diameter of each second cylinder is smaller than that of each first cylinder.
The manufacturing method of the semiconductor package structure as disclosed above includes the following steps:
s1, forming a chip welding pad on the surface of a semiconductor substrate based on rewiring, forming a protective film on the upper portion of the chip welding pad, and etching the protective film to enable the chip welding pad to be partially exposed;
s2, coating the upper parts of the chip welding pad and the protective film formed in the step S1 to form a photosensitive or non-photosensitive polymer bump layer, and forming a through hole corresponding to the etching part of the protective film in the chip welding pad and the protective film; after the macromolecule bump layer is formed, ashing the macromolecule bump layer to remove residues of the macromolecule bump layer;
s3, coating and forming a metal bonding layer on the surface of the macromolecule bump layer, the upper part of the protective film and the upper part of the chip welding pad, and depositing the thickness of the metal bonding layer to 100 Å -20000 Å through sputtering, thermal deposition or electron beam deposition;
s4, coating a light resistor on the upper part of the metal bonding layer, and carrying out local exposure through a light shield which is selectively transparent/shading to photoetch a welding lug forming area; after local exposure, developing the photoresist to expose the metal bonding layer;
s5, ashing the developing area to remove the photoresist residues;
s6, forming a metal bump on the exposed metal bonding layer after the photoresist is developed by an electroplating or electroless plating method, and forming a welding bump on the metal bump, wherein the metal bump comprises a plurality of columnar bodies connected with a chip welding pad and a plane part connected with the welding bump;
and S7, removing the photosensitive photoresist, and etching the metal bonding layer by using the welding lug as a mask to obtain the complete semiconductor packaging structure.
Compared with the prior art, the invention has the following beneficial effects:
(1) based on the arrangement of the polymer bump layer, the distance between the electrode terminal and the metal bonding layer can be effectively reduced, so that the effect of micro-space connection is achieved; this shortens the moving distance of the electric signal, which is advantageous for speeding up the semiconductor chip, and also reduces the size of the semiconductor package, which is advantageous for downsizing the semiconductor product. In addition, the macromolecule bump layer can buffer the stress at the lower part of the welding bump, thereby improving the reliability of the package.
(2) The polymer bump layer is provided with a plurality of through holes, the metal bonding layer forms a plurality of columnar bodies in the through holes, and the upper part of the polymer bump layer forms a plane part, so that the bonding area between the metal bonding layer and a chip bonding pad can be effectively enlarged, the electrical characteristics are improved, and the deterioration caused by partial electrical stress concentration is prevented. In addition, the height of the polymer bump layer is increased to a desired height based on the arrangement of the plurality of columnar bodies, and the aspect ratio of the through holes is increased, so that the problem of circuit breaking is effectively solved.
(3) For the plurality of column bodies, a structure with a large-size column body in the middle and a small-size column body around is preferred, so when the packaging structure provided by the invention is pasted on a printed circuit board, physical and thermal shock generated by the packaging structure can be absorbed by the small-size column body, and the large-size column body is prevented from collapsing.
Drawings
FIG. 1 is a cross-sectional view of a conventional semiconductor package;
fig. 2 is a sectional view of a conventional semiconductor package structure mounted on electrode terminals of a printed circuit board;
FIG. 3 is a cross-sectional view of a semiconductor package structure according to the present invention;
fig. 4 is a sectional view of a semiconductor package structure according to the present invention mounted on electrode terminals of a printed circuit board;
FIG. 5 is a plan view of an exemplary metal adhesion layer in a semiconductor package structure provided in the present invention;
FIG. 6 is another exemplary plan view of a metal adhesion layer in a semiconductor package structure provided in the present invention;
fig. 7 is a flow chart of manufacturing the semiconductor package structure provided by the present invention.
Fig. 8 is a schematic structural diagram of the semiconductor package structure applied to a wafer level chip scale package according to the present invention.
Detailed Description
Hereinafter, preferred embodiments of the inventive concept are described in detail with reference to the accompanying drawings. However, the embodiments of the inventive concept may be modified into various forms and should not be construed as being limited to the embodiments described in detail below. It is to be understood that the embodiments of the inventive concept are provided to more fully illustrate the inventive concept to those of ordinary skill in the art. Like numbers refer to like elements throughout. Further, various elements and regions in the drawings are schematically illustrated. Accordingly, the concepts of the present invention are not limited to the relative sizes or spacings shown in the figures.
Although the terms first, second, etc. may be used to describe various constituent elements, the constituent elements are not limited to the terms. The terms are used only to distinguish one constituent element from other constituent elements. For example, a first component may be named a second component, and conversely, a second component may be named a first component, without departing from the scope of the inventive concept.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. Unless expressly stated otherwise, expressions in the singular also include expressions in the plural. In the present application, expressions "including" or "having" or the like are understood to specify the presence of the features, amounts, steps, actions, components, parts, or combinations thereof described in the specification, but do not preclude the presence or addition of one or more other features, amounts, actions, components, parts, or combinations thereof.
Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. Also, it will be understood that terms, which are commonly used and are defined in dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an excessive manner unless explicitly defined otherwise herein.
Where some embodiments may be implemented differently, the particular processes may be performed out of order from that described. For example, two processes described in succession may, in fact, be executed substantially concurrently, or the processes may be executed in the reverse order to that described.
In the drawings, the deformation of the illustrated shape can be predicted, for example, based on manufacturing techniques and/or tolerances. Therefore, the embodiments of the present invention should not be construed as being limited to the specific shapes of the regions illustrated in the present specification, and are intended to include, for example, variations in shapes that may be caused during the manufacturing process. As used herein, all "and/or" includes all combinations of one or more of the constituent elements involved. Also, the term "substrate" used in the present specification may include the substrate itself, or a stacked structure including the substrate and a predetermined layer or film or the like formed on a surface thereof. In addition, the "surface of the substrate" in the present specification may include a surface where the substrate itself is exposed, or an outer side surface of a predetermined layer, film, or the like formed on the substrate.
Referring to fig. 3-6, a semiconductor package structure according to the present invention is shown:
as shown in fig. 3 to fig. 4, which are cross-sectional views of the semiconductor package structure provided by the present invention, specifically:
the chip pad 110 and the protective film 130 are formed on the semiconductor substrate 120, wherein the protective film 130 is a porous protective film to selectively expose a portion of the chip pad 110.
A polymer bump layer 140 with a through hole 140 'is formed on the chip pad 110 and the protective film 130, and the aperture of the through hole 140' is smaller than that of the protective film 130 exposing the chip pad 110.
A metal adhesive layer 150 formed on the polymer bump layer 140 and extending from the upper portion of the chip pad 110 inside the through hole 140' to the upper portion of the passivation film 130.
Specifically, the metal adhesive layer 150 includes a plurality of columns located inside the through holes 140' and connected to the upper portion of the chip pad 110, and a plane portion connected to the plurality of columns and located on the top of the polymer bump layer 140. Based on this, the adhesion area between the metal adhesion layer 150 and the chip pad 110 can be effectively enlarged, thereby improving electrical characteristics and preventing deterioration caused by partial electrical stress concentration. In addition, the height of the polymer bump layer 140 is increased to a desired height based on the arrangement of the plurality of columns, so that the aspect ratio of the through hole 140' is increased, thereby effectively eliminating the problem of circuit disconnection.
Fig. 5 is a plan view showing an example of the metal adhesive layer 150 according to the present invention, and it can be seen that 3 columns are formed in the metal adhesive layer 150, but in actual use, the present invention is not limited thereto, and a different number of columns may be formed.
Fig. 6 is another exemplary plan view of the metal adhesive layer 150 according to the present invention, wherein a large-sized pillar located in the middle of the chip pad 110 and a small-sized pillar surrounding the large-sized pillar are formed in the metal adhesive layer 150, and for convenience of description and illustration, only 5 small-sized pillars are shown in fig. 6. Based on the structure, the structure is not only beneficial to preventing the disconnection problem and the degradation problem, but also beneficial to buffering the upper impact; that is, when the package structure provided by the present invention is attached to the printed circuit board 180, the physical and thermal shocks generated by the package structure can be absorbed by the small-sized pillar, thereby preventing the large-sized pillar from collapsing. Here, "large size" and "small size" are only relative sizes, and are not limited to specific sizes.
A solder bump 160 is formed on the upper portion of the metal adhesive layer 150, and the upper portion of the solder bump 160 is in contact with an electrode terminal 170 of the printed circuit board 180.
Specifically, when the distance between the conventional semiconductor substrate 120 and the printed circuit board 180 is used as a reference, the connection between the semiconductor substrate 120 and the printed circuit board 180 can be formed by using the smaller solder bump 160 based on the arrangement of the polymer bump layer 140, so that the distance between the electrode terminal 170 and the metal adhesive layer 150 is effectively reduced to achieve the effect of fine pitch connection. In addition, the polymer bump layer 140 may buffer stress at the lower portion of the solder bump 160, thereby improving reliability of the package.
As can be seen, compared to the conventional wire bonding type semiconductor package, the moving distance of the electrical signal is shortened, which is advantageous for high speed, and the size of the semiconductor package can be reduced, which is advantageous for miniaturization of the product.
Referring to fig. 7 (fig. 7 a-7 h), in order to implement the above-disclosed manufacturing flow chart of a semiconductor package structure, it can be seen that a method for manufacturing a semiconductor package structure includes the following steps
First, as shown in fig. 7a, a chip pad 210 is formed on a surface of a semiconductor substrate 220 by rewiring, a protective film 230 is formed on the chip pad 210, and a portion of the protective film 230 is etched to expose the chip pad 210.
Next, as shown in fig. 7b, a polymer bump layer 240, which is photosensitive or non-photosensitive, is coated on the chip pad 210 and the protective film 230, and a through hole 240' corresponding to the etched portion of the protective film 230 is formed therein; after the polymer bump layer 240 is formed, the polymer bump layer is ashed to remove the residue of the polymer bump layer 240. Based on this, the adhesion of the polymer bump layer 240 to the subsequent metal adhesion layer 250 is improved.
Then, as shown in fig. 7c, a metal adhesive layer 250 is formed on the surface of the polymer bump layer 240, the upper portion of the protective film 230 and the upper portion of the chip pad 210, and the metal adhesive layer 250 is deposited to a thickness of 100 Å -20000 Å by sputtering, thermal deposition or electron beam deposition.
The metal adhesion layer 250 is made of a material having good wettability with the polymer bump layer 240, and is specifically made of at least one material selected from titanium or a titanium alloy, chromium or a chromium alloy, nickel or a nickel alloy, copper or a copper alloy, aluminum or an aluminum alloy, gold or a gold alloy, and vanadium or a vanadium alloy, and the structure of the metal adhesion layer includes at least a single layer structure.
Then, as shown in fig. 7d, a photoresist 260 is coated on the upper portion of the metal adhesive layer 250, and local exposure is performed through a selectively transparent/opaque mask; specifically, light masks with different specifications are selected according to the type of the light resistor 260, and a metal bump 270 forming area is photoetched; after the partial exposure, the photoresist 260 is developed to expose the metal adhesive layer 250.
The developed area is ashed to remove the photoresist 260 residue.
Next, as shown in fig. 7e, a metal bump 270 is formed on the metal adhesive layer 250 exposed after the photoresist 260 is developed by electroplating or electroless plating, as shown in fig. 7f, and a solder bump 280 is formed on the metal bump 270; specifically, a plurality of columns connected to the chip pad 210 in the metal adhesive layer 250 and a plurality of flat portions connected to the solder bumps 280 are formed by the metal bumps 270.
Then, as shown in FIG. 7g, the photo resist 260 is removed, and as shown in FIG. 7h, the bonding metal layer 250 is etched using the solder bump 280 as a mask, so as to obtain a complete semiconductor package structure.
Finally, aiming at the complete semiconductor packaging structure, the mode of connecting the semiconductor packaging structure with the printed circuit board is as follows: the solder bump 280 is aligned with the electrode terminal of the printed circuit board, and the upper portion of the solder bump 280 is brought into contact with the electrode terminal of the printed circuit board by a thermocompression bonding method. The electrode terminal of the printed circuit board is press-bonded to the upper surface of the solder bump 280 at a temperature of 100 to 400 ℃. Further, by performing underfill between the semiconductor substrate 220 and the printed circuit board, contact reliability is improved.
In addition, please refer to fig. 8, which shows: the sectional view of the semiconductor packaging welding lug adopting the technology of the invention on the welding pad of the rewiring in the wafer level chip size packaging shows that the lug of the invention has smaller occupied area than the traditional lug and is beneficial to micro-space connection.
The semiconductor package manufacturing method of the present invention is described only as an example of forming the bump by the electrolytic plating method or the electroless plating method, but is not limited thereto. Further, Au stud method/steel print method, etc. can be used.
In summary, the structure of coating the upper portion of the chip pad with the photosensitive or non-photosensitive polymer bump layer to increase the stand-off of the solder bump, achieve fine pitch, and improve the adhesion reliability can be variously changed without departing from the technical idea of the present invention.
As described above, the semiconductor package bump, and the semiconductor package and manufacturing method using the same according to the present invention are implemented by coating the polymer bump layer on the upper portion of the bonding pad of the semiconductor substrate, and compared with the metal bump manufactured by the conventional technology, the semiconductor package bump improves the stand-off of the bonding bump, realizes fine pitch, and enables the semiconductor substrate to be light, thin, short, and multi-pin.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A semiconductor package structure, comprising:
a semiconductor substrate provided with a chip pad;
the polymer bump layer is formed on the chip welding pad, and a plurality of through holes capable of exposing the chip welding pad are formed in the polymer bump layer;
the metal bonding layer is formed on the polymer bump layer and comprises a plurality of columnar bodies positioned on the inner side of the through hole and connected to the chip welding pad, and a plane part connected with the plurality of columnar bodies and positioned at the top of the polymer bump layer;
and the welding lug is connected with the plane part of the metal bonding layer.
2. The semiconductor package structure of claim 1, wherein: the semiconductor packaging structure further comprises a porous protective film formed on the semiconductor substrate, the protective film is used for partially covering the chip welding pad, and the holes of the protective film correspond to the through holes one to one.
3. The semiconductor package structure of claim 2, wherein: the aperture of the protective film is not smaller than that of the through hole.
4. The semiconductor package structure of claim 1, wherein: the metal bonding layer comprises at least one single-layer structure.
5. The semiconductor package structure of claim 4, wherein: the metal bonding layer is made of metal or metal alloy, and the metal is at least one of titanium, nickel, copper, chromium, gold, aluminum, vanadium and bismuth.
6. The semiconductor package structure of claim 1, wherein: the thickness of the metal bonding layer is 100 Å -20000 Å.
7. The semiconductor package structure of claim 1, wherein: the high-molecular bump layer is prepared by mixing an organic material and an inorganic material; wherein the organic material comprises photosensitive or non-photosensitive polyimide, benzocyclobutene, epoxy resin and silicon resin.
8. The semiconductor package structure of claim 7, wherein: the polymer bump layer is made of a material with a dielectric constant larger than 1.
9. The semiconductor package structure of claim 1, wherein: the columnar body comprises a first column body formed in the middle and second column bodies uniformly distributed around the first column body in an annular array mode, and the diameter of each second column body is smaller than that of each first column body.
10. The method for manufacturing a semiconductor package structure according to any one of claims 1 to 9, comprising the steps of:
s1, forming a chip welding pad on the surface of a semiconductor substrate based on rewiring, forming a protective film on the upper portion of the chip welding pad, and etching the protective film to enable the chip welding pad to be partially exposed;
s2, coating the upper parts of the chip welding pad and the protective film formed in the step S1 to form a photosensitive or non-photosensitive polymer bump layer, and forming a through hole corresponding to the etching part of the protective film in the chip welding pad and the protective film; after the macromolecule bump layer is formed, ashing the macromolecule bump layer to remove residues of the macromolecule bump layer;
s3, coating and forming a metal bonding layer on the surface of the macromolecule bump layer, the upper part of the protective film and the upper part of the chip welding pad, and depositing the thickness of the metal bonding layer to 100 Å -20000 Å through sputtering, thermal deposition or electron beam deposition;
s4, coating a light resistor on the upper part of the metal bonding layer, and carrying out local exposure through a light shield which is selectively transparent/shading to photoetch a welding lug forming area; after local exposure, developing the photoresist to expose the metal bonding layer;
s5, ashing the developing area to remove the photoresist residues;
s6, forming a metal bump on the exposed metal bonding layer after the photoresist is developed by an electroplating or electroless plating method, and forming a welding bump on the metal bump, wherein the metal bump comprises a plurality of columnar bodies connected with a chip welding pad and a plane part connected with the welding bump;
and S7, removing the photosensitive photoresist, and etching the metal bonding layer by using the welding lug as a mask to obtain the complete semiconductor packaging structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010658821.XA CN111682006A (en) | 2020-07-09 | 2020-07-09 | Semiconductor packaging structure and manufacturing method thereof |
| PCT/CN2020/126415 WO2022007267A1 (en) | 2020-07-09 | 2020-11-04 | Semiconductor encapsulation structure and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010658821.XA CN111682006A (en) | 2020-07-09 | 2020-07-09 | Semiconductor packaging structure and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112885825A (en) * | 2021-01-21 | 2021-06-01 | Tcl华星光电技术有限公司 | LED panel and preparation method thereof |
| WO2022007267A1 (en) * | 2020-07-09 | 2022-01-13 | 江苏纳沛斯半导体有限公司 | Semiconductor encapsulation structure and manufacturing method therefor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007273547A (en) * | 2006-03-30 | 2007-10-18 | Nec Corp | Semiconductor element and semiconductor device |
| US20090014871A1 (en) * | 2007-07-13 | 2009-01-15 | Infineon Technologies Ag | Semiconductor device |
| CN101364586A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Construction for packaging substrate and preparation thereof |
| CN107204316A (en) * | 2016-03-16 | 2017-09-26 | 三星电子株式会社 | It is capable of the semiconductor device of dispersive stress |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790016B (en) * | 2011-05-16 | 2014-10-15 | 颀邦科技股份有限公司 | Bump structure and producing process thereof |
| CN102790035B (en) * | 2011-05-17 | 2015-02-18 | 颀邦科技股份有限公司 | Bump structure and process |
| TWI502691B (en) * | 2011-11-18 | 2015-10-01 | Chipmos Technologies Inc | Conductive structure and method for forming the same |
| CN111682006A (en) * | 2020-07-09 | 2020-09-18 | 江苏纳沛斯半导体有限公司 | Semiconductor packaging structure and manufacturing method thereof |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007273547A (en) * | 2006-03-30 | 2007-10-18 | Nec Corp | Semiconductor element and semiconductor device |
| US20090014871A1 (en) * | 2007-07-13 | 2009-01-15 | Infineon Technologies Ag | Semiconductor device |
| CN101364586A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Construction for packaging substrate and preparation thereof |
| CN107204316A (en) * | 2016-03-16 | 2017-09-26 | 三星电子株式会社 | It is capable of the semiconductor device of dispersive stress |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022007267A1 (en) * | 2020-07-09 | 2022-01-13 | 江苏纳沛斯半导体有限公司 | Semiconductor encapsulation structure and manufacturing method therefor |
| CN112885825A (en) * | 2021-01-21 | 2021-06-01 | Tcl华星光电技术有限公司 | LED panel and preparation method thereof |
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| WO2022007267A1 (en) | 2022-01-13 |
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