CN111681584A - Display device and electronic apparatus - Google Patents
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- CN111681584A CN111681584A CN202010499321.6A CN202010499321A CN111681584A CN 111681584 A CN111681584 A CN 111681584A CN 202010499321 A CN202010499321 A CN 202010499321A CN 111681584 A CN111681584 A CN 111681584A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
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Abstract
The application provides a display device and electronic equipment, display device includes: a time schedule controller; the source driving chips are electrically connected with the time sequence controller; the source driving chip is used for outputting a feedback signal to the time schedule controller in each horizontal blanking period; the time schedule controller keeps a normal working mode in the horizontal blanking period according to the feedback signal; or, the timing controller retransmits a clock training pattern to the corresponding source driving chip in the horizontal blanking period according to the feedback signal, so as to re-lock the transmission frequency of the display data between the timing controller and the source driving chip. According to the scheme, the abnormal locking between the time schedule controller and the source electrode driving chip can be avoided, and the display device is further prevented from displaying abnormal conditions.
Description
Technical Field
The application relates to the technical field of display, in particular to a display device and electronic equipment.
Background
The display device includes a plurality of source driving chips for supplying data voltages to data lines of the display panel, a plurality of gate driving chips for sequentially supplying scan signals to gate lines of the display panel, and a Timing Controller (TCON) for controlling the source driving chips and the gate driving chips, and the like. The source driving chip can recover a clock signal according to a clock training mode provided by the time schedule controller, and the transmission frequency of display data is locked between the time schedule controller and the source driving chip. However, when the locking of the clock signal is released due to electrostatic discharge (ESD) stress or other environmental stimuli, the locking between the timing controller and the source driving chip is abnormal, which may cause abnormal display of the display device.
Disclosure of Invention
The application provides a display device and an electronic device, which are used for solving the technical problem that abnormal display of the display device is caused due to abnormal locking between a time schedule controller and a source electrode driving chip in the prior art
The application provides a display device, it includes:
a time schedule controller;
the source driving chips are electrically connected with the time sequence controller; wherein the content of the first and second substances,
the source driving chip is used for outputting a feedback signal to the time schedule controller in each horizontal blanking period; the time schedule controller keeps a normal working mode in the horizontal blanking period according to the feedback signal; or, the timing controller retransmits a clock training pattern to the corresponding source driving chip in the horizontal blanking period according to the feedback signal, so as to re-lock the transmission frequency of the display data between the timing controller and the source driving chip.
In the display device provided by the application, the time sequence controller is used for outputting first display data to the corresponding source electrode driving chip;
the source electrode driving chip generates second display data based on the first display data; the feedback signal is the second display data.
In the display device provided by the application, the timing controller comprises a first comparing unit, and the first comparing unit is used for comparing the first display data with the second display data;
if the first display data is different from the second display data, the time schedule controller resends a clock training mode to the corresponding source electrode driving chip in the horizontal blanking period;
and if the first display data is the same as the second display data, the time schedule controller keeps a normal working mode in the horizontal blanking period.
In the display device provided by the application, the time sequence controller is used for outputting the display data to the corresponding source electrode driving chip according to a first frequency;
the source electrode driving chip generates a second frequency based on the first frequency; the feedback signal is the second frequency.
In the display device provided by the application, the timing controller comprises a second comparing unit, and the second comparing unit is used for comparing the first frequency with the second frequency;
if the first frequency is different from the second frequency, the time schedule controller resends a clock training mode to the corresponding source electrode driving chip in the horizontal blanking period;
and if the first frequency is the same as the second frequency, the time schedule controller keeps a normal working mode in the horizontal blanking period.
In the display device provided by the application, the time sequence controller is used for outputting the display data to the corresponding source electrode driving chip according to a first frequency; the source electrode driving chip generates a second frequency based on the first frequency;
the source driving chip comprises a third comparison unit, and the third comparison unit is used for comparing the first frequency with the second frequency;
if the first frequency is the same as the second frequency, the source driving chip outputs a feedback signal indicating that the timing controller and the source driving chip are locked normally, so that the timing controller keeps a normal working mode in the horizontal blanking period;
if the first frequency is different from the second frequency, the source driving chip outputs a feedback signal indicating that locking between the timing controller and the source driving chip is abnormal, so that the timing controller retransmits a clock training mode to the corresponding source driving chip in the horizontal blanking period.
In the display device provided by the application, the time schedule controller is provided with an output pin, and the output pin is electrically connected with each source electrode driving chip through a clock signal bus;
and the time schedule controller transmits the clock training mode to the corresponding source electrode driving chip through the clock signal bus.
In the display device provided by the application, the timing controller is provided with a first receiving pin, and the first receiving pin is electrically connected with each source electrode driving chip through a feedback signal bus;
the time schedule controller receives the feedback signal output by each source electrode driving chip in a time-sharing way through the feedback signal bus.
In the display device provided by the application, the time schedule controller is provided with a plurality of second receiving pins, and each second receiving pin is connected with the source driving chip in a one-to-one correspondence manner through a corresponding connecting wire;
and the time schedule controller receives the feedback signal output by the corresponding source electrode driving chip through the corresponding connecting wire.
Correspondingly, the application also provides an electronic device, which comprises the display device of any one of the above claims.
The application provides a display device and an electronic device, the display device comprises a time schedule controller and at least one source electrode driving chip, a feedback signal is output to the time schedule controller by the source electrode driving chip in each horizontal blanking period, if the feedback signal indicates that the locking between the time schedule controller and the source electrode driving chip is abnormal, the time schedule controller can resend a clock training mode to the corresponding source electrode driving chip in the horizontal blanking period, so that the transmission frequency of display data is relocked between the time schedule controller and the source electrode driving chip, and the abnormal display of the display device is avoided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of data transmitted to a source driving chip by a timing controller according to the present application;
FIG. 2 is a schematic diagram of a first structure of a display device provided in the present application;
fig. 3 is another schematic diagram of a structure of data transmitted from the timing controller to the source driver chip according to the present application;
FIG. 4 is a schematic diagram of a second structure of the display device provided in the present application;
FIG. 5 is a schematic diagram of a third structure of a display device provided in the present application;
fig. 6 is a fourth structural schematic diagram of the display device provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second", etc. may explicitly or implicitly include one or more of the described features and are therefore not to be construed as limiting the application.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of data transmitted to a source driver chip by a timing controller according to the present application. Fig. 2 is a schematic view of a first structure of a display device provided in the present application. As shown in fig. 1 and fig. 2, when the display device displays images, a gate driving circuit (not shown) scans pixels of the display panel 30 line by line, wherein a scanning interval between two adjacent lines of pixels is called a Horizontal Blanking (HB) period. That is, the horizontal blanking period is a very short period of time in which no data exists between the nth horizontal period and the (N +1) th horizontal period, N being a positive integer. In the horizontal blank period, the timing controller 10 may transmit blank data, which may be invalid data, for example, the blank data may be all 0, to the source driving chip 20. Meanwhile, the timing controller 10 transmits display data, for example, red, green and blue (RGB) data corresponding to each row of pixels to the source driving chip 20 in an effective data period during each horizontal period.
Referring to fig. 2 and 3, fig. 3 is another schematic structural diagram of data transmitted to a source driver chip by a timing controller according to the present application. As shown in fig. 2 and 3, the present application provides a display device including: a timing controller 10; at least one source driving chip 20, each source driving chip 20 being electrically connected to the timing controller 10; the source driver chip 20 is configured to output a feedback signal to the timing controller 10 in each horizontal blanking period; the timing controller 10 maintains a normal operation mode in a horizontal blanking period according to the feedback signal; alternatively, the timing controller 10 retransmits the clock training pattern to the corresponding source driving chip 20 in the horizontal blank period according to the feedback signal to re-lock the transmission frequency of the display data between the timing controller 10 and the source driving chip 20.
It is understood that in the display data transmission scheme between the timing controller 10 and the source driving chips 20, first, the timing controller 10 may transmit clock signals to the source driving chips at a fixed frequency. The source driving chip receives the clock signal and locks the transmission frequency at which the timing controller 10 transmits the display data based on the clock signal. The timing controller 10 may transmit the display data to the source driving chip 20 at the fixed frequency while the source driving chip 20 may receive and capture the display data at the fixed frequency. Wherein the clock signal may be a clock training pattern.
With the improvement of the resolution specification of the display device and the load limitation of the source driver chips 20, a plurality of source driver chips 20 are disposed in the display device. The abnormal locking of the transmission frequency of the display data between any source driver chip 20 and the timing controller 10 will cause the display device to display abnormally, which affects the display quality. In each horizontal blanking period, each source driver chip 20 outputs a feedback signal to the timing controller 10, and when any feedback signal indicates that the locking between the timing controller 10 and the corresponding source driver chip 20 is abnormal, the timing controller 10 may re-transmit the clock training mode to the corresponding source driver chip 20 in the horizontal blanking period, so as to re-lock the transmission frequency of the display data between the timing controller 10 and the corresponding source driver chip 20, so that the timing controller 10 and the source driver chip 20 can perform normal transmission of the display data in each horizontal period, and each frame of the display device can normally display.
In practical applications, there may be an abnormal locking between one source driving chip 20 and the timing controller 10, or there may be an abnormal locking between a plurality of source driving chips 20 and the timing controller 10. The timing controller 10 may be configured to re-transmit the clock training pattern to the corresponding source driving chip 20 where the latch abnormality occurs during the horizontal blank period, so as to reduce power consumption of the timing controller 10 and extend a lifetime thereof. The timing controller 10 may also be configured to re-transmit the clock training pattern to each source driving chip 20 during the horizontal blanking period, including the source driving chips 20 without the occurrence of the locking abnormality, so as to further ensure the working consistency of the source driving chips 20. The ground thorns are not particularly limited in this application, and can be set according to actual requirements.
In addition, the source driver Chip 10 may be fixed On a Chip On Film (COF) 40, which is well known to those skilled in the art and will not be described herein.
The embodiment of the present application provides a display device, which includes a timing controller 10 and at least one source driver chip 20, wherein the source driver chip 20 is utilized to output a feedback signal to the timing controller 10 in each horizontal blanking period, and if the feedback signal indicates that the locking between the timing controller 10 and the source driver chip 20 is abnormal, the timing controller 10 can resend a clock training mode to the corresponding source driver chip 20 in the horizontal blanking period, so as to relock the transmission frequency of display data between the timing controller 10 and the source driver chip 20, and avoid the abnormal display of the display device caused by the abnormal locking between the timing controller 10 and the source driver chip 20.
Referring to fig. 2, in the embodiment of the present invention, the timing controller 10 is connected to each source driver chip 20 through a data line 51. The timing controller 10 transmits display data to the corresponding source driving chip 20 through the corresponding data line 51.
In addition, in the embodiment of the present application, the timing controller 10 has an output pin b. The output pin b is electrically connected to each of the source driver chips 20 through a clock signal bus 53. The timing controller 10 transmits the clock training pattern to the corresponding source driver chip 20 through the clock signal bus 53. Wherein, the timing controller 10 may be configured to transmit the clock training pattern to the corresponding one or more source driving chips 20; the timing controller 10 may also be configured to transmit a clock training pattern to each of the source driver chips 20.
It should be noted that, in other embodiments, the clock signal bus 53 may not be provided between the timing controller 10 and the source driver 20. The timing controller 10 may be configured to transmit the clock training pattern to the corresponding source driving chip 20 through the data line 51. This arrangement can reduce the wiring between the timing controller 10 and the source driving chip 20, and avoid the generation of signal crosstalk.
Further, in the embodiment of the present application, the timing controller 10 has a first receiving pin b. The first receiving pin b is electrically connected to each of the source driver chips 20 through a feedback signal bus 52. The timing controller 10 receives the feedback signal outputted from each source driving chip 20 in time-division through the feedback signal bus 52.
In another embodiment of the present application, please refer to fig. 4, and fig. 4 is a second structural diagram of the display device provided in the present application. As shown in fig. 4, the timing controller 10 has a plurality of second receiving pins c. Each second receiving pin c is connected to the source driver chips 20 through a corresponding connecting trace 54 in a one-to-one correspondence. The timing controller 10 receives the feedback signal output from the corresponding source driving chip 20 through the corresponding connection trace 54. This arrangement eliminates the need to configure the timing controller 10 to receive the feedback signal output from each source driver chip 20 at different time intervals, and can reduce the power consumption of the timing controller 10 and prevent transmission errors of the feedback signal.
In an embodiment of the present application, please refer to fig. 5, and fig. 5 is a schematic diagram of a third structure of the display device provided in the present application. As shown in fig. 5, the timing controller 10 is further configured to output a first display data to the corresponding source driver chip 20. The source driving chip 20 generates second display data 20 based on the first display data 10. Wherein the feedback signal is the second display data.
Wherein, the timing controller 10 includes a first comparing unit 11. The first comparing unit 10 is configured to compare the first display data with the second display data; if the first display data is different from the second display data, the timing controller 10 retransmits the clock training pattern to the corresponding source driver chip 20 in the horizontal blanking period; if the first display data is the same as the second display data, the timing controller 10 maintains the normal operation mode during the horizontal blank period.
It is understood that, in the normal operation mode, the timing controller 10 transmits the first display data to the corresponding source driver chip 20 in the data valid period, and the second display data correspondingly received by the source driver chip 20 should be the same as the first display data. However, due to interference from other environmental factors such as static electricity test, the second display data received by the source driver chip 20 may be different from the first display data, which may cause abnormal display of the display device. Therefore, each source driving chip 20 outputs the second display data currently received by it to the timing controller 10 as a feedback signal, and the first comparing unit 11 in the timing controller 10 compares the first display data with the second display data to determine whether the locking between the timing controller 10 and the source driving chip 20 is normal.
The first display data and the second display data are the same, and the first display data and the second display data have the same content and the same byte length.
In another embodiment of the present application, please continue to refer to fig. 5, the timing controller 10 is further configured to output display data to the corresponding source driver chip 20 according to the first frequency; the source driving chip 20 generates a second frequency based on the first frequency; wherein the feedback signal is at a second frequency.
Wherein the timing controller 10 includes a second comparing unit 12. The second comparing unit 12 is used for comparing the first frequency with the second frequency; if the first frequency is different from the second frequency, the timing controller 10 retransmits the clock training pattern to the corresponding source driver chip 20 in the horizontal blanking period; if the first frequency is the same as the second frequency, the timing controller 10 maintains the normal operation mode during the horizontal blank period.
It can be understood that, in the normal operation mode, the timing controller 10 transmits the display data to the corresponding source driver chip 20 according to the first frequency in the data valid period, and the source driver chip 20 receives the display data according to the second frequency, where the first frequency is the same as the second frequency. However, due to interference from other environmental factors such as static electricity test, the second frequency may change and generate a difference with the first frequency, so that the display data received by the source driver chip 20 is incorrect, resulting in abnormal display of the display device. Therefore, each source driving chip 20 outputs the second frequency at which it currently receives the display data to the timing controller 10 as a feedback signal, and the second comparing unit 12 in the timing controller 10 compares the first frequency with the second frequency to determine whether the locking between the timing controller 10 and the source driving chip 20 is normal.
In another embodiment of the present application, please refer to fig. 6, where fig. 6 is a fourth structural diagram of the display device provided in the present application. As shown in fig. 6, the timing controller 10 is further configured to output display data to the corresponding source driver chip 20 according to the first frequency. The source driving chip 20 generates a second frequency based on the first frequency. The display device provided by the embodiment of the present application is different from the display device in fig. 5 in that the timing controller 10 does not need to be provided with the comparing unit 11 or 12; the source driving chip 20 includes a third comparing unit 21. The third comparing unit 21 is configured to compare the first frequency with the second frequency.
If the first frequency is the same as the second frequency, the source driving chip 20 outputs a feedback signal indicating that the timing controller 10 and the source driving chip 20 are locked to be normal, so that the timing controller 10 maintains a normal operation mode during a horizontal blanking period.
If the first frequency is different from the second frequency, the source driver chip outputs a feedback signal indicating that the locking between the timing controller 10 and the source driver chip 20 is abnormal, so that the timing controller 10 retransmits the clock training pattern to the corresponding source driver chip 20 in the horizontal blanking period.
Each source driver chip 20 may include a memory cell (not shown) for storing the first frequency. It is understood that, in the normal operation mode, each of the source driver chips 20 and the timing controller 10 performs the display data transmission according to a fixed frequency, i.e. the first frequency is equal to the second frequency, and at this time, the memory cells in the source driver chips 20 store the second frequency, which is equivalent to storing the first frequency. After the timing controller 10 retransmits the clock training pattern to the corresponding source driving chip 20 every horizontal blank period and re-locks the transmission frequency of the display data between the timing controller 10 and the corresponding source driving chip 20, the storage unit may re-store the second frequency so that the third comparing unit 21 performs the comparing operation in the next horizontal blank period.
In the embodiment of the present application, the third comparing unit 21 is disposed in the source driving chip 20, and directly outputs the feedback signal indicating whether the locking between the timing controller 10 and the source driving chip 20 is abnormal, so that the timing controller 10 can immediately respond after receiving the feedback signal, thereby reducing the load of the timing controller 10.
Accordingly, the present application further provides an electronic device, which includes the display device according to any of the above embodiments, and reference may be made to the above contents, which is not described herein again. In addition, the electronic device may be a smart phone, a tablet computer, an electronic book reader, a smart watch, a camera, a game machine, and the like, which is not limited in this application.
The electronic equipment provided by the application comprises a display device, the display device comprises a time schedule controller and at least one source electrode driving chip, a feedback signal is output to the time schedule controller by the source electrode driving chip in each horizontal blanking period, if the feedback signal indicates that the locking between the time schedule controller and the source electrode driving chip is abnormal, the time schedule controller can resend a clock training mode to the corresponding source electrode driving chip in the horizontal blanking period so as to relock the transmission frequency of display data between the time schedule controller and the source electrode driving chip, the time schedule controller and the source electrode driving chip can normally transmit the display data in each horizontal period, the display device display abnormality caused by the locking abnormality between the time schedule controller and the source electrode driving chip is avoided, and the quality of the electronic equipment is improved.
The display device and the electronic device provided by the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display device, comprising:
a time schedule controller;
the source driving chips are electrically connected with the time sequence controller; wherein the content of the first and second substances,
the source driving chip is used for outputting a feedback signal to the time schedule controller in each horizontal blanking period; the time schedule controller keeps a normal working mode in the horizontal blanking period according to the feedback signal; or, the timing controller retransmits a clock training pattern to the corresponding source driving chip in the horizontal blanking period according to the feedback signal, so as to re-lock the transmission frequency of the display data between the timing controller and the source driving chip.
2. The display device according to claim 1, wherein the timing controller is configured to output a first display data to the corresponding source driver chip;
the source electrode driving chip generates second display data based on the first display data; the feedback signal is the second display data.
3. The display device according to claim 2, wherein the timing controller includes a first comparing unit for comparing the first display data with the second display data;
if the first display data is different from the second display data, the time schedule controller resends a clock training mode to the corresponding source electrode driving chip in the horizontal blanking period;
and if the first display data is the same as the second display data, the time schedule controller keeps a normal working mode in the horizontal blanking period.
4. The display device according to claim 1, wherein the timing controller is configured to output the display data to the corresponding source driver chip according to a first frequency;
the source electrode driving chip generates a second frequency based on the first frequency; the feedback signal is the second frequency.
5. The display device according to claim 4, wherein the timing controller includes a second comparing unit for comparing the first frequency with the second frequency;
if the first frequency is different from the second frequency, the time schedule controller resends a clock training mode to the corresponding source electrode driving chip in the horizontal blanking period;
and if the first frequency is the same as the second frequency, the time schedule controller keeps a normal working mode in the horizontal blanking period.
6. The display device according to claim 1, wherein the timing controller is configured to output the display data to the corresponding source driver chip according to a first frequency; the source electrode driving chip generates a second frequency based on the first frequency;
the source driving chip comprises a third comparison unit, and the third comparison unit is used for comparing the first frequency with the second frequency;
if the first frequency is the same as the second frequency, the source driving chip outputs a feedback signal indicating that the timing controller and the source driving chip are locked normally, so that the timing controller keeps a normal working mode in the horizontal blanking period;
if the first frequency is different from the second frequency, the source driving chip outputs a feedback signal indicating that locking between the timing controller and the source driving chip is abnormal, so that the timing controller retransmits a clock training mode to the corresponding source driving chip in the horizontal blanking period.
7. The display device according to claim 1, wherein the timing controller has an output pin electrically connected to each of the source driver chips through a clock signal bus;
and the time schedule controller transmits the clock training mode to the corresponding source electrode driving chip through the clock signal bus.
8. The display device according to claim 1, wherein the timing controller has a first receiving pin electrically connected to each of the source driver chips through a feedback signal bus;
the time schedule controller receives the feedback signal output by each source electrode driving chip in a time-sharing way through the feedback signal bus.
9. The display device according to claim 1, wherein the timing controller has a plurality of second receiving pins, each of the second receiving pins being connected to the source driver chips in a one-to-one correspondence via a corresponding connection trace;
and the time schedule controller receives the feedback signal output by the corresponding source electrode driving chip through the corresponding connecting wire.
10. An electronic device characterized by comprising the display device according to any one of claims 1 to 9.
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| CN202010499321.6A CN111681584A (en) | 2020-06-04 | 2020-06-04 | Display device and electronic apparatus |
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| CN114373419A (en) * | 2022-02-10 | 2022-04-19 | Tcl华星光电技术有限公司 | Display panel, control method thereof and mobile terminal |
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| CN109785806A (en) * | 2017-11-15 | 2019-05-21 | 三星显示有限公司 | Show equipment and its driving method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114373419A (en) * | 2022-02-10 | 2022-04-19 | Tcl华星光电技术有限公司 | Display panel, control method thereof and mobile terminal |
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