CN111668311B - MOSFET chip layout structure - Google Patents
MOSFET chip layout structure Download PDFInfo
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- CN111668311B CN111668311B CN202010447250.5A CN202010447250A CN111668311B CN 111668311 B CN111668311 B CN 111668311B CN 202010447250 A CN202010447250 A CN 202010447250A CN 111668311 B CN111668311 B CN 111668311B
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- 239000002184 metal Substances 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 230000001413 cellular effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 36
- 238000010586 diagram Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a MOSFET chip layout structure, which is applied to a MOSFET chip and comprises a first layer of source metal positioned at the bottom and a second layer of source metal contacted with the top surface of the first layer of source metal, wherein the first layer of source metal is a source region surrounded by a grid Bus bar, a grid etching window is arranged on the grid Bus bar, the second layer of source metal covers the first layer of source metal, and a grid bonding region arranged on the second layer of source metal is contacted with the grid Bus bar through the grid etching window. The invention has the advantages that: the front metal adopts double-layer wiring, namely the first layer of metal is all source metal except the grid Bus bars, so that the original grid bonding area can be completely expanded to be a source area, and the cellular area of the chip is increased, thereby effectively reducing the on-resistance of the chip and improving the performance of the chip; or under the condition of obtaining the same on-resistance, the chip area can be reduced, and finally the chip cost is reduced.
Description
Technical Field
The invention relates to a MOSFET chip layout structure.
Background
A Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is a Field Effect Transistor that can be widely used in the Field of power electronics. MOSFETs are classified into "N-type" and "P-type" types according to their "channel" (working carrier) polarities, and are also called NMOSFET and PMOSFET, and include NMOS and PMOS for short.
The front metal of a MOSFET chip in the prior art is generally a single-layer metal, and two electrodes of the front metal are: the gate (G pole) and the source (S pole) can only be laid on the same metal layer, so that the gate occupies part of the source area. As shown in fig. 1, the gate bonding region occupies more source region area. The on-resistance of the chip is high, and the performance of the chip is insufficient; on the other hand, to achieve the target on-resistance, a large chip area is required, and the chip cost is high.
Disclosure of Invention
The invention provides a MOSFET chip layout structure, which aims to overcome the defects in the prior art, effectively reduce the on-resistance of a chip, improve the performance of the chip, reduce the area of the chip and reduce the cost of the chip.
The technical solution of the invention is as follows: the utility model provides a MOSFET chip territory structure, is applied to a MOSFET chip, including the first layer source metal that is located the bottom and the second layer source metal with first layer source metal top surface contact, first layer source metal is the source electrode area that has the grid Bus strip of surrounding all around, and it has the grid sculpture window to open on the grid Bus strip, and second layer source metal covers first layer source metal, establishes the grid bonding region on the second layer source metal and passes through grid sculpture window and grid Bus strip contact.
Preferably, the area of the second layer of source metal is larger than that of the first layer of source metal.
A manufacturing method of a MOSFET chip layout structure comprises the following processing steps:
1) covering the grid Bus and the source electrode by the same metal to complete a first layer of metal;
2) photoetching and etching the first layer of metal, and separating Bus metal of the source electrode and the grid electrode;
3) depositing a dielectric layer, photoetching and etching, and opening a grid etching window on the grid Bus;
4) completing the contact between the second layer of metal and the grid Bus metal of the first layer of metal;
5) finally, photoetching and etching are carried out again to separate the grid electrode and the source electrode on the second layer of metal.
The invention has the advantages that: the front metal adopts double-layer wiring, namely the first layer of metal is all source metal except the grid Bus bars, so that the original grid bonding area can be completely expanded to be a source area, and the cellular area of the chip is increased, thereby effectively reducing the on-resistance of the chip and improving the performance of the chip; or under the condition of obtaining the same on-resistance, the chip area can be reduced, and finally the chip cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a prior art MOSFET chip layout structure.
FIG. 2 is a schematic diagram of the first metal layer of the MOSFET chip layout structure of the present invention.
Fig. 3 is a schematic diagram of the MOSFET chip layout structure of the present invention.
Fig. 4 is a longitudinal sectional view of a portion a of fig. 3.
In the figure, 1 is a source region, 2 is a gate bonding region, and 3 is a gate Bus bar.
Detailed Description
The present invention will be described in further detail with reference to examples and specific embodiments.
As shown in fig. 3, a MOSFET chip layout structure is applied to a MOSFET chip, and includes a first layer of source metal located at the bottom and a second layer of source metal in contact with the top surface of the first layer of source metal, where the first layer of source metal is a source region 1 surrounded by gate Bus bars 3, a gate etching window is opened on the gate Bus bars 3, the second layer of source metal covers the first layer of source metal, and a gate bonding region 2 is arranged on the second layer of source metal and is in contact with the gate Bus bars 3 through the gate etching window.
The area of the second layer of source electrode metal is larger than that of the first layer of source electrode metal.
As shown in fig. 2 and 3, a method for manufacturing a MOSFET chip layout structure includes the following steps:
1) covering the grid Bus and the source electrode by the same metal to complete a first layer of metal;
2) photoetching and etching the first layer of metal, and separating Bus metal of the source electrode and the grid electrode;
3) depositing a dielectric layer, photoetching and etching, and opening a grid etching window on the grid Bus;
4) completing the (good) contact between the second layer of metal and the grid Bus metal of the first layer of metal; (the area of the second layer of source electrode metal is required to be as large as possible, and the first layer of source electrode metal is covered as much as possible so as to be beneficial to heat dissipation.)
5) Finally, photoetching and etching are carried out again to separate the grid electrode and the source electrode on the second layer of metal.
All the above components are prior art, and those skilled in the art can use any model and existing design that can implement their corresponding functions.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (1)
1. A MOSFET chip layout structure is applied to a MOSFET chip and is characterized by comprising a first layer of source metal positioned at the bottom and a second layer of source metal contacted with the top surface of the first layer of source metal, wherein the first layer of source metal is a source region (1) surrounded by a grid Bus bar (3), a grid etching window is formed on the grid Bus bar (3), the second layer of source metal covers the first layer of source metal, and a grid bonding region (2) arranged on the second layer of source metal is contacted with the grid Bus bar (3) through the grid etching window; the area of the second layer of source electrode metal is larger than that of the first layer of source electrode metal;
the manufacturing method of the MOSFET chip layout structure comprises the following process steps:
1) covering the grid Bus and the source electrode by the same metal to complete a first layer of metal;
2) photoetching and etching the first layer of metal, and separating Bus metal of the source electrode and the grid electrode;
3) depositing a dielectric layer, photoetching and etching, and opening a grid etching window on the grid Bus;
4) completing the contact between the second layer of metal and the grid Bus metal of the first layer of metal;
5) finally, photoetching and etching are carried out again to separate the grid electrode and the source electrode on the second layer of metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010447250.5A CN111668311B (en) | 2020-05-25 | 2020-05-25 | MOSFET chip layout structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010447250.5A CN111668311B (en) | 2020-05-25 | 2020-05-25 | MOSFET chip layout structure |
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| Publication Number | Publication Date |
|---|---|
| CN111668311A CN111668311A (en) | 2020-09-15 |
| CN111668311B true CN111668311B (en) | 2021-08-24 |
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| CN202010447250.5A Active CN111668311B (en) | 2020-05-25 | 2020-05-25 | MOSFET chip layout structure |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151349A (en) * | 2012-12-19 | 2013-06-12 | 成都芯源***有限公司 | Semiconductor device and method for manufacturing the same |
| CN106816437A (en) * | 2017-03-06 | 2017-06-09 | 北京世纪金光半导体有限公司 | A kind of SiC crystal tube device of integrated current sensors and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008010628A (en) * | 2006-06-29 | 2008-01-17 | Sanyo Electric Co Ltd | Semiconductor device, and manufacturing method thereof |
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- 2020-05-25 CN CN202010447250.5A patent/CN111668311B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151349A (en) * | 2012-12-19 | 2013-06-12 | 成都芯源***有限公司 | Semiconductor device and method for manufacturing the same |
| CN106816437A (en) * | 2017-03-06 | 2017-06-09 | 北京世纪金光半导体有限公司 | A kind of SiC crystal tube device of integrated current sensors and preparation method thereof |
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| CN111668311A (en) | 2020-09-15 |
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Address after: No. 88, Zhongtong East Road, Shuofang street, Xinwu District, Wuxi City, Jiangsu Province Patentee after: Jiangsu Donghai Semiconductor Co.,Ltd. Address before: No. 88, Zhongtong East Road, Shuofang street, Xinwu District, Wuxi City, Jiangsu Province Patentee before: WUXI ROUM SEMICONDUCTOR TECHNOLOGY Co.,Ltd. |
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