CN109244128A - A kind of semi-enclosed shield grid IEGT device architecture and preparation method thereof - Google Patents
A kind of semi-enclosed shield grid IEGT device architecture and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 210000000746 body region Anatomy 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 74
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 12
- 230000001413 cellular effect Effects 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000003628 erosive effect Effects 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000006698 induction Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract
The invention belongs to the manufacturing technology fields of semiconductor devices, it is related to a kind of semi-enclosed shield grid IEGT device architecture, semiconductor substrate includes the first conduction type drift layer, top in the first conduction type drift layer is equipped with the second conductivity type body region, groove and the first conduction type emitter, second conductivity type body region, first conduction type emitter is adjacent with groove side, it is equipped with the polysilicon gate wrapped up by the first oxide layer and the second oxide layer side in the trench, the semi-enclosed shield grid of semi-surrounding polysilicon gate on the outside of the first oxide layer, semi-enclosed shield grid is wrapped up by the second oxide layer, second oxide layer is close to trench wall；Device of the present invention outside polysilicon gate by being provided with the semi-enclosed shield grid of semi-surrounding, the transvercal induction electric current that device is generated when being switched on and off can be effectively eliminated, the phenomenon that avoiding gate voltage overshoot, reduce parasitic capacitance, switching speed is accelerated simultaneously, reduces switching loss.
Description
Technical field
The present invention relates to a kind of power semiconductor and its manufacturing method, especially a kind of semi-enclosed shield grid IEGT
Device architecture and preparation method thereof belongs to the manufacturing technology field of semiconductor devices.
Background technique
GBT (Insulated Gate Bipolar Transistor), insulated gate bipolar transistor is (double by BJT
Polar form triode) and MOS (insulating gate type field effect tube) composition compound full-control type voltage driven type power semiconductor, it is simultaneous
Advantage of both having the high input impedance of MOSFET and the low conduction voltage drop of GTR is collection high-frequency, high voltage, low pass state pressure
The novel power semiconductor device that drop and simple driving circuit are integrated, is widely used in mesohigh field.With current
World energy sources crisis more carrys out urgent and environmental consciousness raising, and energy-efficient, the simple product of driving becomes market development
New trend.Due to the various outstanding advantages of IGBT, power semiconductor manufacturer of various countries all is making great efforts to research and develop, it is desirable to further mention
The pressure resistance of high IGBT is applied with through-current capability in higher voltage domain.
(Injection Enhancement Gate Transistor is electron injection enhancement type gridistor IEGT
It is developed by IGBT, as shown in Figure 1, being the schematic cross-sectional view of the existing single cellular of IEGT device, IEGT is utilized
The design in the area dummy carrys out a large amount of hole heap in the area dummy, in order to reach charge balance, can cause emitter
Electron injection enhancement effect (Injection Enhancement), the increase of carrier quantity make the conductivity modulation effect of device
Enhancing, on-state voltage drop is greatly reduced, while improving the balance of the Carrier Profile in drift region, optimize device switch and
Steady-state characteristic.
Currently, stability, switching loss and reliability are tested power device.In normal operation,
The structure that the area dummy is utilized in IEGT flows into a large amount of holoe carrier in the area dummy, when opening, this part carrier
Surface transverse shifting in the area dummy, forms surface transverse current, forms certain potential difference with gate bottom.In this way
Potential difference produce induced current in the gate, flow through grid equivalent resistance, enhance grid voltage, grid voltage occur
Overshoot.Likewise, carving when off, a large amount of holoe carriers in the area dummy, which need to flow out, forms surface transverse current, in grid
Cause grid voltage to increase in extremely, cause device can not normal turn-off, formed oscillation.Both the above situation all easily causes power
It fails caused by the variation of device transient voltage is excessive.
On the other hand, the area dummy increases the contact area of grid and drain electrode, and such design will lead to miller capacitance
Excessive, miller capacitance affects the switching speed of device, further will affect the switching loss of device.
So a kind of better reliability, the smaller IEGT structure of switching loss are needed, to overcome present in the prior art
It is insufficient.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of semi-enclosed shield grid IEGT device is proposed
Part structure and preparation method thereof, by being provided with the semi-enclosed shield grid of semi-surrounding outside polysilicon gate, and it is semiclosed
Formula shield grid connects zero potential, and the presence of semi-enclosed shield grid can effectively eliminate the transverse direction that device is generated when being switched on and off
Induced current, the phenomenon that avoiding gate voltage overshoot guarantee that device is normally-open and shutdown, while accelerating switching speed,
Reduce switching loss.
To realize the above technical purpose, the technical scheme is that a kind of semi-enclosed shield grid IEGT device architecture,
Including active area, the active area includes several device cellular units parallel with one another, and the device cellular unit includes half
Conductor substrate, in the device cellular unit cross-wise direction, the semiconductor substrate includes the first conduction type drift layer,
Top in the first conduction type drift layer is equipped with the second conductivity type body region, groove and is located at the second conductivity type body region
First conduction type emitter of internal upper part, second conductivity type body region, the first conduction type emitter with groove one
Side is adjacent, which is characterized in that is equipped with the polysilicon gate wrapped up by the first oxide layer and the second oxide layer side in the groove
Pole, semi-surrounding polysilicon gate on the outside of the first oxide layer semi-enclosed shield grid, the semi-enclosed shield grid quilt
Second oxide layer package, second oxide layer 11 are close to 13 inner wall of groove.
Further, the semi-enclosed shield grid is distributed in one of polysilicon gate far from the first conduction type emitter
Side and below, and side of the polysilicon gate far from the first conduction type emitter and the first conduction type drift about interlayer
Pass sequentially through the first oxide layer, semi-enclosed shield grid, the second oxide layer spacer.
Further, oxide protective layer, emitter metal, institute are successively covered on the first conduction type drift layer
State emitter metal and second conductivity type body region, the first conduction type emitter Ohmic contact, the semi-enclosed screen
Grid are covered to be electrically connected with emitter metal.
Further, the first conduction type cutoff layer, second are successively arranged below the first conduction type drift layer
Conduction type collector and collector electrode metal, the collector electrode metal and the second conduction type collector Ohmic contact.
Further, it is gate oxide that second oxide layer, which is close to the side of polysilicon gate,.
In order to further realize the above technical purpose, the present invention also proposes a kind of semi-enclosed shield grid IEGT device architecture
Manufacturing method, which comprises the steps of:
Step 1: choosing semiconductor substrate, the semiconductor substrate includes the first conduction type drift layer, using etching technics,
The upper surface of the first conduction type drift layer is performed etching to obtain several grooves；
Step 2: in the trench, forming the second oxide layer, and continued growth polysilicon in the trench, the polycrystalline by oxidation
Silicon fills up groove；
Step 3: performing etching the polysilicon in groove using etching technics, etch to obtain internal channel in the side of groove,
Semi-enclosed shield grid is obtained in the lower section of groove and the other side simultaneously；
Step 4: in internal channel, the first oxide layer is formed by oxidation, and continued growth polysilicon and fill up septal fossula wherein
Slot obtains polysilicon gate in internal channel；
5th step；Using photoetching process, the second conductive type impurity of layer surface Selective implantation is drifted about simultaneously in the first conduction type
Trap is pushed away, the second conductivity type body region is formed；
Step 6: using photoetching process, it is high in the first conduction type drift the first conductive type impurity of layer surface Selective implantation
Temperature obtains the first conduction type emitter after pushing away trap, then deposited oxide protective layer；
Step 7: selectively being performed etching to oxide protective layer, the first conduction type emitter using etching technics, until dew
Second conductivity type body region out；
Step 8: forming emitter metal in device front deposited metal aluminium；
Step 9: being implanted sequentially the first conductive type impurity, the second conductive type impurity at the device back side, it is respectively formed first and leads
Electric type cutoff layer, the second conduction type collector；
Step 10: the deposited metal aluminium on the second conduction type collector, forms collector electrode metal, it is semiclosed to complete manufacture
Formula shield grid IEGT.
Further, for N-type shield grid IEGT device, first conduction type is that N-type is conductive, and described second is conductive
Type is P-type conduction；For p-type shield grid IEGT device, first conduction type is P-type conduction, second conductive-type
Type is that N-type is conductive.
Compared with conventional trench gate IGBT device, the invention has the following advantages that
1) present invention is outside polysilicon gate by being provided with the semi-enclosed shield grid of semi-surrounding, while by semi-enclosed screen
It covers grid and is electrically connected to N-type emitter (being connected to zero potential), in device opening process, polysilicon gate person's forward voltage,
Semi-enclosed shield grid connects zero potential, when the area dummy (region that N-type drift layer is located at groove side) has transverse current to flow through
When, and can be eliminated when induced current is flowed through from semi-enclosed shield grid, therefore, do not interfere with segregate polycrystalline
The phenomenon that voltage condition on silicon gate avoids the grid voltage variation of transverse current generation, eliminates gate voltage overshoot；
Same device can be equally eliminated, so that device is gathered around in turn off process when transverse current is flowed through from semi-enclosed shield grid
There is higher anti-collector voltage to shake the ability influenced on grid, guarantees device normal turn-off；
2) since grid (i.e. polysilicon gate) and collector has been isolated in semi-enclosed shield grid, it therefore reduces grid and collection
The contact area of electrode, and then miller capacitance (Cgd) is greatly reduced, faster, switching loss is smaller for switching speed.
Detailed description of the invention
The drawings are intended to provide a further understanding of the invention, and constitutes part of specification, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the schematic cross-sectional view of existing IEGT device cellular unit.
Fig. 2 is that the schematic cross-sectional view after groove is formed in the embodiment of the present invention 1.
Fig. 3 is to form the first oxide layer and polysilicon fills up the schematic cross-sectional view of groove in the embodiment of the present invention 1.
Fig. 4 is the schematic cross-sectional view that internal channel and semi-enclosed shield grid are formed in the embodiment of the present invention 1.
Fig. 5 is the schematic cross-sectional view that the second oxide layer and polysilicon gate are formed in the embodiment of the present invention 1.
Fig. 6 is the schematic cross-sectional view that the area PXing Ti is formed in the embodiment of the present invention 1.
Fig. 7 is the schematic cross-sectional view that N-type emitter and oxide protective layer are formed in the embodiment of the present invention 1.
Fig. 8 is the schematic cross-sectional view that N-type emitter and oxide protective layer are etched in the embodiment of the present invention 1.
Fig. 9 is the schematic cross-sectional view that emitter metal is formed in the embodiment of the present invention 1.
Figure 10 is that the sectional structure of formation N-type cutoff layer, p-type collector and collector electrode metal in the embodiment of the present invention 1 shows
It is intended to.
Description of symbols: 1, p-type collector；2, N-type cutoff layer；3, N-type drift layer；4, N-type emitter；5, p-type body
Area；6, polysilicon gate；7, the first oxide layer；8, oxide layer is protected；9, emitter metal；10, semi-enclosed shield grid；11,
Second oxide layer；12, collector electrode metal；13, groove；14, internal channel.
Specific embodiment
Below with reference to specific drawings and examples, a specific embodiment of the invention is carried out specifically below in conjunction with attached drawing
It is bright.It should be understood that the specific embodiments described herein are merely illustrative of the invention, it is not limited to this
Invention.
Embodiment 1 is by taking the semi-enclosed shield grid IEGT of N-type as an example, and the invention will be further described, and described first is conductive
Type is N-type, and second conduction type is p-type；
As shown in Fig. 10, the semi-enclosed shield grid IEGT device architecture of a kind of N-type, including active area, the active area include
Several device cellular units parallel with one another, the device cellular unit includes semiconductor substrate, in the device cellular list
In first cross-wise direction, collector electrode metal 12, p-type collector 1, N-type cutoff layer 2, N-type drift layer 3 are set gradually from bottom to top,
Top in the N-type drift layer 3 is equipped with the area PXing Ti 5, groove 13 and the N-type emitter 4 positioned at 5 internal upper part of the area PXing Ti, institute
The area ShuPXing Ti 5, N-type emitter 4 are adjacent with 13 side of groove, and the other side of groove 13 is the area dummy (i.e. holoe carrier
Injection region), the polysilicon gate 6 wrapped up by the first oxide layer 7 and 11 side of the second oxide layer, position are equipped in the groove 13
In the semi-enclosed shield grid 10 of the semi-surrounding polysilicon gate 6 in 7 outside of the first oxide layer, semi-enclosed 10 quilt of shield grid
Second oxide layer 11 package, second oxide layer 11 are close to 13 inner wall of groove；Second oxide layer 11 is close to polysilicon gate
The side of pole 6 is gate oxide；
The semi-enclosed shield grid 10 is distributed in side of the polysilicon gate 6 far from N-type emitter 4 and below, and described
The first oxide layer 7, semi-enclosed shielding are passed sequentially through between side of the polysilicon gate 6 far from N-type emitter 4 and N-type drift layer 3
Grid 10, the second oxide layer 11 interval, are isolated between the polysilicon gate 6 and semi-enclosed shield grid 10 by the first oxide layer 7；
Successively be covered with oxide protective layer 8, emitter metal 9 on the N-type drift layer 3, the emitter metal 9 with it is described
The area PXing Ti 5,4 Ohmic contact of N-type emitter, the semi-enclosed shield grid 10 are electrically connected with emitter metal 9, the polycrystalline
It is isolated between silicon gate 6 and emitter metal 9 by oxide protective layer 8；
N-type cutoff layer 2, p-type collector 1 and collector electrode metal 12, the current collection are successively arranged below the N-type drift layer 3
Pole metal 12 and 1 Ohmic contact of p-type collector.
A kind of manufacturing method of the semi-enclosed shield grid IEGT device architecture of N-type of the embodiment of the present invention 1, including walk as follows
It is rapid:
As shown in Fig. 2, step 1: choosing semiconductor substrate, the semiconductor substrate includes N-type drift layer 3, using etching work
Skill performs etching the upper surface of the N-type drift layer 3 to obtain several grooves 13；
As shown in figure 3, step 2: forming the second oxide layer 11, and the continued growth in groove 13 by oxidation in groove 13
Polysilicon, the polysilicon fill up groove 13；
As shown in figure 4, step 3: being performed etching using etching technics to the polysilicon in groove 13, at the side of groove 13 quarter
Erosion obtains internal channel 14, while obtaining semi-enclosed shield grid 10 in the lower section of groove 13 and the other side；
As shown in figure 5, step 4: forming the first oxide layer 7 by oxidation, and continued growth is more wherein in internal channel 14
Crystal silicon simultaneously fills up internal channel 14, and polysilicon gate 6 is obtained in internal channel 14；
As shown in fig. 6, the 5th step；Using photoetching process, in 3 surface Selective implantation p type impurity of N-type drift layer and trap is pushed away, shape
At the area PXing Ti 5, the area PXing Ti 5 is located at the side of groove 13 and adjoining；
As shown in fig. 7, step 6:, in 3 surface Selective implantation N-type impurity of N-type drift layer, high temperature pushes away trap using photoetching process
After obtain N-type emitter 4, then deposited oxide protective layer 8；N-type emitter 4 is located in the area PXing Ti 5 at this time, and with groove 13
It is adjacent；
As shown in figure 8, step 7: using etching technics, selectivity performs etching oxide protective layer 8, N-type emitter 4, until dew
The area ChuPXing Ti 5 obtains the metal contact hole for drawing grid and emitter；
Here photoetching process can also be reused, in 5 surface Selective implantation p type impurity of the area PXing Ti, is formed for improving gold
The P type trap zone of 5 Ohmic contacts in the area Shu YuPXing Ti；
As shown in figure 9, step 8: metallic aluminium fills up metal contact hole, and formation is for drawing hair in device front deposited metal aluminium
The emitter metal 9 of emitter-base bandgap grading；
As shown in Figure 10, step 9: being implanted sequentially N-type impurity, p type impurity at the device back side, N-type cutoff layer 2, P are respectively formed
Type collector 1, what this was well known to those skilled in the art, it repeats no more；
Step 10: the deposited metal aluminium on the p-type collector 1, forms the collector electrode metal 12 for drawing collector, complete
Manufacture semi-enclosed shield grid IEGT.
The present invention will be sealed partly by being provided with the semi-enclosed shield grid 10 of semi-surrounding outside polysilicon gate 6
Enclosed shield grid 10 is electrically connected to N-type emitter 9(and is connected to zero potential)；In device opening process, polysilicon gate 6 adds
Forward voltage, semi-enclosed shield grid 10 connect zero potential, when the area dummy (region that N-type drift layer 3 is located at 13 side of groove) has
When transverse current flows through, and it can be eliminated when induced current is flowed through from semi-enclosed shield grid 10, therefore, Bu Huiying
The grid voltage variation for avoiding transverse current generation to the voltage condition on segregate polysilicon gate 6 is rung, grid are eliminated
The phenomenon that pole tension overshoots；For same device in turn off process, transverse current is same when flowing through from semi-enclosed shield grid 10
It can be eliminated, so that device possesses higher anti-collector voltage and shakes the ability influenced on grid, guarantee device normal turn-off；
Further, since grid (i.e. polysilicon gate 6) and collector has been isolated in semi-enclosed shield grid 10, it therefore reduces grid
The contact area of pole and collector, and then miller capacitance (Cgd) is greatly reduced, faster, switching loss is smaller for switching speed.
The present invention and its embodiments have been described above, description is not limiting, it is shown in the drawings also only
It is one of embodiments of the present invention, practical structures are not limited thereto.All in all if those skilled in the art
It is enlightened by it, without departing from the spirit of the invention, is not inventively designed similar with the technical solution
Frame mode and embodiment, are within the scope of protection of the invention.
Claims (7)
1. a kind of semi-enclosed shield grid IEGT device architecture, including active area, the active area include that several are parallel with one another
Device cellular unit, the device cellular unit includes semiconductor substrate, in the device cellular unit cross-wise direction, institute
Stating semiconductor substrate includes the first conduction type drift layer (3), and the top in the first conduction type drift layer (3) is equipped with
Second conductivity type body region (5), groove (13) and the first conduction type transmitting for being located at the second conductivity type body region (5) internal upper part
Pole (4), second conductivity type body region (5), the first conduction type emitter (4) are adjacent with groove (13) side, special
Sign is, the polysilicon gate wrapped up by the first oxide layer (7) and the second oxide layer (11) side is equipped in the groove (13)
Pole (6), the semi-surrounding polysilicon gate (6) being located on the outside of the first oxide layer (7) semi-enclosed shield grid (10), described half seals
Enclosed shield grid (10) is wrapped up by the second oxide layer (11), and second oxide layer (11) is close to groove (13) inner wall.
2. a kind of semi-enclosed shield grid IEGT device architecture according to claim 1, which is characterized in that described semiclosed
Formula shield grid (10) is distributed in the side and below of polysilicon gate (6) far from first conduction type emitter (4), and described
It is passed sequentially through between the side and the first conduction type drift layer (3) of the separate first conduction type emitter (4) of polysilicon gate (6)
First oxide layer (7), semi-enclosed shield grid (10), the second oxide layer (11) interval.
3. a kind of semi-enclosed shield grid IEGT device architecture according to claim 1, which is characterized in that described first
Successively be covered with oxide protective layer (8), emitter metal (9) on conduction type drift layer (3), the emitter metal (9) with
Second conductivity type body region (5), first conduction type emitter (4) Ohmic contact, the semi-enclosed shield grid (10)
It is electrically connected with emitter metal (9).
4. a kind of semi-enclosed shield grid IEGT device architecture according to claim 1, which is characterized in that described first
The first conduction type cutoff layer (2), the second conduction type collector (1) and collection are successively arranged below conduction type drift layer (3)
Electrode metal (12), the collector electrode metal (12) and second conduction type collector (1) Ohmic contact.
5. a kind of semi-enclosed shield grid IEGT device architecture according to claim 1, which is characterized in that second oxygen
Changing layer (11) to be close to the side of polysilicon gate (6) is gate oxide.
6. a kind of manufacturing method of semi-enclosed shield grid IEGT device architecture, which comprises the steps of:
Step 1: choosing semiconductor substrate, the semiconductor substrate includes the first conduction type drift layer (3), using etching work
Skill performs etching the upper surface of the first conduction type drift layer (3) to obtain several grooves (13)；
Step 2: forming the second oxide layer (11) by oxidation, and in the interior continued growth polycrystalline of groove (13) in groove (13)
Silicon, the polysilicon fill up groove (13)；
Step 3: performing etching the polysilicon in groove (13) using etching technics, etch to obtain in the side of groove (13)
Internal channel (14), while semi-enclosed shield grid (10) are obtained in the lower section of groove (13) and the other side；
Step 4: form the first oxide layer (7) by oxidation in the internal channel (14), and continued growth polysilicon is simultaneously wherein
Internal channel (14) are filled up, obtain polysilicon gate (6) in internal channel (14)；
5th step；Using photoetching process, in first conduction type drift layer (3) surface the second conductive type impurity of Selective implantation
And trap is pushed away, it is formed the second conductivity type body region (5)；
Step 6: using photoetching process, it is miscellaneous in first conduction type drift layer (3) surface the first conduction type of Selective implantation
Matter, high temperature obtain the first conduction type emitter (4) after pushing away trap, then deposited oxide protective layer (8)；
Step 7: selectively being carved to oxide protective layer (8), the first conduction type emitter (4) using etching technics
Erosion, until exposing the second conductivity type body region (5)；
Step 8: being formed emitter metal (9) in device front deposited metal aluminium；
Step 9: being implanted sequentially the first conductive type impurity, the second conductive type impurity at the device back side, it is respectively formed first and leads
Electric type cutoff layer (2), the second conduction type collector (1)；
Step 10: the deposited metal aluminium on the second conduction type collector (1), forms collector electrode metal (12), system is completed
Make semi-enclosed shield grid IEGT.
7. a kind of semi-enclosed shield grid IEGT device architecture according to claim 1 or 6 and its manufacturing method, feature
It is, for N-type shield grid IEGT device, first conduction type is that N-type is conductive, and second conduction type is led for p-type
Electricity；For p-type shield grid IEGT device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
Priority Applications (1)
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| CN114256342A (en) * | 2020-09-24 | 2022-03-29 | 比亚迪半导体股份有限公司 | Semiconductor cellular structure, IGBT cellular structure, semiconductor structure and preparation method thereof |
| WO2023093132A1 (en) * | 2021-11-23 | 2023-06-01 | 无锡华润华晶微电子有限公司 | Iegt structure and method for manufacturing same |
| CN117650164A (en) * | 2023-10-31 | 2024-03-05 | 海信家电集团股份有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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