CN111668178B

CN111668178B - Packaging structure and manufacturing method thereof

Info

Publication number: CN111668178B
Application number: CN201910238011.6A
Authority: CN
Inventors: 陈明志; 徐宏欣; 蓝源富; 许献文
Original assignee: Powertech Technology Inc
Current assignee: Powertech Technology Inc
Priority date: 2019-03-08
Filing date: 2019-03-27
Publication date: 2022-06-10
Anticipated expiration: 2039-03-27
Also published as: TW202034485A; CN111668178A

Abstract

The invention provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises a chip, a sealing colloid and a rewiring layer. The chip comprises at least two integrated circuit units and a dummy portion, wherein the dummy portion separates the integrated circuit units and does not electrically connect the integrated circuit units with each other. The sealing colloid is arranged on the chip and surrounds the chip. The rewiring layer is arranged on the sealing colloid and is electrically connected with the integrated circuit unit.

Description

Packaging structure and manufacturing method thereof

Technical Field

The present disclosure relates to package structures and, particularly, to a package structure and a method for fabricating the same.

Background

With the miniaturization and multi-functionalization of electronic products, multi-chip package structures are becoming more common in many electronic products, where two or more chips are packaged in a single package structure to reduce the overall size. For fan-out type packaging, a common multi-chip packaging structure is to arrange more than two chips side by side on the same carrier plate, then wrap the chips with packaging glue, and then form a redistribution layer on the packaging glue to electrically connect the chips, but considering the process error of the die bonder, the ability of the packaging glue to fill the gaps between the chips and the reliability of thermal expansion, a design limit exists between the chips arranged side by side, so that the area of the packaging structure is limited and cannot be further reduced, and the area of the packaging structure is increased along with the increase of the number of the chips. Accordingly, it is an objective of the industry to reduce the volume of the package structure.

Disclosure of Invention

The invention aims to provide a packaging structure and a manufacturing method thereof, so as to reduce the volume of a fan-out type packaging structure.

To achieve the above objective, the present invention provides a package structure, which includes a first chip, a molding compound, and a redistribution layer. The first chip comprises at least two integrated circuit units and a virtual part, wherein the virtual part separates the integrated circuit units, and the virtual part does not electrically connect the integrated circuit units with each other. The sealing colloid is arranged on the first chip and surrounds the first chip. The rewiring layer is arranged on the sealing colloid and is electrically connected with the integrated circuit unit.

To achieve the above object, the present invention provides a method for manufacturing a package structure, comprising: providing a chip wafer, wherein the chip wafer comprises a plurality of integrated circuit units; cutting the chip wafer to form a plurality of first chips, wherein each first chip comprises at least two of the integrated circuit units and a virtual part, the virtual part separates the integrated circuit units, and the virtual part does not electrically connect the integrated circuit units with each other; arranging one of the first chips on a carrier plate; forming a sealing colloid on the first chip; forming a rewiring layer on the sealing colloid, wherein the rewiring layer is electrically connected with the integrated circuit unit; and removing the carrier plate.

In the package structure and the manufacturing method disclosed by the invention, through the design of the first chip with at least two integrated circuit units, the space between the integrated circuit units can be reduced, so that the volume of the package structure can be effectively reduced. Moreover, through the design, the manufacturing cost and the manufacturing procedure of the packaging structure can be effectively reduced, and further the cost is saved.

Drawings

Fig. 1 to 6 are schematic diagrams illustrating a method for fabricating a package structure according to a first embodiment of the invention;

fig. 7 is a schematic cross-sectional view illustrating a package structure according to a second embodiment of the invention.

Description of the symbols:

100. 200 packaging structure;

102 a chip wafer;

104 an integrated circuit unit;

106 cutting a channel;

106a first cutting line;

106b second cutting path;

106c a third cutting lane;

108 a first chip;

108P dummy portion;

110 carrier plates;

112 a release layer;

114 sealing colloid;

116 a bump;

118a rewiring layer;

118a lower electrode;

118a1, 118a2 lower electrode group;

118b interconnect;

118c an upper electrode;

118S1, 118S2 surface;

120 solder balls;

222 a second chip;

a first direction D1;

a second direction D2;

a TP test pad;

an AM alignment mark;

g1, G2 spacing;

an IN insulating layer;

a V channel;

a CL conductive layer.

Detailed Description

Fig. 1 to 6 are schematic diagrams illustrating a method for fabricating a package structure according to a first embodiment of the invention, wherein fig. 1 to 3 are schematic diagrams illustrating a structure of the package structure at different steps, fig. 3 is a schematic diagram illustrating a cross-sectional view along a line a-a ' of fig. 2, fig. 4 is a schematic diagram illustrating a bottom surface of the package structure according to the first embodiment of the invention, and fig. 5 and 6 are schematic diagrams illustrating a cross-sectional view of the package structure along lines B-B ' and C-C ' of fig. 4, respectively. The method for fabricating a package structure provided in this embodiment includes the following steps. As shown in fig. 1, first, a chip wafer 102 is provided, wherein the chip wafer 102 includes a plurality of integrated circuit units 104. Specifically, the chip wafer 102 may be an integrated circuit unit 104 that has been formed with a specific function. In the present embodiment, the integrated circuit units 104 may have the same structure, that is, each integrated circuit unit 104 is a functional unit having the same function and structure. For example, each integrated circuit unit 104 may be a memory device, such as a Dynamic Random Access Memory (DRAM), a Flash memory (Flash), or other suitable memory.

In the present embodiment, the chip wafer 102 may have a plurality of scribe lines 106 respectively located between two adjacent integrated circuit units 104 for separating the integrated circuit units 104 from each other. After the chip wafer 102 is formed, each ic unit 104 in the chip wafer 102 can be inspected, and whether each ic unit 104 is good or bad is recorded in the inspection machine to indicate the position of each functional ic unit 104, thereby facilitating the subsequent dicing of the first chip 108.

Next, a dicing process is performed on the chip wafer 102 to dice the chip wafer 102 along the partial dicing streets 106, thereby forming a plurality of first chips 108. Specifically, since each ic unit 104 can be known to be good or not in the inspection process, the machine can record the position of the ic unit 104 determined to be good, so that the dicing program in the machine can regard at least two adjacent ic units 104 determined to be good as the same first chip 108, and separate the first chip 108 from other portions of the chip wafer 102 along the dicing lane 106 around the first chip 108. For example, the scribe line 106 may include a plurality of first scribe lines 106a extending along the first direction D1, a plurality of second scribe lines 106b extending along the second direction D2, and a plurality of third scribe lines 106c, wherein the first and

second scribe lines

106a and 106b may surround the first chip 108, and the third scribe lines 106c are located between the ic cells 104 of the first chip 108. In the dicing process, no dicing is performed along the third dicing street 106c, so the first chip 108 may include dummy portions 108P corresponding to the positions of the third dicing street 106c, and the dummy portions 108P may connect adjacent integrated circuit cells 104 in the first chip 108. For clarity, the first chip 108 is shown, the first chip 108 of the embodiment includes two adjacent integrated circuit units 104, and therefore the third scribe line 106c between the integrated circuit units 104 is not cut, but is not limited thereto. Since the third scribe line 106c of the present embodiment does not need to be cut, compared to the method of cutting each scribe line, the cutting process of the present embodiment can save the cutting time, thereby improving the cutting efficiency. In the present embodiment, the ic units 104 of the first chip 108 may be arranged along a narrower side direction (e.g., the second direction D2) of the ic units 104, and thus the third scribe line 106c may extend along the first direction D1, but is not limited thereto. In some embodiments, the third scribe line 106c may be defined according to the range of the first chip 108, so the third scribe line 106c may also extend along the second direction D2, or different third scribe lines 106c may extend along the first direction D1 and the second direction D2, respectively. In some embodiments, as shown in fig. 2, the dummy portion 108P of the first chip 108 may include a test pad TP, an alignment mark AM, or other elements that do not affect the final package structure 100. In some embodiments, the test pads TP may be used to detect different integrated circuit units 104, but not limited thereto.

In the present embodiment, the dicing process may include, for example, a laser grooving process and a wafer dicing process, wherein the laser grooving process may cut off a portion of the film layer of the chip wafer 102 located in the first scribe line 106a and the second scribe line 106b, such as a low dielectric constant (low-k) film, a metal layer or a material difficult to be cut off by a dicing blade, such as aluminum nitride, gallium nitride, alumina ceramic or silicon carbide, and the wafer dicing process may include fully dicing the chip wafer 102 by the dicing blade. In some embodiments, the cutting process may also be one or more laser cutting processes. The cutting process of the present invention is not limited to the above, and may be other suitable cutting processes.

In some embodiments, the first chip 108 may also include three or more than four integrated circuit units 104 according to actual requirements. In some embodiments, the integrated circuit cells 104 in the first chip 108 may have different structures and different functional cells, such as different memory elements or different functional integrated circuits, respectively.

It should be noted that the dummy portion 108P of the present embodiment does not electrically connect the adjacent integrated circuit units 104 to each other, that is, the dummy portion 108P does not have any circuit to electrically connect the integrated circuit units 104 in the first chip 108 to each other, so that the integrated circuit units 104 in the first chip 108 are still insulated from each other when no subsequent process is performed. In some embodiments, the dummy portions 108P may also electrically connect the integrated circuit units 104 in the first chip 108 to each other.

As shown in fig. 2 and fig. 3, after the first chips 108 are formed, a die bonding process is performed to dispose one of the first chips 108 on a carrier 110, wherein the carrier 110 is a temporary carrier, such as a glass substrate. Specifically, the carrier substrate 110 may be formed with a release layer 112 to facilitate the removal of the carrier substrate 110 in a subsequent process. Moreover, the surface of the first chip 108 opposite to the pad (not shown) thereof may face the release layer 112. In some embodiments, the first chip 108 may be bonded to the release layer 112 by a high temperature resistant bonding material, for example, during the die bonding process, so as to prevent the first chip 108 from bending in the subsequent processes. It should be noted that, since the first chip 108 of the present embodiment includes at least two ic units 104, compared to the method of disposing at least two chips each having one ic unit on the carrier, the design of the first chip 108 of the present embodiment can effectively reduce the number and the number of times of disposing the chips, thereby improving the production efficiency of the die attach process.

Then, a molding process is performed to form an encapsulant 114 on the first chip 108 and the release layer 112, such that the encapsulant 114 covers the first chip 108. In some embodiments, the bumps 116 may be formed on the pads of the first chip 108 before the molding process. Then, the molding compound 114 is polished until the bumps 116 are exposed. The molding compound 114 may, for example, comprise a molding resin (molding compound) or other suitable molding material. In some embodiments, the bump 116 may not be exposed by the polishing process, and a through hole may be formed in the molding compound 114 on the bump 116 after the polishing process to expose the bump 116. In some embodiments, no bump may be formed on the bonding pad of the first chip 108, in which case the polishing process is performed until the bonding pad of the first chip 108 is exposed.

After the bumps 116 or the pads of the first chip 108 are exposed, the redistribution layer 118 is formed on the molding compound 114, such that the redistribution layer 118 is electrically connected to the integrated circuit units 104 in the first chip 108 through the bumps 116, and the integrated circuit units 104 are electrically connected to each other through the redistribution layer 118. In the embodiment, the redistribution layer 118 may include a plurality of lower electrodes 118a, a plurality of interconnects 118b, and a plurality of upper electrodes 118c, the lower electrodes 118a are exposed on a surface 118S1 of the redistribution layer 118 facing the first chip 108, the upper electrodes 118c are located on another surface 118S2 of the redistribution layer 118 opposite to the surface 118S1, and the interconnects 118b are disposed between the lower electrodes 118a and the upper electrodes 118c, such that the lower electrodes 118a may be electrically connected to the upper electrodes 118c through the interconnects 118 b. In some embodiments, the bottom electrodes 118a may or may not be electrically connected to the top electrodes 118c in a one-to-one manner, that is, the number of the bottom electrodes 118a, the number of the interconnects 118b, the number of the top electrodes 118c, and the connection manner thereof may be determined according to actual requirements. IN some embodiments, the redistribution layer 118 may include a plurality of insulating layers IN, vias (via) V and a plurality of conductive layers CL, wherein each insulating layer IN may have a plurality of through holes, the vias V may be formed IN the through holes for electrical connection IN the vertical direction, and the conductive layers CL may be formed between the insulating layers IN for electrical connection IN the horizontal direction. For example, the bottom electrode 118a may be formed by a channel V IN the insulation layer IN closest to the molding compound 114, the top electrode 118c may be formed by the top conductive layer CL, the top electrode 118c may be exposed by a through hole of the top insulation layer IN, and the interconnection 118b may be formed by the channel V and the conductive layer CL between the bottom electrode 118a and the top electrode 118c, but the design of the redistribution layer 118 of the present invention is not limited thereto.

As shown in fig. 4 to 6, after the redistribution layer 118 is formed, the release layer 112 and the carrier board 110 are removed. Subsequently, solder balls 120 are disposed on the top electrodes 110c to facilitate the package structure 100 to be attached to other components or circuit boards in a subsequent process. Thus, the package structure 100 of the present embodiment can be formed. In some embodiments, after forming the redistribution layer 118, the solder balls 120 may be disposed on the upper electrodes 110c, and then the release layer 112 and the carrier substrate 110 are removed. In some embodiments, between forming the redistribution layer 118 and disposing the solder balls 120, other redistribution layers, other package structures, or other chips may be disposed on the redistribution layer 118.

It should be noted that, since the carrier 110 of the embodiment is only provided with a single first chip 108 (i.e., there is no gap between the integrated circuit units 104), when the molding compound 114 is formed, the design of the first chip 108 can avoid the existence of a gap with a small width, which is helpful for the molding material to quickly cover the first chip 108, thereby avoiding the generation of bubbles between the integrated circuit units 104 and improving the reliability (reliability) of the package structure 100. In addition, in the package structure 100 of the embodiment, since the integrated circuit units 104 in the first chip 108 are not separated in the dicing process, the distance G1 between the integrated circuit units 104 can be close to the width of the dicing street 106, so that the distance G1 can be smaller than the design limit of the chip distance in the die attach process, for example, smaller than 300 μm. For example, the spacing G1 may be less than or equal to 65.6 microns. As a result, the area of the package structure 100 of the present embodiment can be effectively reduced compared to a package structure in which two chips each having one integrated circuit unit are packaged. Moreover, since the distance G1 between the integrated circuit units 104 can be smaller than the design limit of the chip distance, the connection path of the integrated circuit units 104 can be shortened, thereby improving the electrical performance of the package structure 100 and reducing the power consumption.

In the present embodiment, since the pitch G1 of the integrated circuit cells 104 of the present embodiment can be reduced, the minimum pitch of the bottom electrodes 118a of the redistribution layer 118 electrically connecting different integrated circuit cells 104 can also be reduced. Specifically, the bottom electrode 118a of the redistribution layer 118 can be divided into at least two bottom electrode groups 118a1, 118a2, wherein the bottom electrode groups 118a1, 118a2 are electrically connected to different integrated circuit units 104, respectively, and the distance G2 between the bottom electrode groups 118a1, 118a2 can be smaller than the design limit of the chip distance. For example, the gap G2 may be less than 300 microns, or even further less than or equal to 65.6 microns. The minimum pitch of the bumps 116 electrically connecting the different integrated circuit cells 104 is close to the pitch G2 of the bottom electrode groups 118a1, 118a2, and thus can be reduced.

The package structure and the manufacturing method thereof of the present invention are not limited to the above embodiments, and other embodiments of the present disclosure will be further described below. For convenience of comparing the embodiments and simplifying the description, the same elements will be labeled with the same reference numerals, and the differences between the different embodiments will be described in detail below, and the description of the same parts will not be repeated.

Fig. 7 is a schematic cross-sectional view of a package structure according to a second embodiment of the invention. As shown in fig. 7, the difference between the package structure 200 of the present embodiment and the first embodiment is that the package structure 200 of the present embodiment may further include a second chip 222 disposed between the dummy portion 108P of the first chip 108 and the molding compound 114. Specifically, as shown in fig. 7, the manufacturing method of the package structure 200 of the present embodiment is different from that of the first embodiment in that a gap between the first chip 108 and the molding compound 114 is formed, and a second chip 222 is disposed on the dummy portion 108P. The second chip 222 may be the same as or different from the first chip 108 according to actual requirements. For example, since there is no gap between the integrated circuit units 104 of the first chip 108, there is no gap under the second chip 222, so that the molding material does not need to fill the gap with a small width and under the second chip 222 in the molding process, thereby reducing the generation of bubbles and facilitating the addition of the molding material to cover the first chip 108 and the second chip 222.

In summary, in the package structure and the manufacturing method of the invention, the first chip having at least two integrated circuit units is designed, so that the space between the integrated circuit units can be reduced, and the volume of the package structure can be effectively reduced. Moreover, by the design, the manufacturing cost and the manufacturing procedure of the packaging structure can be effectively reduced, and the cost is further saved.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.

Claims

1. A package structure, comprising:

a first chip including at least two integrated circuit units and a dummy portion, wherein the dummy portion separates the at least two integrated circuit units and the dummy portion does not electrically connect the at least two integrated circuit units to each other;

the sealing colloid is arranged on the first chip and surrounds the first chip;

the rewiring layer is arranged on the sealing colloid and is electrically connected with the at least two integrated circuit units;

the redistribution layer is provided with at least two lower electrode groups, the lower electrode groups are arranged on the surface of the redistribution layer facing the first chip and are respectively electrically connected with a corresponding integrated circuit unit, and the distance between the at least two lower electrode groups is smaller than the design limit of the chip distance;

the redistribution layer further comprises a plurality of interconnections and a plurality of upper electrodes, wherein the upper electrodes are positioned on the other surface of the redistribution layer opposite to the surface, and the interconnections are arranged between the lower electrodes and the upper electrodes, so that the lower electrodes are electrically connected to the upper electrodes through the interconnections.

2. The package structure of claim 1, wherein a pitch between the at least two integrated circuit units is less than a design limit of a chip pitch.

3. The package structure of claim 1, wherein each integrated circuit unit has the same structure.

4. The package structure of claim 1 wherein each integrated circuit unit includes a memory element.

5. The package structure of claim 1, wherein a pitch between the at least two integrated circuit units is less than 300 microns.

6. The package structure of claim 1, further comprising a second chip disposed on the dummy portion.

7. A method for manufacturing a package structure includes:

providing a chip wafer, wherein the chip wafer comprises a plurality of integrated circuit units;

cutting the chip wafer to form a plurality of first chips, wherein each first chip comprises at least two of a plurality of integrated circuit units and a virtual part, the virtual part separates the at least two integrated circuit units, and the virtual part does not electrically connect the at least two integrated circuit units with each other;

arranging one of the first chips on a carrier plate;

forming a sealing colloid on the first chips;

forming a redistribution layer on the encapsulant, wherein the redistribution layer is electrically connected with the at least two integrated circuit units; and

removing the carrier plate;

the redistribution layer is provided with at least two lower electrode groups, the lower electrode groups are arranged on the surface of the redistribution layer facing the first chip and are respectively and electrically connected with a corresponding integrated circuit unit, and the distance between the at least two lower electrode groups is smaller than the design limit of the chip distance;

8. The method of claim 7, further comprising disposing a second chip on the dummy portion before forming the encapsulant.

9. The method for manufacturing a package structure according to claim 7, wherein a pitch between the at least two integrated circuit units is smaller than a chip pitch design limit of a die attach process.