CN111667874A

CN111667874A - Test system

Info

Publication number: CN111667874A
Application number: CN201910165686.2A
Authority: CN
Inventors: 林士杰; 林盛霖
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-03-05
Filing date: 2019-03-05
Publication date: 2020-09-15
Anticipated expiration: 2039-03-05
Also published as: CN111667874B

Abstract

A test system, comprising: the device comprises a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a temporary register. The registers operate as pipeline registers for the memory test circuitry and the output logic circuitry. In the first test mode, the memory test circuit transmits a first test signal to the memory, so that the memory outputs the test signal to the temporary memory and then further transmits the test signal to the memory test circuit or the output logic circuit for testing.

Description

Test system

Technical Field

The present invention relates to testing technologies, and more particularly, to a testing system.

Background

Conventionally, when an embedded static random access memory (eSRAM) is tested, two tests are performed. One is to test the memory using a memory test circuit; the other is to test the circuit function, so that an input logic circuit tests an output logic circuit after the output of the memory, which is also called scan test (scan test). However, in order to perform the above test and the output logic circuit function normally, it is often necessary to provide a plurality of registers (registers) to solve the data error caused by the delay of the memory in the timing sequence. Such an arrangement often increases the hardware cost of the test circuit.

Therefore, how to design a new test system to solve the above-mentioned shortcomings is an urgent problem to be solved in the industry.

Disclosure of Invention

This summary is intended to provide a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and is intended to neither identify key/critical elements of the embodiments nor delineate the scope of the embodiments.

It is an object of the present disclosure to provide a test system, by which the problems of the prior art are ameliorated.

To achieve the above object, one aspect of the present invention relates to a test system, comprising: the device comprises a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The memory is electrically coupled to the memory test circuit. The input logic circuit is electrically coupled to the memory. The bypass circuit is selectively electrically coupled to one of the memory test circuit or the input logic circuit. The register includes an input terminal selectively electrically coupled to one of the memory or the bypass circuit, and an output terminal electrically coupled to the memory test circuit and the output logic circuit, and operates as a pipeline register of the memory test circuit and the output logic circuit. When the test mode is the first test mode, the memory test circuit transmits a first test signal to the memory, the memory outputs the test signal to the temporary storage for temporary storage, and then the test signal is further transmitted to the memory test circuit, so as to test according to the first transmission result.

The test system of the invention can provide a temporary storage mechanism for the output logic circuit, the memory test circuit and the bypass circuit through the setting of the temporary storage, and can greatly reduce the cost of hardware. Furthermore, the test system can test all possible paths among the memory test circuit, the output logic circuit and the bypass circuit through the common path formed by the register, thereby further improving the test coverage.

Drawings

In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description of the preferred embodiments of the invention in which:

FIG. 1 is a block diagram of a test system according to an embodiment of the present invention;

FIG. 2 is a block diagram of the test system of FIG. 1 operating in a first test mode in accordance with an embodiment of the present invention;

FIG. 3 is a block diagram of the test system of FIG. 1 operating in a second test mode or a third test mode according to an embodiment of the present invention; and

FIG. 4 is a diagram illustrating a scan chain according to an embodiment of the invention.

Description of the symbols

1: the test system 100: memory test circuit

102: the memory 104: input logic circuit

105: the comparator 106: bypass circuit

108: output logic circuit 110: temporary storage device

112: multiplexer 114: multiplexer

400: scan chain 402: shift temporary storage device

404: multiplexer 406: combinational logic circuit

ADD1, ADD 2: address signals CLK: clock signal

CTL1, CTL 2: control signal DATA: data signal

DATA1, DATA 2: data signal OOUT: memory output operation signal

OUT: output signal P1: first path

P2: second path P3: third path

P41, P42: fourth path POUT: bypass output test signal

And (2) SCAN: scanning signal SE: selection signal

SEL1, SEL 2: selection signal TOUT: memory output test signal

Detailed Description

Please refer to fig. 1. Fig. 1 is a block diagram of a test system 1 according to an embodiment of the present invention. The test system 1 includes: the memory test circuit 100, the memory 102, the input logic 104, the bypass circuit 106, the output logic 108, the register 110, the multiplexer 112, and the multiplexer 114.

One of the memory test circuit 100 or the input logic circuit 104 is selectively electrically coupled to the memory 102 through the multiplexer 112.

In one embodiment, the multiplexer 112 selects according to a selection signal SEL 1. For example, when the selection signal SEL1 is at the first voltage level, the multiplexer 112 electrically couples the memory test circuit 100 to the memory 102 and the bypass circuit 106. When the selection signal SEL1 is at the second voltage level, the multiplexer 112 electrically couples the input logic 104 to the memory 102 and the bypass circuit 106.

In one embodiment, the memory 102 is, for example but not limited to, an embedded static random access memory (eRAM) configured to store and output signals input through the memory test circuit 100 or the input logic circuit 104.

In one embodiment, memory Test circuit 100 is a Built-in Self Test (BIST) circuit and is configured to generate a set of signals including, for example and without limitation, DATA signal DATA1, address signal ADD1, and control signal CTL1, and pass through multiplexer 112 to memory 102.

In one embodiment, the input logic 104 is configured to generate a set of signals including, for example and without limitation, the DATA signal DATA2, the address signal ADD2, and the control signal CTL2, which are transmitted to the memory 102 through the multiplexer 112.

On the other hand, one of the memory test circuit 100 or the input logic circuit 104 can be selectively electrically coupled to the bypass circuit 106 through the multiplexer 112. Bypass circuit 106 is configured to pass signals passed by memory test circuit 100 or input logic circuit 104 to other circuits. In one embodiment, the bypass circuit 106 only has the function of transmitting signals and does not have a temporary storage mechanism.

The register 110 has an input terminal and an output terminal. Through the multiplexer 114, one of the memory 102 or the bypass circuit 106 can be selectively electrically coupled to the input terminal of the register 110, so that the input terminal of the register 110 receives the signal transmitted from the memory 102 or the bypass circuit 106 for temporary storage.

The output terminal of the register 110 is electrically coupled to the memory test circuit 100 and the output logic circuit 108, so as to further transmit the temporarily stored signal to the memory test circuit 100 and the output logic circuit 108.

In the run mode, the register 110 operates as a pipeline register (pipeline register) of the output logic 108.

In more detail, in the operation mode, the input logic circuit 104 can transmit the input operation signals, such as, but not limited to, the DATA signal DATA2, the address signal ADD2 and the control signal CTL2, to the memory 102 through the multiplexer 112 for storage. The memory 102 further outputs a memory output operation signal OOUT to the register 110 for temporary storage, and then the operation signal OOUT is further transmitted from the register 110 to the output logic circuit 108. Due to the existence of the register 110, the signal received by the output logic circuit 108 is not affected by the delay of the memory 102, and the data error caused by timing error (timing operation) is avoided.

Please refer to fig. 2. Fig. 2 is a block diagram illustrating the test system 1 of fig. 1 operating in a first test mode according to an embodiment of the present invention.

In the first test mode, the first test signal including, but not limited to, the DATA signal DATA1, the address signal ADD1 and the control signal CTL1 is transmitted from the memory test circuit 100 to the memory 102 for storage after being controlled by the selection signal SEL1 via the multiplexer 112. Then, the memory 102 outputs the memory output test signal TOUT, which is transmitted to the register 110 for temporary storage after being controlled by the multiplexer 114 according to the selection signal SEL2, and further transmitted to the memory test circuit 100 or the output logic circuit 108.

Thus, in the first test mode, the register 110 may operate as a pipeline register for the memory test circuit 100 and the output logic 108.

More specifically, the presence of the register 110 prevents the signals received by the memory test circuit 100 and the output logic 108 from being affected by the delay of the memory 102, thereby avoiding data errors caused by incorrect timing.

In one embodiment, the memory test circuit 100 includes a comparator 105 configured to compare the first test signal with a first transmission result transmitted from the register 110 to the memory test circuit 100 to test the memory 102.

In this case, in addition to the memory 102, the first path P1 from the memory 102 to the register 110 and the second path P2 from the register 110 to the memory test circuit 100 can be tested.

Please refer to fig. 3. Fig. 3 is a block diagram illustrating the test system 1 of fig. 1 operating in the second test mode or the third test mode according to an embodiment of the present invention.

In the second test mode, the first test signal including, for example and without limitation, the DATA signal DATA1, the address signal ADD1 and the control signal CTL1 is transmitted from the memory test circuit 100 or the second test signal including, for example and without limitation, the DATA signal DATA2, the address signal ADD2 and the control signal CTL2 is transmitted from the input logic circuit 104 to the bypass circuit 106 after being controlled by the multiplexer 112 according to the selection signal SEL 1.

Then, the bypass circuit 106 outputs the bypass output test signal POUT, and the bypass output test signal POUT is transmitted to the register 110 for temporary storage after being controlled by the multiplexer 114 according to the selection signal SEL2, and the scan test can test the fourth path P41 or P42 from the memory test circuit 100 or the input logic circuit 104 to the bypass circuit 106 and then to the register 110 through the register 110.

In one embodiment, the scan test may send a test signal to the memory test circuit 100 through the register 110 for comparison to test the logic function of the memory test circuit 100 itself.

In this case, in addition to the logic function test of the memory test circuit 100 itself, the second path P2 from the register 110 to the memory test circuit 100 can also be tested.

The scan test may send the scan test signal to the output logic 108 through the register 110, so that the third path P3 from the register 110 to the output logic 108 may be tested.

It should be noted that without register 110, in the second test mode, the test path must be from memory test circuit 100 to memory test circuit 100 through bypass circuit 106, from memory test circuit 100 to output logic circuit 108 through bypass circuit 106, from input logic circuit 104 to memory test circuit 100 through bypass circuit 106, or from input logic circuit 104 to output logic circuit 108 through bypass circuit 106.

However, if there is a register 110, the scan test path can be divided into memory test circuit 100 to register 110, input logic 104 to register 110, register 110 to memory test circuit 100, register 110 to output logic 108. Therefore, in the case of having the register 110, the respective paths are short, and the timing problem is easily overcome in circuit design.

In another embodiment, in the third test mode, the first test signal including, for example, but not limited to, the DATA signal DATA1, the address signal ADD1 and the control signal CTL1 is transmitted from the memory test circuit 100, or the second test signal including, for example, but not limited to, the DATA signal DATA2, the address signal ADD2 and the control signal CTL2 is transmitted from the input logic circuit 104 to the bypass circuit 106, so that the bypass output test signal POUT is output from the bypass circuit 106 to the register 110 for temporary storage, and testing is performed according to the third transmission result, such that the fourth paths P41 and P42 can be tested.

Then, the register 110 outputs the third TEST signal TEST to the memory TEST circuit 100 or the output logic circuit 108 through the connected scan chain (scan chain) for testing according to the fourth transmission result, so that the second path P2 and the third path P3 can be tested. The third TEST signal TEST may be different from the second TEST signal, and the third TEST signal TEST may be input into the register 110 through the scan chain by a host (not shown) outside the TEST system 1.

Please refer to fig. 4. Fig. 4 is a diagram illustrating a scan chain 400 according to an embodiment of the invention.

Scan chain 400 includes a plurality of shift registers (shift registers). Taking the shift register 402 shown in fig. 4 as an example, which operates according to the clock signal CLK, the multiplexer 404 selects the DATA signal DATA as an input in the operation mode according to the selection signal SE, so as to transmit the DATA signal DATA to the combinational logic circuit 406 according to the path shown by the dotted line. Or in the SCAN mode, the SCAN signal SCAN is selected as an input, and the SCAN signal SCAN is transmitted to the next stage of the shift register along the path shown by the thick solid line until the last stage of the shift register generates the output signal OUT.

In one embodiment, the memory test circuit 100, the input logic 104, and the output logic 108 each have at least one internal register. The register 110 may output the third TEST signal TEST as the SCAN signal SCAN through the shift register of the SCAN chain 400 as the output signal OUT, and transmit the output signal OUT to the internal registers included in the memory TEST circuit 100 or the output logic circuit 108, so that the second path P2 and the third path P3 may be tested for correctness.

In some techniques, in order to prevent incorrect timing caused by signal transmission, three registers are required for three paths corresponding to the memory test circuit 100, the output logic circuit 108 and the bypass circuit 106 to provide the technical effect of pipeline registers. In such a configuration, paths that cannot be tested exist among paths separated from each other among the memory test circuit 100, the output logic circuit 108, and the bypass circuit 106, and the test accuracy is reduced.

Therefore, the test system 1 of the present invention can provide the output logic circuit 108 as a pipeline register in the run mode by setting the register 110, and can also provide a temporary storage mechanism for the bypass circuit 106 in addition to the memory test circuit 100 as a pipeline register in the test mode, thereby greatly reducing the hardware cost. Furthermore, through the common path formed by the register 110, the test system 1 can test all possible paths among the memory test circuit 100, the output logic circuit 108 and the bypass circuit 106, including the first path P1, the second path P2, the third path P3 and the fourth path P4, so as to achieve a test coverage (test coverage) improvement.

Although the foregoing embodiments have been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A test system, comprising:

a memory test circuit;

a memory electrically coupled to the memory test circuit;

an input logic circuit electrically coupled to the memory;

a bypass circuit selectively electrically coupled to one of the memory test circuit or the input logic circuit;

an output logic circuit; and

a register including an input selectively electrically coupled to one of the memory and the bypass circuit, and an output electrically coupled to the memory test circuit and the output logic circuit, the register operating as a pipeline register of the memory test circuit and the output logic circuit;

when the test device is in a first test mode, the memory test circuit transmits a first test signal to the memory, the memory outputs a memory output test signal to the temporary storage for temporary storage and then further transmits the memory output test signal to the memory test circuit, and the test is carried out according to a first transmission result.

2. The test system of claim 1, wherein when in the first test mode, a first path from the memory to the register and a second path from the register to the memory test circuit are tested.

3. The test system of claim 1, wherein in a second test mode, the memory test circuit transmits the first test signal or the input logic circuit transmits a second test signal to the bypass circuit, so that the bypass circuit outputs a bypass output test signal to the register for temporary storage, the register further transmits the bypass output test signal to the memory test circuit or the output logic circuit for testing according to a second transmission result;

when in a third test mode, the memory test circuit transmits the first test signal or the input logic circuit transmits the second test signal to the bypass circuit, the bypass circuit outputs the bypass output test signal to the temporary storage for temporary storage, so as to perform testing according to a third transmission result, and the temporary storage transmits a third test signal to the memory test circuit or the output logic circuit through a scan chain, so as to perform testing according to a fourth transmission result.

4. The test system of claim 3, wherein when in the second test mode, the bypass output test signal is buffered by the register and transmitted to the memory test circuit for testing a fourth path from one of the memory test circuit or the input logic circuit to the bypass circuit to the register and a second path from the register to the memory test circuit;

when the bypass output test signal is temporarily stored in the register and then transmitted to the output logic circuit in the second test mode, the bypass output test signal is used for testing the fourth path and a third path from the register to the output logic circuit.

5. The test system of claim 3, wherein when in the third test mode, the third transmission result is used to test a fourth path from one of the memory test circuit or the input logic circuit to the bypass circuit to the register, the fourth transmission result is used to test a second path from the register to the memory test circuit or a third path from the register to the output logic circuit.

6. The test system of claim 3, further comprising a first multiplexer, wherein the first multiplexer is configured to electrically couple the memory to the register in the first test mode and to electrically couple the bypass circuit to the register in the second test mode and the third test mode.

7. The test system of claim 1, further comprising a second multiplexer, wherein the second multiplexer is configured to electrically couple one of the memory test circuit or the input logic circuit to the bypass circuit.

8. The test system of claim 1, wherein the memory test circuit is a built-in self-test circuit.

9. The test system of claim 1, wherein in a run mode, the input logic circuit transmits an input operation signal to the memory to output a memory output operation signal from the memory to the register for temporary storage and further to the output logic circuit, such that the signal received by the output logic circuit is not affected by the delay of the memory.

10. The test system of claim 1, wherein the memory test circuit, input logic circuit and output logic circuit each have at least one internal register.