CN111654276B - Switching value signal control circuit and control method - Google Patents

Switching value signal control circuit and control method Download PDF

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Publication number
CN111654276B
CN111654276B CN202010559707.1A CN202010559707A CN111654276B CN 111654276 B CN111654276 B CN 111654276B CN 202010559707 A CN202010559707 A CN 202010559707A CN 111654276 B CN111654276 B CN 111654276B
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Prior art keywords
triode
field effect
electrically connected
mosfet field
interface
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CN111654276A (en
Inventor
汪亮
袁鹏
王文宇
李爱武
刘勇
邹志强
解苗
唐赛
朱晶亮
肖红
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Hunan Zhongke Electric Co ltd
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Hunan Zhongke Electric Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated

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Abstract

The invention provides a switching value signal control circuit and a control method, wherein the switching value signal control circuit comprises a microprocessor, a first switching tube and a relay, the microprocessor is provided with a first I/O interface, a second I/O interface and a third I/O interface, the control end of the first switching tube is electrically connected with the first I/O interface, a pair of normally open contacts of the relay are connected in a controlled circuit of the switching value signal control circuit, the switching value signal control circuit also comprises a second switching tube and a switching tube driving unit, and the first switching tube, the second switching tube and a relay coil are electrically connected between a first power supply end and ground in series; the switching tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switching tube and a third end electrically connected with the second I/O interface. The invention can avoid the risk of misoperation caused by the output of the unexpected default level signal by the first I/O interface, and safely control the relay.

Description

Switching value signal control circuit and control method
Technical Field
The invention relates to the field of industrial automation control, in particular to a circuit and a method for reliably outputting a switching value signal.
Background
As countries walk into the industrial 4.0 information intelligence era, unmanned, automatic, digital and intelligent control has become the most dominant development trend in the field of industrial field control in recent years, and has almost penetrated into each field in the industrial control field, such as unmanned workshops, unmanned restaurants and other application places; unmanned, automatic, digital and intelligent control is based on the collection and output of a reliable and stable field control system, and the requirements on the precision and accuracy of automatic control are higher and higher, such as analog quantity collection, switching value input signal collection, switching value signal output control and the like.
The main principle diagrams of the traditional switching value signal output control are shown in the following fig. 1 (a) and 1 (b); the state of the transistor or the enhanced MOSFET electronic switch is controlled mainly by configuring the high-low level state of the output I/O port of the microprocessor MCU, so that the power on or power off of the relay coil is achieved, the relay contacts are finally closed or opened, the modes of fig. 1 (a) and 1 (b) have the advantages of high electric isolation and common mode interference resistance, but the two modes have a fatal disadvantage, when the microprocessor is in an uncertain state or an uncontrolled state in the power on and power off process, the default state of the I/O port of each microprocessor chip is different in the period from the power on to the initialization of the switching value signal output I/O port, the default state of the I/O port of the microprocessor chip is high, and the default state of the I/O port of the microprocessor chip is low. Since the default level is not controllable, the adaptive setting can be performed only for different microprocessors to avoid the malfunction. However, since the default levels of the different microprocessors are different, if the corresponding settings are made for each microprocessor, the production efficiency is greatly affected.
Disclosure of Invention
The invention aims to solve the problems that the default states of I/O ports of different microprocessors are different and uncontrolled in the power-on and power-off processes, so that the traditional switching value signal control circuit is easy to generate switching value signal misoperation in the process to bring fatal harm to the stability, safety and reliability of a control system, and provides the switching value signal control circuit and a control method.
In order to solve the technical problems, the invention adopts the following technical scheme: the switching value signal control circuit comprises a microprocessor, a first switching tube and a relay, wherein the microprocessor is provided with a first I/O interface, a second I/O interface and a third I/O interface, the control end of the first switching tube is electrically connected with the first I/O interface, and a pair of normally open contacts of the relay are connected in a controlled circuit of the switching value signal control circuit;
The method is characterized in that: the switching value signal control circuit further comprises a second switching tube and a switching tube driving unit, and the first switching tube, the second switching tube and the relay coil are electrically connected between the first power supply end and the ground in series;
The switching tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switching tube and a third end electrically connected with the second I/O interface;
The circuit structure of the switching tube driving unit is that:
(A) When the output of the second I/O interface and the output of the third I/O interface are both in a high level, the switching tube driving unit turns off the second switching tube;
(B) When the output of the second I/O interface and the output of the third I/O interface are both in a low level, the switching tube driving unit turns off the second switching tube;
(C) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, or when the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level and the first switch tube is conducted, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level and the first switch tube is conducted, the switch tube driving unit enables the second switch tube to be conducted.
The applicant has found that although the default status of the I/O ports is different and uncontrolled during power up and power down of different microprocessors, the output level status of the various I/O port output levels during the process is consistent for the same microprocessor, i.e. both high and both low. In the invention, when the output of the second I/O interface and the output of the third I/O interface are default to be high level or default to be low level in the power-on or power-off process, the switch tube driving unit turns off the second switch tube, even if an error level signal is transmitted to the first switch tube due to the default output level of the first I/O interface, the relay coil is not conducted due to misoperation because the first switch tube, the second switch tube and the relay coil are electrically connected in series, thereby avoiding the risk of misoperation caused by the output of an unexpected default level signal by the first I/O interface and effectively protecting the controlled circuit of the switching value signal control circuit. When the outputs of the second I/O interface and the third I/O interface are in opposite levels (one is in a high level and the other is in a low level), the microprocessor is indicated to finish initializing all the I/O interfaces, and at the moment, the relay is controlled by all the I/O interfaces without the risk of misoperation. If the switch tube driving unit is structured such that the second switch tube is turned on only when the outputs of the second I/O interface and the third I/O interface are respectively at a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the output level of the first I/O interface can be used to control the on-off of the first switch tube, and if the first switch tube is turned on, the first switch tube and the second switch tube in the series circuit are turned on to enable the relay to meet the power-on condition, so that the relay can be safely controlled. If the switch tube driving unit is structured such that the second switch tube is turned on when the outputs of the second I/O interface and the third I/O interface are respectively high level and low level and the first switch tube is turned on, or when the outputs of the second I/O interface and the third I/O interface are respectively low level and high level and the first switch tube is turned on, the first switch tube and the second switch tube in the series loop are turned on, so that the relay can meet the power-on condition, and the relay can be safely controlled.
Further, the switching tube driving unit is a third switching tube, and the control end, one connecting end and the other connecting end of the third switching tube are respectively corresponding to the first end, the second end and the third end of the switching tube driving unit;
The circuit structure of the third switching tube is that:
(A1) When the output of the second I/O interface and the output of the third I/O interface are at a high level, the third switching tube is turned off, so that the second switching tube is turned off;
(B1) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the third switching tube is turned off, so that the second switching tube is turned off;
(C1) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, the third switch tube is conducted;
(D1) When the third switching tube is conducted, or when the first switching tube and the third switching tube are both conducted, the second switching tube is conducted.
Further, the first switch tube, the second switch tube and the third switch tube are triodes T1, T2 and T3 respectively, the base electrode of each triode is correspondingly a control end of each triode, and the collector electrode and the emitter electrode of the triode T3 are respectively a connecting end and another connecting end of the triode T3;
(a1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, PNP type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly electrically connected with one end of the relay coil and the ground, and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the relay coil and the first power supply end; or (b)
(B1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the ground of the triode T2, and the collector of the triode T2 is electrically connected with the first power supply end through a relay coil; or (b)
(C1) The collector of the triode T1 is electrically connected with the ground through a relay coil, and the collector and the emitter of the triode T2 are correspondingly and electrically connected with the emitter and the first power supply end of the triode T1 respectively; or (b)
(D1) The collector and the emitter of the triode T1 are respectively and correspondingly electrically connected with one end of the relay coil and the first power supply end, and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the relay coil and the ground; or (b)
(E1) The triode T1, the triode T2 and the triode T3 are respectively PNP type, PNP type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the first power supply end of the triode T2, and the collector of the triode T2 is electrically connected with the ground through a relay coil; or (b)
(F1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector of the triode T1 is electrically connected with the first power supply end through the relay coil, and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the ground of the triode T1.
Further, the first switch tube, the second switch tube and the third switch tube are respectively a MOSFET field effect tube Q1, a MOSFET field effect tube Q2 and a MOSFET field effect tube Q3, the grid electrode of each MOSFET field effect tube is respectively a control end of each MOSFET field effect tube, and the drain electrode and the source electrode of each MOSFET field effect tube Q3 are respectively a connecting end and another connecting end of the MOSFET field effect tube Q3;
(a2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the ground, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the relay coil and the first power supply end; or (b)
(B2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect tube Q2, and the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the first power supply end through a relay coil; or (b)
(C2) The drain electrode of the MOSFET field effect tube Q1 is electrically connected with the ground through a relay coil, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are correspondingly and electrically connected with the source electrode of the MOSFET field effect tube Q1 and the first power supply end respectively; or (b)
(D2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of a P-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the first power supply end, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the relay coil and the ground; or (b)
(E2) The drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with the source electrode and the first power supply end of the MOSFET field effect tube Q2, and the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the ground through a relay coil; or (b)
(F2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, a drain electrode of the MOSFET field effect tube Q1 is electrically connected with the first power supply end through a relay coil, and a drain electrode and a source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with a source electrode and ground of the MOSFET field effect tube Q1.
Further, the switching tube driving unit is a logic gate circuit with two logic input ends and one logic output end,
One logic input end, one logic output end and the other logic input end of the logic gate circuit are respectively a first end, a second end and a third end of the logic gate circuit;
the circuit structure of the logic gate circuit is that:
(A2) When the output of the second I/O interface and the output of the third I/O interface are both in high level, the logic gate circuit outputs a first level signal, so that the second switching tube is turned off;
(B2) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the logic gate circuit outputs a first level signal, so that the second switching tube is turned off;
(C2) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, the logic gate circuit outputs a second level signal;
(D2) The second switching tube is turned on when the logic gate circuit outputs a second level signal or when the first switching tube is turned on and the logic gate circuit outputs a second level signal.
Further, the first switch tube and the second switch tube are triodes T1 and T2 respectively, and the base electrode of each triode is the control end of each triode;
(a3) The triode T1 and the triode T2 are respectively NPN type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with one end of the relay coil and the ground, the collector and the emitter of the triode T2 are respectively and correspondingly and electrically connected with the other end of the relay coil and the first power supply end, and the logic gate circuit is a logic exclusive nor gate; or (b)
(B3) The triode T1 and the triode T2 are respectively of NPN type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the ground of the triode T2, the collector of the triode T2 is electrically connected with the first power supply end through a relay coil, and the logic gate circuit is a logic exclusive-OR gate; or (b)
(C3) The triode T1 and the triode T2 are respectively PNP type and PNP type, the collector of the triode T1 is electrically connected with the ground through a relay coil, the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the first power supply end of the triode T1, and the logic gate circuit is a logic exclusive nor gate; or (b)
(D3) The triode T1 and the triode T2 are respectively PNP type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with one end of the relay coil and the first power supply end, the collector and the emitter of the triode T2 are respectively and correspondingly and electrically connected with the other end of the relay coil and the ground, and the logic gate circuit is a logic exclusive-OR gate; or (b)
(E3) The triode T1 and the triode T2 are respectively PNP type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the first power supply end of the triode T2, the collector of the triode T2 is electrically connected with the ground through a relay coil, and the logic gate circuit is a logic exclusive nor gate; or (b)
(F3) The triode T1 and the triode T2 are respectively NPN type and NPN type, the collector of the triode T1 is electrically connected with the first power supply end through a relay coil, the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the ground of the triode T1, and the logic gate circuit is a logic exclusive-OR gate.
Further, the first switch tube and the second switch tube are respectively a MOSFET field effect tube Q1 and a MOSFET field effect tube Q2, and the grid electrodes of the MOSFET field effect tubes are respectively control ends of the MOSFET field effect tubes;
(a4) The MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the ground, the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the relay coil and the first power supply end, and the logic gate circuit is a logic exclusive nor gate; or (b)
(B4) The MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with the source electrode and the ground of the MOSFET field effect tube Q2, the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the first power supply end through a relay coil, and the logic gate circuit is a logic exclusive-OR gate; or (b)
(C4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with ground through a relay coil, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive nor gate; or (b)
(D4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly and electrically connected with one end of the relay coil and the first power supply end, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly and electrically connected with the other end of the relay coil and the ground, and the logic gate circuit is a logic exclusive-OR gate; or (b)
(E4) The MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with the source electrode and the first power supply end of the MOSFET field effect tube Q2, the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the ground through a relay coil, and the logic gate circuit is a logic exclusive nor gate; or (b)
(F4) The MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect tube Q1 is electrically connected with the first power supply end through the relay coil, the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect tube Q1, and the logic gate circuit is a logic exclusive-OR gate.
Further, the first power supply terminal is electrically connected with the positive voltage power supply terminal of the microprocessor.
The invention also provides a switching value signal control method using the switching value signal control circuit, which comprises the following steps: the output signal initialization values of the second I/O interface and the third I/O interface are respectively high level and low level or respectively low level and high level, and the turn-off or turn-on of the second switching tube is controlled by controlling the output level of the first I/O interface, so that the relay coil is controlled to lose or get electricity, and a pair of normally open contacts of the relay are turned off or turned on.
The invention has the advantages and positive effects that: the invention can avoid the risk of misoperation caused by the output of the unexpected default level signal by the first I/O interface, and safely control the relay.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 (a) is a schematic diagram of a prior art transistor switching value output circuit;
FIG. 1 (b) is a schematic diagram of a prior art enhanced MOSFET switching value output circuit;
fig. 2 (a) is a schematic circuit diagram of a switching value signal control circuit according to embodiment 1 of the present invention;
fig. 2 (b) is a schematic circuit diagram of a switching value signal control circuit according to embodiment 2 of the present invention;
fig. 2 (c) is a schematic circuit diagram of a switching value signal control circuit according to embodiment 3 of the present invention;
Fig. 3 is a schematic circuit diagram of a switching value signal control circuit according to embodiment 4 of the present invention;
fig. 4 is a circuit diagram of a switching value signal control circuit according to embodiment 7 of the present invention;
fig. 5 (a) is a schematic diagram showing a partial circuit configuration of a switching value signal control circuit according to embodiment 13 of the present invention;
fig. 5 (b) is a schematic diagram of a part of the circuit configuration of the switching value signal control circuit of embodiment 14 of the present invention;
fig. 5 (c) is a schematic diagram of a part of the circuit configuration of the switching value signal control circuit of embodiment 15 of the present invention;
In the above figures, 1, microprocessor, 2, relay, 3, logic exclusive-or gate, 4, logic exclusive-nor gate.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
How to ensure that the whole-process switching value signal can be stably, reliably and safely output is a key place for reducing misoperation of an industrial automation field control system.
The invention provides a switching value signal control circuit which comprises a microprocessor 1, a first switching tube and a relay 2, wherein the microprocessor 1 is provided with a first I/O interface, a second I/O interface and a third I/O interface, the control end of the first switching tube is electrically connected with the first I/O interface, a pair of normally open contacts (P1 and P2) of the relay 2 are connected in a controlled circuit of the switching value signal control circuit, and the switching value signal control circuit further comprises a second switching tube and a switching tube driving unit. The controlled circuit is turned on or off by a pair of normally open contacts of the relay 2.
The first switching tube, the second switching tube and the relay 2 coil are electrically connected in series between the first power supply end and the ground. The first switching tube, the second switching tube and the relay 2 coil are electrically connected in series between the first power supply end and the ground, and the meaning is that: the two connecting ends of the first switching tube, the two connecting ends of the second switching tube and the two ends of the coil of the relay 2 are all positioned in a series circuit between the first power supply end and the ground.
The switching tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switching tube and a third end electrically connected with the second I/O interface.
The circuit structure of the switching tube driving unit is that:
(A) When the output of the second I/O interface and the output of the third I/O interface are both in a high level, the switching tube driving unit turns off the second switching tube;
(B) When the output of the second I/O interface and the output of the third I/O interface are both in a low level, the switching tube driving unit turns off the second switching tube;
(C) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, or when the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level and the first switch tube is conducted, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level and the first switch tube is conducted, the switch tube driving unit enables the second switch tube to be conducted.
The first I/O interface, the second I/O interface and the third I/O interface are respectively I/O1, I/O2 and I/O3.
The switching tube driving unit is a third switching tube, and a control end, a connecting end and the other connecting end of the third switching tube are respectively corresponding to a first end, a second end and a third end of the switching tube driving unit;
As shown in fig. 2 (a), in embodiment 1, the first switching tube, the second switching tube, and the third switching tube are respectively a triode T1, a triode T2, and a triode T3. The base B1, B2 and B3 of each triode are correspondingly control ends of each triode, the collector C3 and the emitter E3 of the triode T3 are respectively one connecting end and the other connecting end of the triode T3 and are respectively electrically connected with the base B2 and the second I/O interface I/O2 of the triode T2.
The triode T1, the triode T2 and the triode T3 are respectively NPN type, PNP type and NPN type, the collector C1 and the emitter E1 of the triode T1 are respectively and correspondingly and electrically connected with one end of a coil of the relay 2 and the ground GND, and the collector C2 and the emitter E2 of the triode T2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay 2 and the first power supply end VCC.
In this embodiment 1, the structure of the transistor T1, the transistor T2, and the transistor T3 and the connection relationship described above enable:
(A1) When the output of the second I/O interface and the output of the third I/O interface are both in high level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(B1) When the output of the second I/O interface and the output of the third I/O interface are both in a low level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(C1) And when the output of the second I/O interface and the output of the third I/O interface are respectively in a low level and a high level, the triode T3 is conducted. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is finished after the microprocessor 1 is started, namely the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is just started, and two switching tubes connected with the coil of the relay 2 in series are not needed to be used for protection;
(D1) When the triode T3 is conducted, the triode T2 is conducted. If the output level of the I/O1 is high, the transistor T1 is turned on, and at this time, two switching tubes connected in series with the coil of the relay 1 are both turned on, so that the connection or disconnection of a pair of normally open contacts of the relay 1 can be controlled by using the output level of the I/O1.
The relay 2 is connected with a diode D1 in parallel with the coil.
The first power supply terminal VCC may be a positive voltage power supply terminal. Preferably, the first power supply terminal VCC is electrically connected to the positive voltage power supply terminal VDD of the microprocessor 1. The ground GND is commonly grounded to the ground terminal VSS of the microprocessor 1.
T1, T2, T3 are transistors. The PNP triode can be selected from a triode with model number SS8550BBU of the company of the favone, the collector current (Collector Current) I C is-1.5A, and the collector emitter voltage V CE is-25V. The NPN triode can be selected from a triode with model BC81716MFT of a favolte company, the collector current (Collector Current) is 0.8A, the collector emitter voltage V CE is 45V, and the transistors T1, T2 and T3 all work in a switching state. Collector current I C and collector emitter voltage V CE of transistors T1, T2, and T3 are sufficient in a low-current control system of a microprocessor. The I/O port of the microprocessor has the capability of carrying out the current filling and drawing of +/-4 mA, and the I/O port generally outputs 3.3V or 5V level when outputting high level and 0V level when outputting low level. The type of the switching value output relay 2 can be PA1a-5V of a releasing company, rated voltage at two ends of a coil is 5VDC, rated current consumption of the relay is 24mA, and under the condition that the VCC power of a power supply is enough, transistors T1, T2 and T3 are enough to meet the field switching value signal output requirement. The diode D1 is a freewheeling diode for loosening the relay coil, and when the relay coil is in power failure, the diode D1 provides a freewheeling loop for coil energy so as to avoid voltage spike breakdown of the relay coil, and the model of the diode is FDLL4148 of the faerian company.
The microprocessor can be a single chip microcomputer, a DSP, an FPGA and a CPLD control chip, such as TMS320F2812 of TI company.
A first resistor R1 is connected between the base electrode of the triode T1 and the first I/O interface, a second resistor R2 is connected between the base electrode of the triode T2 and the collector electrode of the triode T3, and a third resistor R3 is connected between the base electrode of the triode T3 and the third I/O interface. The resistance values of the first resistor R1, the second resistor R2 and the third resistor R3 can be selected to be 4.7KΩ, 1.5KΩ and 4.7KΩ, so that the current flowing into or out of the I/O port of the microprocessor can be controlled below 4 mA.
The corresponding switching value output method in this embodiment 1 is that, after the microprocessor MCU is powered on and after the initialization is completed, in the process of initializing the I/O port of the microprocessor, I/O1, I/O2 and I/O3 are set to be in a push-pull output state, and in the whole process of outputting the switching value of the microprocessor, I/O3 is set to be in a high level output and I/O2 is set to be in a low level output, when the contacts of the relay 2 need to be controlled to be closed, I/O1 is set to be in a high level, and when the contacts of the relay need to be controlled to be opened, I/O1 is set to be in a low level, so as to control the coil of the relay 2 to lose or get power, so that a pair of normally open contacts of the relay 2 are turned off or on, thereby realizing the control of the controlled circuit.
Example 2
As shown in fig. 2 (b), this embodiment 2 is different from embodiment 1 in that: the triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector C1 and the emitter E1 of the triode T1 are respectively and correspondingly and electrically connected with the emitter E2 and the ground GND of the triode T2, and the collector C2 of the triode T2 is electrically connected with the first power supply end VCC through a coil of the relay 2.
In this embodiment 2, the structure of the transistor T1, the transistor T2, and the transistor T3 and the connection relationship described above enable:
(A1) When the output of the second I/O interface I/O2 and the output of the third I/O interface I/O3 are both in a high level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(B1) When the output of the second I/O interface I/O2 and the output of the third I/O interface I/O3 are both in a low level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(C1) And when the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, the triode T3 is conducted. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is finished after the microprocessor 1 is started, namely the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is just started, and the protection function is not required to be realized by utilizing two switching tubes connected with the coil of the relay 2.
(D1) When the triode T1 and the triode T3 are both conducted, the triode T2 is conducted. After the triode T3 is conducted, the relay 2 can be controlled by utilizing the triode T1, namely the triode T1 is conducted by utilizing the output signal of the I/O1, and at the moment, the triode T2 is conducted under the condition that the conduction condition is met, so that a loop where a coil of the relay 1 is located is conducted, and a pair of normally open contacts are closed. If the output signal of the I/O1 signals the transistor T1 to turn off, it is indicated that the controlled circuit is not expected to turn on at this time, and the loop where the coil of the relay 1 is located cannot be turned on due to the turn-off of the transistor T1 and the turn-off of the transistor T2, so that the controlled circuit cannot be turned on.
The corresponding switching value output method in this embodiment 2 is that after the microprocessor MCU is powered on and after the initialization is completed, in the process of initializing the I/O port of the microprocessor, I/O1, I/O2 and I/O3 are set to be in push-pull output states, and in the whole switching value output operation process of the microprocessor, I/O3 is set to be in low level output and I/O2 is set to be in high level output. When the contact of the relay 2 needs to be controlled to be closed, the I/O1 is set to be high level, and when the contact of the relay needs to be controlled to be opened, the I/O1 is set to be low level, so that the coil of the relay 2 is controlled to be powered off or on, and a pair of normally open contacts of the relay 2 are turned off or on, so that the control of a controlled circuit is realized.
Example 3
As shown in fig. 2 (c), this embodiment 3 is different from embodiment 1 in that: the triode T1, the triode T2 and the triode T3 are PNP type, PNP type and NPN type respectively, the collector of the triode T1 is electrically connected with the ground GND through the coil of the relay 2, and the collector and the emitter of the triode T2 are correspondingly and electrically connected with the emitter of the triode T1 and the first power supply end VCC respectively.
(A1) When the output of the second I/O interface and the output of the third I/O interface are both in high level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(B1) When the output of the second I/O interface and the output of the third I/O interface are both in a low level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(C1) And when the output of the second I/O interface and the output of the third I/O interface are respectively in a low level and a high level, the triode T3 is conducted. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is finished after the microprocessor 1 is started, namely the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is just started, and two switching tubes connected with the coil of the relay 2 in series are not needed to be used for protection;
(D1) When the triode T3 is conducted, the triode T2 is conducted. When the triode T3 is conducted, the triode T2 is conducted. If the output level of the I/O1 is low, the transistor T1 is turned on, and at this time, two transistors connected in series with the coil of the relay 1 are both turned on, so that the output level of the I/O1 can be used to control the transistor T1, thereby controlling the connection or disconnection of a pair of normally open contacts of the relay 1.
The corresponding switching value output method in this embodiment 3 is that, after the microprocessor MCU is powered on and after the initialization is completed, in the process of initializing the I/O port of the microprocessor, I/O1, I/O2 and I/O3 are set to be in a push-pull output state, and in the whole process of outputting the switching value of the microprocessor, I/O3 is set to be in a high level output and I/O2 is set to be in a low level output, when the contacts of the relay 2 need to be controlled to be closed, I/O1 is set to be in a low level, and when the contacts of the relay need to be controlled to be opened, I/O1 is set to be in a high level, so as to control the coil of the relay 2 to lose or get power, so that a pair of normally open contacts of the relay 2 are turned off or on, thereby realizing the control of the controlled circuit.
Examples 4 to 6
As shown in fig. 3, embodiment 4 differs from embodiment 1 in that: the triode T1, the triode T2 and the triode T3 are PNP type, NPN type and PNP type respectively, the collector C1 and the emitter E1 of the triode T1 are correspondingly and electrically connected with one end of the coil of the relay 2 and the first power supply end VCC respectively, and the collector C2 and the emitter E2 of the triode T2 are correspondingly and electrically connected with the other end of the coil of the relay 2 and the ground GND respectively.
Example 5 differs from example 4 in that: the triode T1, the triode T2 and the triode T3 are PNP type, PNP type and NPN type respectively, the collector C1 and the emitter E1 of the triode T1 are correspondingly and electrically connected with the emitter E2 and the first power supply end of the triode T2 respectively, and the collector C2 of the triode T2 is electrically connected with the ground through a coil of the relay 2. The corresponding figures are not shown and can be taken from an analogy to figure 3.
Example 6 differs from example 4 in that: the triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector of the triode T1 is electrically connected with the first power supply end through the coil of the relay 2, and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the ground of the triode T1. The corresponding figures are not shown and can be taken from an analogy to figure 3.
Examples 7 to 12
As shown in fig. 4, embodiment 7 differs from embodiment 1 in that: the first switch tube, the second switch tube and the third switch tube are respectively MOSFET field effect tube Q1, MOSFET field effect tube Q2 and MOSFET field effect tube Q3, the grid electrodes (G1, G2 and G3) of the MOSFET field effect tubes are respectively control ends of the MOSFET field effect tubes, the drain electrode D3 and the source electrode S3 of the MOSFET field effect tube Q3 are respectively one connecting end and the other connecting end of the MOSFET field effect tube Q3, and are respectively and correspondingly and electrically connected with the grid electrodes G2 and I/O2 of the Q2, and the grid electrode G3 is electrically connected with the I/O3. The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode D1 and the source electrode S1 of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the ground GND, and the drain electrode D2 and the source electrode S2 of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the first power supply end VCC.
Example 8 differs from example 7 in that: the MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect tube Q2, and the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the first power supply end through a coil of the relay 2. The corresponding figures are not shown and can be taken from an analogy to figure 4.
Example 9 differs from example 7 in that: the MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect tube Q1 is electrically connected with the ground through a coil of the relay 2, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the source electrode of the MOSFET field effect tube Q1 and the first power supply end. The corresponding figures are not shown and can be taken from an analogy to figure 4.
Example 10 differs from example 7 in that: the MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of a P-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the first power supply end, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the ground. The corresponding figures are not shown and can be taken from an analogy to figure 4.
Example 11 differs from example 7 in that: the MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect tube Q2, and the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the ground through a coil of the relay 2. The corresponding figures are not shown and can be taken from an analogy to figure 4.
Example 12 differs from example 7 in that: the drain electrode of the MOSFET field effect tube Q1 is electrically connected with the first power supply end through a coil of the relay 2, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are correspondingly and electrically connected with the source electrode and the ground of the MOSFET field effect tube Q1 respectively. The corresponding figures are not shown and can be taken from an analogy to figure 4.
In the embodiment of the invention, the P-channel enhancement type MOSFET can adopt FDN5618P of Ansen America, the Drain Current (Drain Current) I D is-1.25A, and the Drain source voltage V DS is-60V. The N-channel enhancement MOSFET can be 2N7002 from Ansen, drain Current (Drain Current) I D is 0.115A, and Drain-source voltage V DS is 60V. The Q1, Q2 and Q3 enhancement MOSFETs all operate in a switching state, and the drain current I D and drain source voltage V DS of Q1, Q2 and Q3 are sufficient for use in a low current control system of a microprocessor.
A first resistor R1 may be disposed between the gate G1 of Q1 and the first I/O interface, a second resistor R2 may be disposed between the gate G2 of Q2 and the drain D3 of Q3, and a third resistor R3 may be disposed between the gate G3 of Q3 and the third I/O interface. And R1, R2 and R3 can be patch resistors with 3K resistance values, and the current flowing into or out of an I/O port of the microprocessor is controlled below 4 mA.
Example 13
This embodiment 13 differs from embodiment 1 in that:
the switching tube driving unit is a logic gate circuit with two logic input ends and one logic output end, and one logic input end, one logic output end and the other logic input end of the logic gate circuit are respectively a first end, a second end and a third end of the logic gate circuit.
The circuit structure of the logic gate circuit is that:
(A2) When the output of the second I/O interface and the output of the third I/O interface are both in high level, the logic gate circuit outputs a first level signal, so that the second switching tube is turned off;
(B2) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the logic gate circuit outputs a first level signal, so that the second switching tube is turned off;
(C2) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, the logic gate circuit outputs a second level signal;
(D2) The second switching tube is turned on when the logic gate circuit outputs a second level signal or when the first switching tube is turned on and the logic gate circuit outputs a second level signal.
The first switch tube and the second switch tube are triodes T1 and T2 respectively, and base electrodes B1 and B2 of the triodes are control ends of the triodes;
The circuit of this embodiment 13 differs from that of embodiment 1 in that the components of fig. 5 (a) are used instead of the devices between the I/O interface and the M2 point of the microprocessor 1 of fig. 2 (a).
In this embodiment 13, the transistors T1 and T2 are NPN and PNP respectively, the collector and emitter of the transistor T1 are electrically connected with one end of the coil of the relay 2 and ground respectively, the collector and emitter of the transistor T2 are electrically connected with the other end of the coil of the relay 2 and the first power supply terminal respectively, and the logic gate circuit is a logic exclusive nor gate 4.
In embodiment 13, the structures of the transistor T1, the transistor T2, and the logically exclusive nor gate 4 and the connection relationships described above enable:
(A2) When the outputs of the second I/O interface and the third I/O interface are both high level, the output of the logic exclusive nor gate 4 is high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(B2) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the output of the logic exclusive nor gate 4 is in high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(C2) When the outputs of the second I/O interface and the third I/O interface are respectively low level and high level or respectively high level and low level, the output of the logic exclusive nor gate 4 is low level. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is finished after the microprocessor 1 is started, namely the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is just started, and two switching tubes connected with the coil of the relay 2 in series are not needed to be used for protection;
(D2) When the output of the logically exclusive nor gate 4 is low, the transistor T2 is turned on. If the I/O1 outputs a high level, the transistor T1 is turned on. At this time, two switching tubes connected in series with the coil of the relay 1 are both on, so that the output level of the I/O1 can be used to control the connection or disconnection of a pair of normally open contacts of the relay 1.
In this embodiment, the xor gate may use HEF4077B, and the xor gate may use 74HCT1G86.
Example 14
The circuit of this embodiment 14 differs from that of embodiment 1 in that the components of fig. 5 (b) are used instead of the components between the I/O interface and the M1 point of the microprocessor 1 of fig. 2 (b).
This example 14 differs from example 13 in that: the triode T1 and the triode T2 are respectively NPN type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the ground of the triode T2, the collector of the triode T2 is electrically connected with the first power supply end VCC through the coil of the relay 2, and the logic gate circuit is a logic exclusive-OR gate 3.
In embodiment 14, the structures of the transistor T1, the transistor T2, and the logic exclusive-or gate 3 and the connection relationships described above enable:
(A2) When the output of the second I/O interface and the output of the third I/O interface are both in high level, the output of the logic exclusive OR gate 3 is in low level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O state just after the microprocessor is started is avoided;
(B2) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the output of the logic exclusive-OR gate 3 is in low level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O state just after the microprocessor is started is avoided;
(C2) When the outputs of the second I/O interface and the third I/O interface are respectively low level and high level or respectively high level and low level, the logic exclusive or gate 3 outputs high level. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is finished after the microprocessor 1 is started, namely the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is just started, and two switching tubes connected with the coil of the relay 2 in series are not needed to be used for protection;
(D2) When the output of the logical exclusive-or gate 3 is at high level and the transistor T1 is turned on, the transistor T2 is turned on. When the I/O1 outputs a high level, the relay 2 can be controlled by the triode T1, namely the triode T1 is conducted by the output signal of the I/O1, and at the moment, the triode T2 is conducted under the condition that the conduction condition is met, so that a loop where a coil of the relay 1 is located is conducted, and a pair of normally open contacts are closed. If the output signal of the I/O1 signals the transistor T1 to turn off, it is indicated that the controlled circuit is not expected to turn on at this time, and the loop where the coil of the relay 1 is located cannot be turned on due to the turn-off of the transistor T1 and the turn-off of the transistor T2, so that the controlled circuit cannot be turned on.
Example 15
The circuit of this embodiment 15 differs from that of embodiment 1 in that the components of fig. 5 (c) are used instead of the components of fig. 2 (c) between the I/O interface and point M3 of the microprocessor 1.
This embodiment 15 differs from embodiment 13 in that: the triode T1 and the triode T2 are respectively PNP type and PNP type, the collector of the triode T1 is electrically connected with the ground through a coil of the relay 2, the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the first power supply end of the triode T1, and the logic gate circuit is a logic exclusive nor gate 4.
In this embodiment 15, the structure of the transistor T1, the transistor T2, the transistor T3 and the connection relationship described above enable:
(A2) When the outputs of the second I/O interface and the third I/O interface are both high level, the output of the logic exclusive nor gate 4 is high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(B2) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the output of the logic exclusive nor gate 4 is in high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and misoperation caused by uncertain and uncontrolled I/O states just after the microprocessor is started is avoided;
(C2) When the outputs of the second I/O interface and the third I/O interface are respectively low level and high level or respectively high level and low level, the output of the logic exclusive nor gate 4 is low level. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is finished after the microprocessor 1 is started, namely the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is just started, and two switching tubes connected with the coil of the relay 2 in series are not needed to be used for protection;
(D2) When the output of the logically exclusive nor gate 4 is low, the transistor T2 is turned on. If the I/O1 output is low, transistor T1 is turned on. At this time, two switching tubes connected in series with the coil of the relay 1 are both on, so that the output level of the I/O1 can be used to control the connection or disconnection of a pair of normally open contacts of the relay 1.
Examples 16 to 18
Example 16 differs from example 13 in that: the triode T1 and the triode T2 are respectively PNP type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with one end of the coil of the relay 2 and the first power supply end, the collector and the emitter of the triode T2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay 2 and the ground, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown and can be seen by analogy with figures 4 and 5 (a).
Example 17 differs from example 13 in that: the triode T1 and the triode T2 are respectively PNP type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the first power supply end of the triode T2, the collector of the triode T2 is electrically connected with the ground through a coil of the relay 2, and the logic gate circuit is a logic exclusive nor gate 4. The corresponding figures are not shown and can be seen by analogy with figures 4 and 5 (a).
Example 18 differs from example 13 in that: the triode T1 and the triode T2 are respectively NPN type and NPN type, the collector of the triode T1 is electrically connected with the first power supply end through the coil of the relay 2, the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the ground of the triode T1, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown and can be seen by analogy with figures 4 and 5 (a).
Examples 19 to 24
Example 19 differs from example 13 in that: the first switch tube and the second switch tube are respectively a MOSFET field effect tube Q1 and a MOSFET field effect tube Q2, and the grid electrodes of the MOSFET field effect tubes are respectively control ends of the MOSFET field effect tubes; the MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the ground, the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the first power supply end, and the logic gate circuit is a logic exclusive nor gate 4. Corresponding figures are not given and can be obtained in analogy with other figures.
Example 20 differs from example 19 in that: the MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect tube Q2, the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the first power supply end through a coil of the relay 2, and the logic gate circuit is a logic exclusive-OR gate 3. Corresponding figures are not given and can be obtained in analogy with other figures.
Example 21 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with ground through a coil of the relay 2, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive nor gate 4.
Example 22 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the first power supply end, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the ground, and the logic gate circuit is a logic exclusive-OR gate 3. Corresponding figures are not given and can be obtained in analogy with other figures.
Example 23 differs from example 19 in that: the MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with the source electrode and the first power supply end of the MOSFET field effect tube Q2, the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the ground through a coil of the relay 2, and the logic gate circuit is a logic exclusive nor gate 4. Corresponding figures are not given and can be obtained in analogy with other figures.
Example 24 differs from example 19 in that: the MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect tube Q1 is electrically connected with the first power supply end through a coil of the relay 2, the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect tube Q1, and the logic gate circuit is a logic exclusive-OR gate 3. Corresponding figures are not given and can be obtained in analogy with other figures.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The foregoing describes the embodiments of the present application in detail, but the description is only a preferred embodiment of the present application and should not be construed as limiting the scope of the application. All equivalent changes and modifications within the scope of the present application are intended to be covered by this patent. Modifications of the application which are equivalent to various embodiments of the application will occur to those skilled in the art upon reading the application, and are within the scope of the application as defined in the appended claims. Embodiments of the application and features of the embodiments may be combined with each other without conflict.

Claims (9)

1. The switching value signal control circuit comprises a microprocessor (1), a first switching tube and a relay (2), wherein the microprocessor (1) is provided with a first I/O interface, a second I/O interface and a third I/O interface, the control end of the first switching tube is electrically connected with the first I/O interface, a pair of normally open contacts of the relay (2) are connected in a controlled circuit of the switching value signal control circuit,
The method is characterized in that: the switching value signal control circuit further comprises a second switching tube and a switching tube driving unit, and the first switching tube, the second switching tube and a coil of the relay (2) are electrically connected in series between the first power supply end and the ground;
The switching tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switching tube and a third end electrically connected with the second I/O interface;
The circuit structure of the switching tube driving unit is that:
(A) When the output of the second I/O interface and the output of the third I/O interface are both in a high level, the switching tube driving unit turns off the second switching tube;
(B) When the output of the second I/O interface and the output of the third I/O interface are both in a low level, the switching tube driving unit turns off the second switching tube;
(C) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, or when the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level and the first switch tube is conducted, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level and the first switch tube is conducted, the switch tube driving unit enables the second switch tube to be conducted.
2. The switching value signal control circuit according to claim 1, wherein: the switching tube driving unit is a third switching tube, and a control end, a connecting end and the other connecting end of the third switching tube are respectively corresponding to a first end, a second end and a third end of the switching tube driving unit;
The circuit structure of the third switching tube is that:
(A1) When the output of the second I/O interface and the output of the third I/O interface are at a high level, the third switching tube is turned off, so that the second switching tube is turned off;
(B1) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the third switching tube is turned off, so that the second switching tube is turned off;
(C1) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, the third switch tube is conducted;
(D1) When the third switching tube is conducted, or when the first switching tube and the third switching tube are both conducted, the second switching tube is conducted.
3. The switching value signal control circuit according to claim 2, wherein: the first switch tube, the second switch tube and the third switch tube are triodes T1, T2 and T3 respectively, the base electrode of each triode is a control end of each triode correspondingly, and the collector electrode and the emitter electrode of each triode T3 are one connecting end and the other connecting end of the triode T3 respectively;
(a1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, PNP type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the ground, and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the first power supply end; or (b)
(B1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the ground of the triode T2, and the collector of the triode T2 is electrically connected with the first power supply end through a coil of the relay (2); or (b)
(C1) The triode T1, the triode T2 and the triode T3 are PNP type, PNP type and NPN type respectively, the collector of the triode T1 is electrically connected with the ground through a coil of the relay (2), and the collector and the emitter of the triode T2 are correspondingly and electrically connected with the emitter and the first power supply end of the triode T1 respectively; or (b)
(D1) The collector and the emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and a first power supply end, and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the ground; or (b)
(E1) The triode T1, the triode T2 and the triode T3 are PNP type, PNP type and NPN type respectively, the collector and the emitter of the triode T1 are correspondingly and electrically connected with the emitter and the first power supply end of the triode T2 respectively, and the collector of the triode T2 is electrically connected with the ground through a coil of a relay (2); or (b)
(F1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector of the triode T1 is electrically connected with the first power supply end through a coil of the relay (2), and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the ground of the triode T1.
4. The switching value signal control circuit according to claim 2, wherein: the first switch tube, the second switch tube and the third switch tube are respectively a MOSFET field effect tube Q1, a MOSFET field effect tube Q2 and a MOSFET field effect tube Q3, the grid electrode of each MOSFET field effect tube is respectively a control end of each MOSFET field effect tube, and the drain electrode and the source electrode of each MOSFET field effect tube Q3 are respectively a connecting end and another connecting end of the MOSFET field effect tube Q3;
(a2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the ground, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the first power supply end; or (b)
(B2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect tube Q2, and the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the first power supply end through a coil of the relay (2); or (b)
(C2) The drain electrode of the MOSFET field effect tube Q1 is electrically connected with the ground through a coil of a relay (2), and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are electrically connected with the source electrode of the MOSFET field effect tube Q1 and the first power supply end correspondingly respectively; or (b)
(D2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of a P-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and a first power supply end, and the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the ground; or (b)
(E2) The drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with the source electrode and the first power supply end of the MOSFET field effect tube Q2, and the drain electrode of the MOSFET field effect tube Q2 is electrically connected with the ground through a coil of a relay (2); or (b)
(F2) The MOSFET field effect tube Q1, the MOSFET field effect tube Q2 and the MOSFET field effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, a drain electrode of the MOSFET field effect tube Q1 is electrically connected with a first power supply end through a coil of a relay (2), and a drain electrode and a source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly electrically connected with a source electrode and ground of the MOSFET field effect tube Q1.
5. The switching value signal control circuit according to claim 1, wherein: the switching tube driving unit is a logic gate circuit with two logic input ends and one logic output end,
One logic input end, one logic output end and the other logic input end of the logic gate circuit are respectively a first end, a second end and a third end of the logic gate circuit;
the circuit structure of the logic gate circuit is that:
(A2) When the output of the second I/O interface and the output of the third I/O interface are both in high level, the logic gate circuit outputs a first level signal, so that the second switching tube is turned off;
(B2) When the output of the second I/O interface and the output of the third I/O interface are both in low level, the logic gate circuit outputs a first level signal, so that the second switching tube is turned off;
(C2) When the output of the second I/O interface and the output of the third I/O interface are respectively high level and low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively low level and high level, the logic gate circuit outputs a second level signal;
(D2) The second switching tube is turned on when the logic gate circuit outputs a second level signal or when the first switching tube is turned on and the logic gate circuit outputs a second level signal.
6. The switching value signal control circuit according to claim 5, wherein: the first switch tube and the second switch tube are triodes T1 and T2 respectively, and the base electrode of each triode is the control end of each triode;
(a3) The triode T1 and the triode T2 are respectively NPN type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with one end of a coil of the relay (2) and the ground, the collector and the emitter of the triode T2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay (2) and the first power supply end, and the logic gate circuit is a logic exclusive nor gate (4); or (b)
(B3) The triode T1 and the triode T2 are respectively NPN type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the ground of the triode T2, the collector of the triode T2 is electrically connected with the first power supply end through a coil of the relay (2), and the logic gate circuit is a logic exclusive-OR gate (3); or (b)
(C3) The triode T1 and the triode T2 are respectively PNP type and PNP type, the collector of the triode T1 is electrically connected with ground through a coil of the relay (2), the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the first power supply end of the triode T1, and the logic gate circuit is a logic exclusive nor gate (4); or (b)
(D3) The triode T1 and the triode T2 are respectively PNP type and NPN type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with one end of a coil of the relay (2) and a first power supply end, the collector and the emitter of the triode T2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay (2) and the ground, and the logic gate circuit is a logic exclusive-OR gate (3); or (b)
(E3) The triode T1 and the triode T2 are respectively PNP type and PNP type, the collector and the emitter of the triode T1 are respectively and correspondingly and electrically connected with the emitter and the first power supply end of the triode T2, the collector of the triode T2 is electrically connected with the ground through a coil of a relay (2), and the logic gate circuit is a logic exclusive nor gate (4); or (b)
(F3) The triode T1 and the triode T2 are respectively NPN type and NPN type, the collector of the triode T1 is electrically connected with the first power supply end through a coil of the relay (2), the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter and the ground of the triode T1, and the logic gate circuit is a logic exclusive-OR gate (3).
7. The switching value signal control circuit according to claim 5, wherein: the first switch tube and the second switch tube are respectively a MOSFET field effect tube Q1 and a MOSFET field effect tube Q2, and the grid electrodes of the MOSFET field effect tubes are respectively control ends of the MOSFET field effect tubes;
(a4) The MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with one end of a coil of the relay (2) and the ground, the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay (2) and the first power supply end, and the logic gate circuit is a logic exclusive nor gate (4); or (b)
(B4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly and electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is electrically connected with the first power supply end through a coil of a relay (2), and the logic gate circuit is a logic exclusive-OR gate (3); or (b)
(C4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with ground through a coil of a relay (2), the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive nor gate (4); or (b)
(D4) The MOSFET field effect tube Q1 and the MOSFET field effect tube Q2 are respectively of a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect tube Q1 are respectively and correspondingly and electrically connected with one end of a coil of the relay (2) and a first power supply end, the drain electrode and the source electrode of the MOSFET field effect tube Q2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay (2) and the ground, and the logic gate circuit is a logic exclusive-OR gate (3); or (b)
(E4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly and electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is electrically connected with ground through a coil of a relay (2), and the logic gate circuit is a logic exclusive nor gate (4); or (b)
(F4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with the first power supply end through a coil of the relay (2), the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive-OR gate (3).
8. The switching value signal control circuit according to claim 1, wherein: the first power supply end is electrically connected with the positive voltage power supply end of the microprocessor (1).
9. A switching value signal control method using the switching value signal control circuit according to any one of claims 1 to 8, characterized in that the switching value signal control method includes: the output signal initialization values of the second I/O interface and the third I/O interface are respectively high level and low level or respectively low level and high level, and the turn-off or turn-on of the second switching tube is controlled by controlling the output level of the first I/O interface, so that the coil of the relay (2) is controlled to be powered off or powered on, and a pair of normally open contacts of the relay (2) are turned off or turned on.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669783A (en) * 1992-08-20 1994-03-11 Hitachi Ltd Semiconductor integrated circuit device
CN201867606U (en) * 2010-11-04 2011-06-15 北京握奇数据***有限公司 Switch circuit
CN206413223U (en) * 2016-12-29 2017-08-15 深圳市崧盛电子股份有限公司 A kind of single I/O interface LED adjusting control circuits
CN109901689A (en) * 2019-01-29 2019-06-18 珠海市杰理科技股份有限公司 Hardware switch circuit
CN212463187U (en) * 2020-06-18 2021-02-02 湖南中科电气股份有限公司 Switching value signal control circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669783A (en) * 1992-08-20 1994-03-11 Hitachi Ltd Semiconductor integrated circuit device
CN201867606U (en) * 2010-11-04 2011-06-15 北京握奇数据***有限公司 Switch circuit
CN206413223U (en) * 2016-12-29 2017-08-15 深圳市崧盛电子股份有限公司 A kind of single I/O interface LED adjusting control circuits
CN109901689A (en) * 2019-01-29 2019-06-18 珠海市杰理科技股份有限公司 Hardware switch circuit
CN212463187U (en) * 2020-06-18 2021-02-02 湖南中科电气股份有限公司 Switching value signal control circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种具有在线自检功能的开出回路设计;***;王志鹏;;电子设计工程;20171205(23);第191-194页 *

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