CN115567045A

CN115567045A - Continuous time comparator and laser radar system

Info

Publication number: CN115567045A
Application number: CN202110747392.8A
Authority: CN
Inventors: 高飞; 向少卿
Original assignee: Hesai Technology Co Ltd
Current assignee: Hesai Technology Co Ltd
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2023-01-03

Abstract

A continuous time comparator and a laser radar system are provided. The continuous-time comparator includes: n cascaded fully differential amplifiers, wherein N is more than or equal to 2 and is a positive integer; wherein: in the N cascaded fully-differential amplifiers, a first stage fully-differential amplifier includes: the first amplifying circuit is suitable for working in a first voltage domain and outputting a primary comparison result to the second amplifying circuit according to an input signal and a preset threshold value; the second amplifying circuit is suitable for working in a second voltage domain and amplifying the primary comparison result so as to output a first-stage differential signal to the second-stage fully differential amplifier; and the first voltage value corresponding to the first voltage domain is greater than the second voltage value corresponding to the second voltage domain. By adopting the scheme, the reliability of the comparator can be improved.

Description

Continuous time comparator and laser radar system

Technical Field

The invention relates to the technical field of comparators, in particular to a continuous time comparator and a laser radar system.

Background

In a laser radar system, an optical signal received by a receiving end is converted into an electric signal through a photoelectric conversion device and sent to a comparator, and the comparator detects whether an input signal exceeds a threshold value or not so as to distinguish a signal to be detected and noise. If the input signal exceeds the threshold, the comparator outputs a digital pulse. The digital pulse can reflect the flight time and pulse width information of the input signal for the subsequent quantization, and further reduce the distance information of the measured object. The comparator is used as a core module in a laser radar imaging scheme, and the performance of the comparator directly influences the imaging performance of a laser radar system.

The defects of the existing continuous-time comparator are as follows: the input threshold variation range is relatively small.

In order to increase the variation range of the input threshold, a common solution is to use a full differential amplifier in an NP complementary form to form a continuous time comparator, but the continuous time comparator is not suitable for an application scenario in which the threshold varies from rail to rail, and the first-stage full differential amplifier is in an NP complementary form, that is, a pair of PMOS transistors and a pair of NMOS transistors are simultaneously connected to two input terminals. Therefore, the situation that only one-side MOS tube is opened easily occurs in the continuous time comparator, the working state of the comparator is wrong, and the reliability of the comparator is poor.

Disclosure of Invention

The invention aims to solve the problems that: a continuous-time comparator is provided that is suitable for application scenarios with threshold rail-to-rail variations.

To solve the above problem, an embodiment of the present invention provides a continuous-time comparator, including: n cascaded fully differential amplifiers, wherein N is more than or equal to 2 and is a positive integer; wherein: in the N cascaded fully-differential amplifiers, a first stage fully-differential amplifier includes:

the first amplifying circuit is suitable for working in a first voltage domain and outputting a primary comparison result to the second amplifying circuit according to an input signal and a preset threshold;

the second amplifying circuit is suitable for working in a second voltage domain and amplifying the primary comparison result so as to output a first-stage differential signal to the second-stage fully differential amplifier;

and the first voltage value corresponding to the first voltage domain is greater than the second voltage value corresponding to the second voltage domain.

The embodiment of the invention also provides a laser radar system which comprises the continuous time comparator.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

by applying the scheme of the invention, the first-stage fully differential amplifier of the continuous time comparator comprises the first amplifying circuit and the second amplifying circuit, after the first amplifying circuit obtains the initial comparison result according to the input signal and the preset threshold value, the second amplifying circuit amplifies the initial comparison result, thereby outputting the first-stage differential signal. Because the first amplification circuit works in the first voltage domain, the second amplification circuit works in the second voltage domain, and the first voltage value corresponding to the first voltage domain is greater than the second voltage value corresponding to the second voltage domain, the first comparison result in the first voltage domain is converted into the second voltage domain to be amplified and then output, so that the voltage of the first-stage differential signal cannot exceed the second voltage value corresponding to the second voltage domain, and even if the threshold value input by the first amplification circuit changes from rail to rail, the first-stage fully differential amplifier can still be ensured to output correct first-stage differential signal, thereby improving the reliability of the comparator.

Drawings

FIG. 1 is a schematic diagram of a dynamic comparator in the prior art;

FIG. 2 is a timing diagram of signals of the prior art dynamic comparator shown in FIG. 1;

FIG. 3 is a schematic diagram of a prior art continuous time comparator;

FIG. 4 is a timing diagram of the signals of the prior art continuous-time comparator shown in FIG. 3;

FIG. 5 is a schematic diagram of a comparator detection waveform in a lidar system;

FIG. 6 is a schematic diagram of a first stage fully differential amplifier according to the prior art;

fig. 7 is a schematic waveform diagram of the input signal Vin and the detection threshold Vth in fig. 6;

fig. 8 is a schematic diagram of a first stage fully differential amplifier according to an embodiment of the present invention;

FIG. 9 is a timing diagram of the signals of the first stage fully differential amplifier of FIG. 8;

FIG. 10 is a schematic diagram of a power dissipation load of an amplifier according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a continuous time comparator according to an embodiment of the present invention;

FIG. 12 is a diagram illustrating a structure of a level shift circuit according to an embodiment of the present invention;

FIG. 13 is a timing diagram of signals of the level shift circuit of FIG. 12;

FIG. 14 is a schematic diagram of a monostable circuit according to an embodiment of the invention;

FIG. 15 is a timing diagram of the signals of the continuous-time comparator of FIG. 11.

Detailed Description

The comparator is used as a core module of the laser radar imaging system, and the performance of the comparator directly influences the imaging performance of the laser radar system.

Fig. 1 is a schematic circuit diagram of a conventional dynamic comparator. The dynamic comparator includes: NMOS transistors Mtail, M1, M2, M3 and M4, and PMOS transistors M5, M6, M7 and M8.INN and INP are input signals, and CLK is a clock signal. The capacitors CL1 and CL2 are equivalent ground capacitors for simulating a load capacitor which may exist subsequently.

The dynamic comparator has two states: a voltage comparison state and a reset (reset) state. The state of the dynamic comparator is controlled by a clock signal CLK, the timing of which is shown in fig. 2.

Referring to fig. 2, when the clock signal CLK is at a high level, the dynamic comparator is in a reset state, and the output signals Outp and Outn are both at a low level.

When the clock signal CLK is at a low level, the dynamic comparator is in a voltage comparison state for comparing the input voltages of the input signals INN and INP. Specifically, when the input voltage of the input signal INP is greater than the input voltage of the input signal INN, the output signal Outp is at a high level, and the output signal Outn is at a low level. When the input voltage of the input signal INN is greater than the input voltage of the input signal INP, the output signal Outp is at a low level, and the output signal Outn is at a high level.

After each voltage comparison, the dynamic comparator needs to be reset. During reset, the dynamic comparator cannot respond to the input signal. In the lidar system, the time of occurrence of the received signal is uncertain, and the comparator needs to respond to the input signal in real time in the whole measurement period, so that the dynamic comparator cannot meet the requirements.

In order to meet the requirement of continuous time measurement, a continuous time comparator is adopted in the laser radar system to compare input signals.

Fig. 3 is a schematic diagram of a continuous-time comparator. Referring to fig. 3, the continuous-time comparator includes: n stages of cascaded fully differential amplifiers OPA1 to OPAN, and inverters INV1 and INV2. The capacitors CL3 and CL4 are grounded capacitors, and are used to simulate the load capacitance that may exist.

FIG. 4 is a timing diagram of signals in the continuous time comparator of FIG. 3. Referring to fig. 3 and 4, the n-stage fully differential amplifiers OPA1 to OPAN detect a voltage difference between the input signal Vin and the detection threshold Vth and amplify into the rail-to-rail differential signals oun and outp output. The rail-to-rail differential signal outn is shaped by an inverter INV1 and then outputs a digital pulse out +, and the rail-to-rail differential signal outp is shaped by an inverter INV2 and then outputs a digital pulse out-.

The rail-to-rail, i.e. full swing, may be an output or an input. For example, the rail-to-rail differential signals oun and outp, i.e., the variation range of the voltage values of the differential signals oun and outp, may be full swing.

The accuracy of the continuous time comparator is directly related to the bandwidth and gain of the fully differential amplifier, and the higher the gain bandwidth, the higher the accuracy, and the higher the corresponding power consumption.

In the lidar system, a plurality of comparators are usually used, the detection threshold (for example, vth1, vth2 and Vth3 in fig. 5) of each comparator is set differently, which is equivalent to that a plurality of points are adopted on an input signal pulse, so that pulse information can be better restored, therefore, the variation range of the detection threshold at the input end of each comparator is close to [0, vdd ], the first-stage fully differential amplifier needs to work normally in the variation range of the threshold, and the detection waveform is shown in fig. 5 Vin.

To implement the rail-to-rail input of the detection threshold, the first stage fully differential amplifier is usually set as NP complementary input, and the specific circuit structure of the first stage fully differential amplifier can be referred to fig. 6.

Referring to fig. 6, the first stage fully differential amplifier is NP complementary. Specifically, the first stage fully differential amplifier includes: a pair of NMOS transistors N1 and N2, and a pair of PMOS transistors P1 and P2. The NMOS tubes N1 and N2 and the PMOS tubes P1 and P2 are respectively connected with a ground wire and a power supply voltage output end, and the power supply voltage output end outputs power supply voltage VDD.

Wherein, V _BIAS1 And V _BIAS2 The Class AB control circuit is provided by an external circuit and is used for controlling an NMOS tube and a PMOS tube of a later stage to work in a saturation region. The threshold value maximum variation range VDD/2 of the NMOS tubes N1 and N2 and the PMOS tubes P1 and P2 is limited by the working voltage of the MOS tubes.

Referring to fig. 7, the common mode levels of the input signal Vin and the detection threshold Vth are set to be V _CM1 And V _CM2 . When V is shown in FIG. 6 _CM1 And V _CM2 Meanwhile, when the voltage of the input signal Vin is changed within the range of 0-VDD, the NMOS pair transistor is conducted, and when the voltage of the input signal Vin is smaller than VDD/2, the PMOS pair transistor is conducted, so that the first-stage fully differential amplifier can normally amplify the input signal Vin.

However, the problem with the first stage fully differential amplifier described above is that: v _CM1 And V _CM2 Should not be too great, if V is present _CM1 >VDD/2，V _CM2 <The VDD/2 condition can cause the input pair tube to be opened only on one side, and the working state is wrong. This NP complementary form of the input stage is not suitable for the case where the comparator has only a single-sided threshold rail-to-rail variation. In other words, the first stage fully differential amplifier cannot operate normally when the common mode level of the input signal Vin and the detection threshold Vth is different greatly.

In view of the foregoing problems, an embodiment of the present invention provides a continuous time comparator, where a first-stage fully differential amplifier includes a first amplifier circuit and a second amplifier circuit, and since the first amplifier circuit operates in a first voltage domain, the second amplifier circuit operates in a second voltage domain, and a first voltage value corresponding to the first voltage domain is greater than a second voltage value corresponding to the second voltage domain, a first comparison result in the first voltage domain is converted into a second voltage domain and then amplified and then output, so that a voltage of a first-stage differential signal may not exceed a second voltage value corresponding to the second voltage domain, and thus, even when a threshold value input by the first amplifier circuit changes from rail to rail, the first-stage fully differential amplifier may still output a correct first-stage differential signal, and thus reliability of the comparator may be improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 8, an embodiment of the present invention provides a continuous-time comparator, which may include N cascaded fully-differential amplifiers; wherein: in the N cascaded fully-differential amplifiers, the first stage fully-differential amplifier may include:

the first amplifying circuit 81 is adapted to operate in a first voltage domain, and output the primary comparison results out1 and out2 to the second amplifying circuit 82 according to the input signal Vin and the preset threshold Vth;

a second amplifying circuit 82, adapted to operate in a second voltage domain, for amplifying the primary comparison results out1 and out2 to output first-stage differential signals outp and outn to the second-stage fully differential amplifier;

the first voltage value VDD1 corresponding to the first voltage domain is greater than the second voltage value VDD2 corresponding to the second voltage domain.

By adopting the first voltage domain and the second voltage domain and ensuring that VDD1 is larger than VDD2, the input signal Vin and the preset threshold Vth can cover threshold variation within the range of [0, VDD2] in the first voltage domain, and further when the input signal Vin or the preset threshold Vth is converted to be output in the second voltage domain through folding, when the voltage of the input signal Vin or the preset threshold Vth is very low, the voltage of the first-stage differential signals outp and outn does not exceed VDD2 too much, so that the voltage of the subsequent input stage can be ensured not to be over-voltage, and the reliability of the comparator can be improved.

Wherein the output of the first stage differential signal does not exceed the second voltage domain. Preferably, the subsequent stages of the continuous time comparator differential amplifier operate in the second voltage domain and the output of each stage of the continuous time comparator does not exceed the second voltage domain.

In a specific implementation, the first voltage value VDD1 enables the first amplifying circuit 81 to operate normally, and the second voltage value VDD2 enables the second amplifying circuit 82 to operate normally. The difference between the first voltage value VDD1 and the second voltage value VDD2 can be set according to factors such as the voltage withstanding capability of the MOS transistor and the normal on-state voltage range.

For example, the first voltage value VDD1 may be set to 2.5V, the second voltage value VDD2 may be set to 1.8V, and a difference between the first voltage value VDD1 and the second voltage value VDD2 is close to a normal on voltage of a MOS transistor, for example, the difference may be 0.7V.

In a specific implementation, the first amplifying circuit 81 and the second amplifying circuit 82 may have various circuit structures, and are not particularly limited as long as the input signal and the preset threshold can be amplified.

In an embodiment of the present invention, referring to fig. 8, the first amplifying circuit 81 may include: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, and a second NMOS transistor MN2. Wherein:

and the source electrode of the first PMOS pipe MP1 is connected with the first voltage output end. The drain electrode of the first PMOS transistor MP1 is connected to the source electrode of the second PMOS transistor MP2 and the source electrode of the third PMOS transistor MP 3. The drain of the second PMOS transistor MP2, which is used as the first output terminal of the first amplifying circuit 81, outputs a first output signal out1, and is connected to the drain of the first NMOS transistor MN 1. The drain of the third PMOS transistor MP3, which is used as the second output end out2 of the first amplifying circuit 81, outputs the second output signal out2, and is connected to the drain of the second NMOS transistor MN2. And the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3 are used as the input ends of the difference value detection circuit.

Specifically, an input signal Vin is input to the gate of the second PMOS transistor MP2, and a predetermined threshold Vth is input to the gate of the third PMOS transistor MP 3. The gate of the first PMOS transistor MP1 inputs the first control voltage Vbp _1, and the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 input the second control voltage Vbn _1.

FIG. 9 is a timing diagram of the signals in FIG. 8. Referring to fig. 9, when each MOS transistor in the first amplifying circuit 81 is turned on, the first amplifying circuit 81 compares an input signal Vin with a predetermined threshold Vth. When Vin > Vth, the first output signal out1 is at a negative level, and the second output signal out2 is at a positive level. When Vin < Vth, the first output signal out1 is at a positive level, and the second output signal out2 is at a negative level. The first output signal out1 and the second output signal out2 are differential signals.

The first output signal out1 and the second output signal out2 are input signals to the second amplifier circuit 82, and are amplified by the second amplifier circuit 82. The circuit configuration of the second amplifying circuit 82 may also be various, and is not particularly limited.

In an embodiment of the present invention, the second amplifying circuit 82 may include: a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. Wherein:

and the source electrode of the fourth PMOS tube MP4 and the source electrode of the fifth PMOS tube MP5 are connected with the second voltage output end. The grid electrode of the fourth PMOS transistor MP4 is connected to the drain electrode of the fourth PMOS transistor MP 4. The grid electrode of the fifth PMOS transistor MP5 is connected to the drain electrode of the fifth PMOS transistor MP 5. The drain of the fourth PMOS transistor MP4 is used as the first output terminal of the second amplifying circuit 82, outputs a third output signal outp, and is connected to the drain of the third NMOS transistor MN 3. The drain of the fifth PMOS transistor MP5, which is used as the second output terminal of the second amplifying circuit 82, outputs a fourth output signal outn, and is connected to the drain of the fourth NMOS transistor MN4. The source of the third NMOS transistor MN3 is connected to the second output terminal of the first amplifier circuit 81, and the source of the fourth NMOS transistor MN4 is connected to the first output terminal of the first amplifier circuit 81.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 input the third control voltage Vbn _2. After the first output signal out1 and the second output signal out2 are input to the sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the voltages of the third output signal outp and the fourth output signal outn are increased, as shown in fig. 9, so as to achieve the purpose of amplifying the first output signal out1 and the second output signal out 2.

Referring to fig. 9, a voltage difference between the first output signal out1 and the second output signal out2 is V1, and a voltage difference between the first output signal out1 and the second output signal out2 is V2, V1 < V2 < VDD2.

By adopting the first-stage fully differential amplifier, a power supply voltage is added, the voltage range of the final output signal of the first-stage fully differential amplifier is controlled by switching the folding circuit between two voltage domains, rail-to-rail threshold input is realized at a low cost, and the circuit complexity is reduced.

In a specific implementation, in the continuous time comparator, only two fully differential amplifiers may be provided, or three or more fully differential amplifiers may be provided, and the specific number is not limited. Because the input signal of the first-stage fully differential amplifier in the embodiment of the present invention can ensure that the input voltage of the later-stage fully differential amplifier is not over-voltage, the structure of the existing fully differential amplifier (for example, fig. 1) can be adopted for the later-stage fully differential amplifier. Of course, part or all of the post-stage fully differential amplifier may also adopt the structure of the first-stage fully differential amplifier in the embodiment of the present invention.

Since the direct influence factors of the bandwidth of the fully differential amplifier are the driving current and the load, in an embodiment of the present invention, in order to save power consumption, the loads of the N cascaded fully differential amplifiers may be set to gradually decrease from the first stage to the last stage. By setting the load of the multistage amplifier to decrease step by step from the first stage to the last stage, the current of each stage of amplifier can be reduced step by step. Each stage of amplifier is a front stage load, the current of the first stage amplifier is the highest, the circuit size is the largest, the circuit size is reduced step by the rear stage, and the load is reduced, so the current can be reduced step by step while the bandwidth is kept unchanged, and the total power consumption is reduced.

The amplifier power consumption load schematic diagram is shown in fig. 10, where the load of the first-stage fully differential amplifier OPA1 is C, the load of the second-stage fully differential amplifier OPA2 is C/2, the load of the third-stage fully differential amplifier OPA3 is C/4, and the load of the fourth-stage fully differential amplifier OPA4 is C/8. Accordingly, the current of each stage of amplifier is as follows: i, I/2, I/4, I/8.

In a specific implementation, referring to fig. 3, the outputs of the n cascaded fully differential amplifiers may be shaped by an inverter INV1 and an inverter INV2 and then output.

In the practical application of a laser radar system, a received signal is weak when a long distance is detected, the threshold-crossing amplitude is small, a comparator is required to have high detection precision and can identify the weak signal, and the overall power consumption is difficult to reduce due to the high-precision requirement.

In an embodiment of the present invention, referring to fig. 11, in order to improve the accuracy of the continuous-time comparator, the continuous-time comparator may further include a level shift circuit 110. The level shift circuit 110 is connected to the last stage of the N cascaded fully differential amplifiers OPAN, and is adapted to convert the differential signals outp 'and outn' output by the last stage of the fully differential amplifiers OPAN into the single-ended signal LS _0.

In specific implementation, the level shift circuit 110 may have various circuit structures, and is not particularly limited as long as the differential signals outp 'and outn' output by the final stage fully differential amplifier OPAN can be converted into the single-ended signal LS _0.

In an embodiment of the present invention, in order to trade off accuracy and power consumption, referring to fig. 12, the level shift circuit 110 may include: a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a first switch S1, and a second switch S2. Wherein:

the source electrode of the sixth PMOS pipe MP6 is connected with the second voltage output end; the grid electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the sixth PMOS tube MP 6; the drain of the sixth PMOS transistor MP6 is grounded via the first switch S1.

The source electrode of the seventh PMOS tube MP7 is connected with the second voltage output end; the grid electrode of the seventh PMOS tube MP7 is connected with the drain electrode of the seventh PMOS tube MP 7; the drain electrode of the seventh PMOS tube MP7 is grounded through the second switch S2;

the first switch S1 is adapted to be opened or closed under the control of a signal output from a first output terminal of the last stage fully differential amplifier OPAN; the second switch S2 is adapted to be opened or closed under control of a signal output from the second output terminal of the last stage fully differential amplifier OPAN.

FIG. 13 is a timing diagram of signals in the level shift circuit of FIG. 12. With reference to fig. 13 and 12, when the differential signal outp 'output by the last stage of fully differential amplifier OPAN is at a high level and outn' is at a low level, the first switch S1 is closed, the second switch S2 is opened, the voltage at the point X is pulled low, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are turned on, and the single-ended signal LS _0 outputs a high level. When the differential signal outp 'output by the last stage of fully differential amplifier OPAN is at a low level and outn' is at a high level, the first switch S1 is turned off, the second switch S2 is turned on, the single-ended signal LS _0 is pulled low to output a low level, at this time, the level shift circuit 110 does not have static power consumption, and at this time, the level shift circuit 110 realizes that the static power consumption is 0 through the combination of the output of the amplifier and the input of the level shift circuit 110.

Compared with the continuous-time comparator in fig. 3, the continuous-time comparator in fig. 11 outputs a single-ended signal, so that the influence of the double-ended signal on the comparison result due to misalignment can be avoided, and the accuracy of the continuous-time comparator is improved. Moreover, by using the level shift circuit 110 shown in fig. 12, the accuracy of the continuous time comparator can be improved without increasing the static power consumption, and the problem of compromising the power consumption and the accuracy is solved.

In a specific implementation, referring to fig. 11, the signal output by the level shift circuit 110 may output the final result signal of the continuous-time comparator via the shaping circuit 111. The shaping circuit may be formed by a plurality of (for example, two) inverters connected in series, so as to shape the signal output by the level shift circuit 110, and obtain a corresponding digital signal. Compared with the signal before shaping, the rising edge and the falling edge of the digital signal obtained after shaping are more obvious, and the final comparison result can be represented more accurately.

In other embodiments, the signal output from the level shift circuit 110 may not be shaped, but may be directly used as a plurality of (e.g., two) inverters connected in series.

In a specific implementation, in the case of a narrow pulse input, the pulse width of the output signal of the comparator is too narrow, which results in that the subsequent stage cannot process the output signal, and the distance information conveyed by the pulse is leaked.

To this end, in an embodiment of the present invention, referring to fig. 11, the continuous-time comparator may further include a monostable 112 connected to the level shift circuit 110 and adapted to increase a minimum output pulse width of the digital signal output by the level shift circuit 110.

It will be appreciated that in a specific implementation, when the continuous-time comparator further includes the shaping circuit 111, the monostable 112 is connected to the level shift circuit 110 through the shaping circuit 111.

In a specific implementation, the minimum output pulse width of the digital signal output by the monostable circuit can be more than 1ns, so that the subsequent processing can be facilitated without losing the detected relevant information.

In specific implementations, the monostable 112 can have various circuit structures, and is not particularly limited as long as the minimum output pulse width of the digital signal output by the level shift circuit 110 can be increased.

In an embodiment of the present invention, referring to fig. 14, the monostable 112 may include: a first inverter 141, a first nand gate 142, a capacitor C1, a resistor R1, a second inverter 143, and a second nand gate 144. Wherein:

the input end of the first inverter 141 is connected to the output end of the shaping circuit; the output end of the first inverter 141 is connected to the first nand gate 142 and the second nand gate 144; the first NAND gate is connected with a second inverter 143 through a capacitor C1 of 141; the second inverter 143 is connected to the second nand gate 144; the resistor R1 is connected with the capacitor C1.

In a specific implementation, the input signal out' (i.e. the output signal of the shaping circuit or the level shifting circuit) is inverted by the first inverter 141 and then input to the input terminal of the first nand gate 142, and then input to the input terminal of the second nand gate 144. The first nand gate 142 outputs the output signal of the second inverter 143 and the output signal of the first inverter 141 after performing nand operation, and the output signal of the first nand gate 142 is filtered by RC filtering formed by a capacitor C1 and a resistor R1 and then output to the second inverter 143. The second nand gate 144 performs a nand operation on the output signal of the second inverter 143 and the output signal of the first inverter 141, and outputs the nand operation.

As can be seen from fig. 14, the pulse width of the output signal of the first nand gate 142 increases after RC filtering, so that the minimum output pulse width of the digital signal output by the second nand gate 144 increases.

In fig. 14, the third inverter 145 and the fourth inverter 146 connected to the output of the second nand gate 144 are used to drive the load of the subsequent stage, change the pulse direction, and facilitate the subsequent processing.

By adding the monostable circuit, the minimum output pulse width of the continuous time comparator is controlled, so that the continuous time comparator forces the minimum output pulse width to be more than 1ns, thereby ensuring that useful information cannot be lost and lightening the design burden of a post-stage circuit.

Referring to fig. 11, when N =4, that is, the continuous-time comparator includes 4 cascaded fully-differential amplifiers, the output of the 4 th-stage fully-differential amplifier OPA4 sequentially passes through the level shift circuit 110, the shaping circuit 111, and the monostable circuit 112, and then the final result signal out of the continuous-time comparator is obtained, and a timing diagram of each signal can be referred to fig. 15.

From the above, it can be seen that the continuous time comparator in the embodiment of the present invention, due to the special design of the amplifier part, can reduce the total power consumption of the comparator, reduce the chip area, and simultaneously can achieve very high precision, thereby solving the problem of compromise between power consumption and precision. In addition, few circuits are added on the basis of a conventional continuous time comparator, two additional functions of rail-to-rail threshold input and minimum output pulse width control are obtained with low cost, and the overall complexity of the radar system is reduced.

There is also provided in an embodiment of the present invention a lidar system that may include the continuous-time comparator of the above-described embodiments.

In a laser radar system, an optical signal received by a receiving end is converted into an electric signal through a photoelectric conversion device and is sent to the continuous time comparator, and the continuous time comparator detects whether an input signal exceeds a threshold value or not, so that the signal to be detected and noise can be distinguished. When the input signal exceeds the threshold value, the continuous time comparator can output digital pulses if the input signal exceeds the threshold value so as to reflect the flight time and pulse width information of the input signal, and the digital pulses are used for the subsequent quantization and finally restore the distance information of the measured object.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A continuous-time comparator, comprising: n cascaded fully differential amplifiers, wherein N is more than or equal to 2 and is a positive integer; wherein: in the N cascaded fully-differential amplifiers, a first stage fully-differential amplifier includes:

2. The continuous-time comparator as claimed in claim 1, wherein the first voltage value is greater than the second voltage value to enable the first amplifying circuit to operate normally.

3. The continuous-time comparator as claimed in claim 1, wherein said first amplifying circuit comprises: the PMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor; wherein:

the source electrode of the first PMOS tube is connected with the first voltage output end; the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the source electrode of the third PMOS tube; the drain electrode of the second PMOS tube is used as a first output end of the first amplifying circuit and is connected with the drain electrode of the first NMOS tube; the drain electrode of the third PMOS tube is used as a second output end of the first amplifying circuit and is connected with the drain electrode of the second NMOS tube; and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are used as the input end of the first amplifying circuit.

4. The continuous-time comparator of claim 1, wherein the second amplification circuit comprises: a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube and a fourth NMOS tube; wherein:

the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected with the second voltage output end; the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the drain electrode of the fifth PMOS tube; the drain electrode of the fourth PMOS tube is used as the first output end of the second amplifying circuit and is connected with the drain electrode of the third NMOS tube; the drain electrode of the fifth PMOS tube is used as a second output end of the second amplifying circuit and is connected with the drain electrode of the fourth NMOS tube; the source electrode of the third NMOS tube is connected with the second output end of the first amplifying circuit; and the source electrode of the fourth NMOS tube is connected with the first output end of the first amplifying circuit.

5. The continuous-time comparator as claimed in any one of claims 1 to 4, wherein the load of the N cascaded fully differential amplifiers decreases from the first stage to the last stage.

6. The continuous-time comparator as claimed in claim 4, further comprising:

and the level shift circuit is connected with the last stage of fully differential amplifier in the N cascaded fully differential amplifiers and is suitable for converting the differential signal output by the last stage of fully differential amplifier into a single-ended signal.

7. The continuous-time comparator as claimed in claim 6, wherein said level shifting circuit comprises: a sixth PMOS tube, a seventh PMOS tube, a first switch and a second switch; wherein:

the source electrode of the sixth PMOS tube is connected with the second voltage output end; the grid electrode of the sixth PMOS tube is connected with the drain electrode of the sixth PMOS tube; the drain electrode of the sixth PMOS tube is grounded through the first switch;

the source electrode of the seventh PMOS tube is connected with the second voltage output end; the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube; the drain electrode of the seventh PMOS tube is grounded through the second switch;

the first switch is suitable for being opened or closed under the control of a signal output by a first output end of the final stage fully differential amplifier; the second switch is suitable for being opened or closed under the control of a signal output by the second output end of the final stage fully differential amplifier.

8. The continuous-time comparator as claimed in claim 6, comprising:

and the monostable circuit is connected with the level shifting circuit and is suitable for increasing the minimum output pulse width of the digital signal output by the level shifting circuit.

9. The continuous-time comparator as claimed in claim 8, wherein the digital signal output by the monostable has a minimum output pulse width greater than 1ns.

10. The continuous-time comparator of claim 8, wherein the monostable circuit comprises: the first inverter, the first NAND gate, the capacitor, the resistor, the second inverter and the second NAND gate; wherein:

the input end of the first inverter is connected with the output end of the level shift circuit; the output end of the first inverter is connected with the first NAND gate and the second NAND gate; the first NAND gate is connected with the second inverter through a capacitor; the second inverter is connected with the second NAND gate; the resistor is connected with the capacitor.

11. The continuous-time comparator as claimed in claim 1, wherein N =4.

12. A lidar system comprising the continuous-time comparator of any of claims 1 to 11.