CN111627990A - Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer. The high-dielectric-constant gate dielectric is Al2O3Gate dielectric or HfO2And a gate dielectric. The invention not only realizes high-quality compact Al on the graphene2O3Growth of dielectric layers, and not in two-dimensional materialsThere are significant drawbacks.
Description
Technical Field
The invention relates to a top gate type field effect transistor, in particular to a method for preparing the top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer.
Background
Since the discovery of graphene in 2004, two-dimensional materials have attracted considerable scientific attention. The materials have wide application prospects in the aspects of logic devices, photoelectric detectors, flexible touch screens, radio frequency devices and the like. However, most of the novel physical phenomena and unique two-dimensional material characteristics are discovered based on the back gate structure so far. This is because these van der waals force bonded layered two-dimensional materials lack intrinsic dangling bonds at the surface, high dielectric constant gate dielectrics, such as alumina (Al)2O3) Hafnium oxide (HfO)2) It is difficult to integrate on the surface of these two-dimensional materials, and thus it is difficult to fabricate a top-gate two-dimensional material Field Effect Transistor (FET). However, in order to apply the two-dimensional material to the actual thin film transistor circuit, a two-dimensional material device based on the top gate structure is very necessary. First, a back gate Field Effect Transistor (FET) is not compatible with integrated circuit technology (CMOS), because it cannot individually adjust the electrical characteristics of each device as a top gate Field effect transistor. Second, to lower the operating voltage and further reduce the device size, the gate dielectric needs to be thinner and have a higher dielectric constant. Thirdly, for a low-power device, coulomb scattering in a graphene channel can be effectively inhibited by utilizing the gate coupling effect of the top gate, so that the carrier mobility and the maximum saturation current are improved.
The Atomic Layer Deposition (ALD), the most mature technology for preparing gate dielectrics at present, is a standard method for preparing gate dielectrics in CMOS process due to its precise thickness control, excellent sample surface flatness and lower growth temperature. However, gate dielectric growth by such standard processes is difficult for most conventional two-dimensional materials, such as graphene and transition metal chalcogenides. In order to solve the problem that the surface of the two-dimensional material is lack of intrinsic dangling bonds, the gate dielectric is uniformly grown on the surface of the two-dimensional material, and various pretreatment methods are adopted to form dangling bonds on the surface of the two-dimensional material. For example, the method includes oxidizing the surface of a sample with ultraviolet ozone, bombarding the surface of the sample with plasma, spin-coating an organic polymer on the surface of the sample, or thermally evaporating an ultra-thin metal film as a seed layer. These approaches not only add technical complexity, but also compromise the lattice integrity of the two-dimensional material and reduce the overall gate capacitance of the device.
Disclosure of Invention
The invention aims to solve the technical problem that lattice defects can be caused by adopting a chemical method to carry out surface pretreatment on the existing two-dimensional material (such as graphene, transition metal sulfide and the like) before integrating a high-dielectric-constant gate medium, and provides a method for preparing a top-gate field effect transistor by utilizing a thermally evaporated aluminum seed layer, wherein the surface pretreatment can not cause obvious structural damage or defects of the two-dimensional material.
In order to solve the technical problems, the invention provides a method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer.
The surface pretreatment method of the invention before the ALD growth of the high dielectric constant gate dielectric comprises the following steps: the method comprises the steps of firstly thermally evaporating an ultrathin metal medium to the surface of a two-dimensional material, then placing the two-dimensional material into a drying oven to be naturally oxidized into a seed layer, and then preparing the top-gate two-dimensional material FET through a standard micro-nano manufacturing process. The surface pretreatment method has three advantages: (1) by using the thermal evaporation ultrathin metal medium as a seed layer, nucleation positions can be provided on the surface of the two-dimensional material, so that precursors in the ALD process can be effectively chemisorbed. (2) The thermal evaporation of ultrathin metal on the surface of two-dimensional material belongs to the physical process. Thus, in contrast to other chemical methods (e.g., ultraviolet ozone or plasma pretreatment), in two-dimensional materialsNo significant structural damage or defects occur. (3) After thermal evaporation of the ultra-thin metal dielectric, the ultra-thin metal layer will rapidly oxidize to form amorphous Al2O3Or hafnium oxide (HfO)2) And therefore does not significantly reduce the top gate capacitance as does the polymer coating pretreatment.
The high-dielectric-constant gate dielectric is aluminum oxide (Al)2O3) Gate dielectric or hafnium oxide (HfO)2) And a gate dielectric.
The method for preparing the top gate type field effect transistor by utilizing the thermal evaporation aluminum seed layer comprises the following steps:
1) stripping the two-dimensional material crystal onto a silicon wafer by using a micro-mechanical stripping method so as to attach a single-layer two-dimensional material nanosheet onto the silicon wafer;
2) forming a source electrode pattern and a drain electrode pattern on a silicon wafer attached with a single-layer two-dimensional material nanosheet by using an electron beam exposure method, and preparing the source electrode and the drain electrode by using a thermal evaporation coating and stripping process;
3) evaporating ultrathin metal Al to the surface of the two-dimensional material nanosheet between the source electrode and the drain electrode by using a thermal evaporation coating machine, and after evaporation is finished, putting the silicon wafer into an oxidation box for oxidation so that an ultrathin metal Al medium obtained by thermal evaporation is completely oxidized;
4) growing Al on the surface of the ultrathin metal Al medium obtained in the step 3) by utilizing an atomic layer deposition method2O3A gate dielectric;
5) al by electron beam exposure2O3Forming a gate electrode pattern on the gate dielectric, and preparing a gate electrode by using electron beam coating;
6) and packaging to obtain the finished product.
The step 3) comprises the following steps:
(1) placing the silicon wafer with the prepared source electrode and drain electrode into an evaporation chamber of a thermal evaporation coating machine, and vacuumizing to ensure that the pressure in the evaporation chamber is only 110-5Pa；
(2) Starting a thermal evaporation coating machine to coat an ultrathin metal medium Al on the surface of the two-dimensional material of the silicon wafer, wherein the coating parameters are as follows: al deposition thickness 2 nm, evaporation rate: 0.3A/s;
(3) and after the film coating is finished, taking out the silicon wafer, and putting the silicon wafer into a drying box with the temperature of 25 ℃ and the relative humidity of 20% for oxidizing for 30 minutes to completely oxidize the ultrathin metal aluminum obtained by thermal evaporation on the silicon wafer.
The atomic layer deposition method comprises the following steps:
(1) placing the silicon wafer attached with the two-dimensional material nanosheet into a reaction chamber, and introducing nitrogen with the purity of 99.9997% and the gas flow flux of 40 sccm for cleaning for 20 minutes;
(2) setting the temperature rise time to be 25-35 min, and heating the reaction cavity to 148-152 ℃;
(3) introducing trimethylaluminum and distilled water into the reaction cavity, setting the introduction time of the trimethylaluminum to be 8-12 s, the introduction time of the distilled water to be 8-12 s, switching the valve for 0.015s, and performing 273 cycles by taking the valve as a cycle until Al with the thickness of 30nm grows on the silicon wafer attached with the two-dimensional material nanosheets2O3A gate dielectric;
(4) to be Al2O3And taking out the gate dielectric after the growth of the gate dielectric is finished.
In order to reduce parasitic capacitance and enhance gating characteristics, the gate electrode completely covers the conductive channel of the two-dimensional material nanosheet.
The applicant takes graphene as an example to confirm the effectiveness of the method:
as shown in FIG. 3, the invention not only realizes high-quality compact Al on the graphene by means of thermally evaporating an aluminum oxide seed layer on the graphene before ALD growth2O3The surface roughness (Ra) of the graphene which is directly subjected to ALD growth without pretreatment is reduced from 2.8 nm to 0.32 nm.
As shown in FIG. 4, after the Al seed layer is used for the process of the present invention, the leakage current can be increased from 10-3A is reduced to 10-11A, reduced by 8 orders of magnitude, and also demonstrated that Al was obtained using the pretreatment method of the present invention2O3Excellent insulating properties of the gate dielectric.
As shown in fig. 5, raman characterization and atomic force characterization of graphene in the thermal evaporation Al seed layer treatment process find that no raman characteristic defect peak (D peak) occurs in the entire process flow, and an atomic force scanning image of the device is very clean, which indicates that the method has no obvious damage to graphene.
As shown in fig. 6, the substantial characterization and transport characteristics performance of graphene top-gate devices prepared by the present invention indicates that the top-gate graphene devices have high mobility (— 6200 cm)2V-1s-1) And high transconductance (— 117 μ S), and preparing the resultant Al2O3The relative dielectric constant of the gate dielectric is 6.5, and the tunneling current (leakage current) is less than 1.6 pA/mum2。
As shown in FIGS. 7 and 8, the method of the present invention is also applicable to two-dimensional material molybdenum telluride (MoTe)2) And Black Phosphorus (BP), which was also found to be present after pretreatment with a thermally evaporated aluminum seed layer by atomic force characterization, in molybdenum telluride (MoTe)2) And Black Phosphorus (BP) to form dense Al2O3A film. These results indicate that high quality Al can be achieved by functionalizing the two-dimensional material surface with a thermally evaporated aluminum seed layer2O3And growing the gate dielectric to obtain the high-performance top gate field effect transistor.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic flow chart of the present invention for fabricating a top gate type FET by thermally evaporating an Al seed layer.
Fig. 2 is a schematic cross-sectional view of a top gate graphene field effect transistor prepared by the present invention. Wherein S represents a source, D represents a drain, G represents a top gate electrode,V TGrepresenting the top gate voltage applied across the device,V BGrepresenting the back gate voltage. Si and SiO2Respectively representing silicon and silicon dioxide, i.e. silicon wafers, in which the oxide layer (SiO)2) The thickness was 300 nm. Graphene stands for Graphene and the alkoxide for an amorphous (oxidized) Al seed layer with natural oxidation after thermal evaporation.
FIG. 3 is an atomic force scan and an electron microscope image comparison of a graphene directly subjected to ALD growth and an Al seed layer treatment, and then subjected to ALD growth, wherein (a) and (c) are the atomic force scan and the electron microscope image of the graphene directly subjected to ALD growth; (b) and (d) an atomic force scanning image and an electron microscope image of the graphene which is subjected to ALD growth after the Al seed layer treatment, wherein Ra represents the plane roughness of the surface of the sample.
Fig. 4 is a comparison of Metal-insulator-semiconductor (MIS) leakage current of a Metal-insulator-semiconductor (ALD) structure grown directly and graphene MIS structure grown by ALD after Al seed layer processing, wherein,I Gwhich is representative of the leakage current,V TGrepresenting the top gate voltage.
Fig. 5 shows raman and atomic force characterization of graphene in the thermal evaporation Al seed layer processing flow process, where a is raman characterization, b is atomic force characterization, G and 2D are both raman characteristic peaks of graphene, and D is a structural defect raman characteristic peak of graphene.
FIG. 6 is a graph of the basic characteristics and transport characteristics of a graphene top-gate FET, wherein a is a transfer characteristic graph, b is a hysteresis scan graph, an inset in a is an optical characterization of the graphene top-gate device, S represents a source, D represents a drain, TG represents a top-gate electrode,I DSwhich is representative of the source-drain current,V DSwhich represents the source-drain voltage, is,V Gwhich represents the gate voltage, is used as a reference,V TGwhich represents the voltage of the top gate,g mrepresenting the transconductance.
FIG. 7 shows the growth of molybdenum telluride (MoTe) by ALD after Al seed layer treatment2) An atomic force scan and a Raman characterization map, wherein a is the atomic force scan and b is the Raman characterization map.
FIG. 8 is an atomic force scan and a Raman characterization of Black Phosphorus (BP) after Al seed layer treatment and ALD growth, where a is the atomic force scan and b is the Raman characterization.
Detailed Description
The invention is further described below with reference to specific preferred embodiments, without thereby limiting the scope of protection of the invention.
For convenience of description, the relative positional relationship of the components, such as: the descriptions of the upper, lower, left, right, etc. are described with reference to the layout directions of the drawings in the specification, and do not limit the structure of the present patent.
As shown in fig. 1 and fig. 2, an embodiment of the method for manufacturing a top gate fet by using a thermally evaporated aluminum seed layer according to the present invention includes the following steps:
firstly, preparing graphene by a micro-mechanical stripping method: (1) bulk graphene crystals (model: Smart Elements) were placed on a tape (model: Scotch tape). (2) By repeatedly folding the adhesive tape in half, the bulk graphene is peeled off to a thin layer and attached to the whole adhesive tape. (3) The tape was adhered to a silicon wafer (doping type: P type; thickness of oxide layer: 300 nm). After standing for one minute, peeling off the adhesive tape, and obtaining the single-layer (or thin-layer) graphene nanosheet on the silicon wafer.
And secondly, processing the source electrode and the drain electrode of the field effect transistor by a microelectronic process:
(one) electron beam exposure to obtain the required electrode pattern: (1) the position of the graphene nanoplatelets on the silicon wafer is positioned by using an optical microscope (model: Olympus DX 51) with a coordinate displacement table, and the horizontal and vertical coordinate values are recorded. (2) Spin-coating an electron beam exposure paste (model: PMMA 950K) onto a silicon wafer substrate with parameters of forward rotation of 600r (or 500r, 550r, 600r, 650r,700 r), continuation of 10s (or 8s, 9s, 10s, 11s, 12 s), backward rotation of 4000r (or 3800r, 3900r, 4000r,4100r, 4200r), and continuation of 40s (or 38s, 39s, 40s, 41s, 42 s). Heating on a drying table for 120s (or 110s, 115s, 120s, 125s, 130s) at 170 deg.C (or 165 deg.C, 170 deg.C, 175 deg.C). (3) After the coordinates were determined, the desired source and drain electrode patterns were exposed (parameters: high voltage: 10 kV, aperture size: 30 μm, beam current: 217 pA). (4) After the exposure, the silicon wafer was taken out and left to stand in a developing solution for 30s (or 28s, 29s, 30s, 31s, 32 s) and a fixing solution for 30s (or 28s, 29s, 30s, 31s, 32 s). And finally, taking out the silicon wafer, and flushing the residual liquid on the surface of the sample by using an air gun to obtain the required source and drain electrode patterns.
(II) preparing a metal electrode by thermal evaporation coating: (1) putting the silicon wafer subjected to electron beam exposure into an evaporation cavity of a coating machine, vacuumizing the evaporation cavity by using a mechanical pump and a molecular pump for more than 2 hours to ensure that the pressure in the evaporation cavity is only 110-5Pa, (2) according to the metal to be plated (the purity is 99.995%), adjusting corresponding crucibles, (3) according to the experiment, titanium (Ti) is plated firstly, gold (Au) is plated later, coating parameters (deposition thickness: Ti: 4nm, Au: 50nm, evaporation rate: 0.5 Å/s, Au: 1.5 Å/s) are set, a baffle plate is opened, and after the coating is automatically started by a coating machine, (4) the vacuum of the thermal evaporation coating machine is broken, the silicon wafer is taken out, and the coating operation is completed.
(III) stripping process: (1) placing the plated silicon wafer in hot acetone, covering glass plate with the glass plate, and standing at 65 deg.C (55 deg.C, 60 deg.C, 65 deg.C, 70 deg.C) for 5min (or 4min, 5min, 6min, 7 min). (2) And when bubbles appear on the gold film on the silicon wafer, placing the beaker filled with the hot acetone and the silicon wafer in an ultrasonic cleaning machine for ultrasonic treatment, and taking out after about 1 second. (3) And (3) putting the stripped silicon wafer into an isopropanol solution for cleaning for about 1 minute, taking out the silicon wafer, and removing residual liquid on the surface by using an air gun to obtain a source electrode and a drain electrode of the graphene field effect transistor at two ends of the silicon wafer.
Thirdly, preparing an ultrathin metal aluminum seed layer: (1) and evaporating Al to the surface of the silicon wafer by using a thermal evaporation coating machine. The specific operation is the same as the second point in step two, and the parameters used herein are Al: 2 nm, evaporation rate: 0.3A/s. (2) After the thermal evaporation operation, the silicon wafer was put into an oxidation oven to oxidize for 30 minutes, so that the ultrathin metallic aluminum obtained by thermal evaporation was completely oxidized (drying oven environment: temperature: 25 ℃ C.; relative humidity: 20%).
Preparation of high quality Al by atomic layer deposition2O3A gate dielectric: (1) the silicon wafer was placed in a reaction chamber and purged with nitrogen gas (purity: 99.9997%, gas flow rate: 40 sccm) for 20 minutes. (2) Heating the reaction chamber to 150 deg.C (or 148 deg.C, 149 deg.C, 150 deg.C, 151 deg.C, 152 deg.C), and setting the temperature rise time to 30min (or 25min, 30min, 35 min). (3) Introducing trimethylaluminum and distilled water into the reaction cavity, setting the introducing time of the trimethylaluminum to be 10s (or 8s, 9s, 10s, 11s, 12 s), the introducing time of the distilled water to be 10s (or 8s, 9s, 10s, 11s, 12 s), switching the valve time to be 0.015s, taking the time as a period, and carrying out 273 cycles (273 cycles are equivalent to the grown Al) of the reaction2O3The thickness of the gate dielectric is 30 nm). (4) To be Al2O3And after the gate dielectric grows, taking out the silicon wafer (attached with the graphene).
Fifthly, preparing a graphene top gate electrode: and repeating the second step to obtain the graphene top gate electrode. Here, in order to reduce parasitic capacitance and enhance gate control characteristics, the top gate electrode completely covers the graphene conductive channel. But also avoid overlapping with the source and drain electrodes, and avoid leakage of the device. Here, the top gate electrode was still plated with 4nm Ti and then 50nm Au.
Sixthly, packaging the top gate graphene field effect transistor: (1) and fixing the silicon wafer attached with the graphene nanosheets on a pin chip carrier (type: R-150-0 XX-1X-0X-0000) by using conductive silver paste glue. (2) The black phosphorus top gate device prepared in the previous step was packaged into a pin chip carrier using a wire-down machine (model: West Bond). Here we use the package parameters: bonding force: 30g/N (or 28g/N, 29g/N, 30g/N, 31g/N, 32 g/N), bonding strength (relative value): 60 (or 58, 59, 60, 61, 62), bonding time: 25 μ s (or 23 μ s, 24 μ s, 25 μ s, 26 μ s, 27 μ s), bonding point length: 19 μm (or 18 μm, 19 μm, 20 μm).
The above examples are high quality Al grown on graphene2O3The gate dielectric is illustrated as an example, but the method of the present invention is not limited to graphene, and the present invention is not limited to grapheneThe method is also suitable for other two-dimensional materials, and through atomic force characterization, the method can also be used for molybdenum telluride (MoTe) after pretreatment by utilizing a thermal evaporation aluminum seed layer2) And Black Phosphorus (BP) to form dense Al2O3A film. These results indicate that high quality Al can be achieved by functionalizing the two-dimensional material surface with a thermally evaporated aluminum seed layer2O3And growing the gate dielectric to obtain the high-performance top gate type field effect transistor.
The above description is only for the preferred embodiment of the present application and should not be taken as limiting the present application in any way, and although the present application has been disclosed in the preferred embodiment, it is not intended to limit the present application, and those skilled in the art should understand that they can make various changes and modifications within the technical scope of the present application without departing from the scope of the present application, and therefore all the changes and modifications can be made within the technical scope of the present application.
Claims (6)
1. A method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer is characterized in that an ultrathin metal medium is thermally evaporated to the surface of a two-dimensional material, then the surface of the two-dimensional material is dried and naturally oxidized into the seed layer in a drying box, and then a high-dielectric-constant gate medium is grown on the surface of the two-dimensional material by utilizing an atomic layer deposition method.
2. The method of claim 1, wherein the high-k gate dielectric is Al2O3Gate dielectric or HfO2And a gate dielectric.
3. The method of claim 1, comprising the steps of:
1) stripping the two-dimensional material crystal onto a silicon wafer by using a micro-mechanical stripping method so as to attach a single-layer two-dimensional material nanosheet onto the silicon wafer;
2) forming a source electrode pattern and a drain electrode pattern on a silicon wafer attached with a single-layer two-dimensional material nanosheet by using an electron beam exposure method, and preparing the source electrode and the drain electrode by using a thermal evaporation coating and stripping process;
3) evaporating ultrathin metal aluminum to the surface of the two-dimensional material nanosheet between the source electrode and the drain electrode by using a thermal evaporation coating machine, and after evaporation is finished, putting the silicon wafer into a drying box for natural oxidation to completely oxidize an ultrathin metal Al medium obtained by thermal evaporation;
4) growing Al on the surface of the ultrathin metal Al medium obtained in the step 3) by utilizing an atomic layer deposition method2O3A gate dielectric;
5) al by electron beam exposure2O3Forming a gate electrode pattern on the gate dielectric, and preparing a gate electrode by using electron beam coating;
6) and packaging to obtain the finished product.
4. The method of claim 3, wherein the step 3) comprises:
(1) placing the silicon wafer with the prepared source electrode and drain electrode into an evaporation chamber of a thermal evaporation coating machine, and vacuumizing to ensure that the pressure in the evaporation chamber is only 110-5Pa；
(2) Starting a thermal evaporation coating machine to coat an ultrathin metal medium Al on the surface of the two-dimensional material of the silicon wafer, wherein the coating parameters are as follows: al deposition thickness 2 nm, evaporation rate: 0.3A/s;
(3) and after the film coating is finished, taking out the silicon wafer, and putting the silicon wafer into a drying box with the temperature of 25 ℃ and the relative humidity of 20% for oxidizing for 30 minutes to completely oxidize the ultrathin metal aluminum obtained by thermal evaporation on the silicon wafer.
5. The method of claim 3, wherein the atomic layer deposition method comprises:
(1) placing the silicon wafer attached with the two-dimensional material nanosheet into a reaction chamber, and introducing nitrogen with the purity of 99.9997% and the gas flow flux of 40 sccm for cleaning for 20 minutes;
(2) setting the temperature rise time to be 25-35 min, and heating the reaction cavity to 148-152 ℃;
(3) introducing trimethylaluminum and distilled water into the reaction cavity, setting the introduction time of the trimethylaluminum to be 8-12 s, the introduction time of the distilled water to be 8-12 s, switching the valve for 0.015s, and performing 273 cycles by taking the valve as a cycle until Al with the thickness of 30nm grows on the silicon wafer attached with the two-dimensional material nanosheets2O3A gate dielectric;
(4) to be Al2O3And taking out the gate dielectric after the growth of the gate dielectric is finished.
6. The method for preparing a top-gate field effect transistor by using the thermally evaporated aluminum seed layer as claimed in claim 3, wherein the gate electrode completely covers the conductive channel of the two-dimensional material nanosheet.
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