CN111627933A - 主动元件基板及其制造方法 - Google Patents
主动元件基板及其制造方法 Download PDFInfo
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- CN111627933A CN111627933A CN202010504481.5A CN202010504481A CN111627933A CN 111627933 A CN111627933 A CN 111627933A CN 202010504481 A CN202010504481 A CN 202010504481A CN 111627933 A CN111627933 A CN 111627933A
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- layer
- electrode
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- metal oxide
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- 239000000758 substrate Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 71
- 239000010703 silicon Substances 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 50
- 229910044991 metal oxide Inorganic materials 0.000 claims description 60
- 150000004706 metal oxides Chemical class 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 59
- 239000003990 capacitor Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 40
- 230000000149 penetrating effect Effects 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 239000007769 metal material Substances 0.000 description 27
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910010272 inorganic material Inorganic materials 0.000 description 5
- 239000011147 inorganic material Substances 0.000 description 5
- 239000011368 organic material Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- ZBFOLPMOGPIUGP-UHFFFAOYSA-N dizinc;oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Zn+2].[Zn+2] ZBFOLPMOGPIUGP-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- BDVZHDCXCXJPSO-UHFFFAOYSA-N indium(3+) oxygen(2-) titanium(4+) Chemical compound [O-2].[Ti+4].[In+3] BDVZHDCXCXJPSO-UHFFFAOYSA-N 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种主动元件基板及其制造方法,主动元件基板包括基板、硅层、第一绝缘层、第一栅极、第一介电层、第一转接电极、第二转接电极以及第二介电层。两个开口贯穿第一介电层并重叠于硅层。第一转接电极以及第二转接电极分别位在两个开口中。第二介电层位在第一转接电极以及第二转接电极上。两个第一通孔贯穿第二介电层。第一转接电极以及第二转接电极为两个第一通孔的蚀刻中止层。
Description
技术领域
本发明涉及一种主动元件基板,且特别涉及一种包括硅层的主动元件基板及其制造方法。
背景技术
显示装置中往往包含了许多的主动元件,为了因应各种不同的功能需求,显示装置中可能含有一种以上的主动元件。举例来说,在显示装置中,为了获得较好的产品性能,位于驱动电路中的主动元件可能与位于像素中的主动元件具有不同的阻抗。
在现有技术中,可以通过调整主动元件的通道层长度或通道层的掺杂浓度以获得不同阻抗的主动元件。然而,仅通过调整主动元件的通道层长度难以满足所有的需求。因此,为了形成性能差异较大的主动元件,往往需要增加许多的工艺步骤,这导致了显示装置的制造成本大幅上升。
发明内容
本发明提供一种主动元件基板,可以改善硅层过度蚀刻的问题。
本发明提供一种主动元件基板的制造方法,可有效改善因过度蚀刻造成桥接不良的问题。
本发明的至少一实施例提供一种主动元件基板。主动元件基板包括基板、硅层、第一绝缘层、第一栅极、第一介电层、第一转接电极、第二转接电极、第二介电层、金属氧化物通道层、第二栅极、第一源极、第一漏极、第二源极以及第二漏极。硅层位在基板上。第一绝缘层位在硅层上。第一栅极位在第一绝缘层上。第一介电层位在第一栅极上。两个开口至少贯穿第一介电层,且两个开口重叠于硅层。第一转接电极以及第二转接电极分别位在两个开口中。第一转接电极以及第二转接电极分别连接硅层。第二介电层位在第一转接电极以及第二转接电极上。两个第一通孔至少贯穿第二介电层。第一转接电极以及第二转接电极为两个第一通孔的蚀刻中止层。金属氧化物通道层位于第二介电层上方。第二栅极重叠于金属氧化物通道层。第一源极以及第一漏极位在两个第一通孔中。第一源极以及第一漏极分别电性连接第一转接电极以及第二转接电极。第二源极以及第二漏极电性连接金属氧化物通道层。
本发明的至少一实施例提供一种主动元件基板的制造方法,包括以下步骤。形成硅层于基板上。形成第一绝缘层于硅层上。形成第一栅极于第一绝缘层上。形成第一介电层于第一栅极上。执行第一蚀刻工艺以形成至少贯穿第一介电层的两个开口。两个开口暴露出硅层。形成第一转接电极以及第二转接电极于两个开口中,以连接硅层。形成第二介电层于第一转接电极以及第二转接电极上。执行第二蚀刻工艺以形成至少贯穿第二介电层的两个第一通孔,其中第一转接电极以及第二转接电极为两个第一通孔的蚀刻中止层。形成金属氧化物通道层于第二介电层上方。形成第二栅极于基板上方。分别形成第一源极以及第一漏极于两个第一通孔中。形成第二源极以及第二漏极于金属氧化物通道层上。
本发明的至少一实施例提供一种主动元件基板的制造方法,包括以下步骤。形成硅层于基板上。形成第一绝缘层于硅层上。形成第一栅极于第一绝缘层上。形成第一介电层于第一栅极上。执行第一蚀刻工艺以形成至少贯穿第一介电层的两个第一通孔。两个第一通孔暴露出硅层。形成氧化物层于第一介电层上方。氧化物层包括两个保护电极以及分离于两个保护电极的金属氧化物通道层。两个保护电极分别填入两个第一通孔且连接硅层。形成第一源极以及第一漏极于两个保护电极上。形成第二源极以及第二漏极于金属氧化物通道层上。
附图说明
图1A至图1G是依照本发明一实施例的一种显示装置的制造方法的剖面示意图。
图2是依照本发明另一实施例的一种显示装置的剖面示意图。
图3是依照本发明又一实施例的一种显示装置的剖面示意图。
图4A至图4E是依照本发明又一实施例的一种显示装置的制造方法的剖面示意图。
图5A至图5E是依照本发明又一实施例的一种显示装置的制造方法的剖面示意图。
附图标记说明:
1、2、3、4、5:显示装置
10、20、30、40、50:主动元件基板
100:基板
102:绝缘层
110:硅层
112、114:掺杂区
113、115:轻掺杂区
116:通道区
120:第一绝缘层
122:第二绝缘层
130:第一介电层
132:第二介电层
134:介电层
136:第三介电层
140、140’:金属氧化物通道层
140”:氧化物材料层
140a:氧化物层
142、144:导电区
146:半导体区
148a、148a’、148b、148b’:保护电极
150:钝化层
152:平坦层
154:第一电极
156:像素定义层
158:间隙物
160:开口
162:发光层
164:第二电极
212、214:第一通孔
216:第二通孔
218、220、232、234、236、240:第三通孔
300:光刻胶层
300’:图案化光刻胶层
310:半调式掩模
M:金属材料层
D1:第一漏极
D2:第二漏极
S1:第一源极
S2:第二源极
G1:第一栅极
G2:第二栅极
CE1:电容电极
OP1、OP2:开口
TE1:第一转接电极
TE2:第二转接电极
具体实施方式
图1A至图1G是依照本发明一实施例的一种显示装置的制造方法的剖面示意图。
请参考图1A,提供基板100。基板100的材料可包括玻璃、石英、有机聚合物、或是不透光/反射材料(例如:导电材料、金属、晶圆、陶瓷或其他相似材料)或是其它合适的材料。
形成硅层110于基板100上。在一些实施例中,选择性地先形成绝缘层102于基板100上,再形成硅层110于绝缘层102上。绝缘层102的材料可包括氧化硅。当基板100的材料为导电材料或金属时,绝缘层102可避免发生短路。此外,绝缘层102还可阻挡基板100材料(例如:氮化硅、玻璃杂质)的扩散,并阻挡硅层110的蓄热。硅层110包含非晶硅、多晶硅、微晶硅、单晶硅或上述的组合。在本实施例中,硅层110例如为低温多晶硅(Low TemperaturePoly-Silicon;LTPS),且硅层110包括两个掺杂区112、114、位在两个掺杂区112、114之间的通道区116以及位在两个掺杂区112、114与通道区116之间的轻掺杂区113、115。在一些实施例中,轻掺杂区113、115的掺杂浓度小于掺杂区112、114的掺杂浓度。
形成第一绝缘层120在硅层110上。在本实施例中,第一绝缘层120覆盖在硅层110的顶面与侧壁上,且延伸至基板100的表面上。也就是说,第一绝缘层120共形于基板100与硅层110,但本发明不以此为限。在其他实施例中,第一绝缘层可只覆盖在通道层116上。
第一绝缘层120的材料例如包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料或其它合适的材料或上述的组合。此处,第一绝缘层120的厚度例如是10纳米至200纳米,在此厚度范围内,第一绝缘层120能有较佳的栅极控制能力,并可预防栅极电流的穿透,此外,此厚度范围内的第一绝缘层120的工艺良率较高,且硅层110所对应的主动元件能有较佳的效能,但本发明不以此为限。
形成第一栅极G1以及电容电极CE1于第一绝缘层120上。第一绝缘层120位于第一栅极G1与通道层116之间。第一栅极G1于基板100上的正投影重叠于硅层110于基板100上的正投影,且电容电极CE1于基板100上的正投影不重叠于硅层110于基板100上的正投影。
在本实施例中,第一栅极G1以及电容电极CE1属于同一膜层。举例来说,可先形成金属材料层(未示出)在第一绝缘层120上,而后对金属材料层进行光刻蚀刻工艺,以形成第一栅极G1以及电容电极CE1,但本发明不以此为限。第一栅极G1和电容电极CE1的材料例如是金属材料、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或其它合适的材料或是金属材料与其它导电材料的堆叠层。
请参考图1B,形成第一介电层130于第一栅极G1上。第一介电层130覆盖第一栅极G1、电容电极CE1以及第一绝缘层120。第一栅极G1以及电容电极CE1皆位于第一绝缘层120与第一介电层130之间。第一介电层130的材料可例如包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料或其它合适的材料或上述的组合,但本发明不以此为限。
执行第一蚀刻工艺以形成至少贯穿第一介电层130的两个开口OP1、OP2。在本实施例中,开口OP1贯穿第一介电层130以及第一绝缘层120并暴露出硅层110的掺杂区112,开口OP2贯穿第一介电层130以及第一绝缘层120并暴露出硅层110的掺杂区114。第一介电层130的厚度例如是10纳米至500纳米,在此厚度范围内,第一介电层130的工艺良率较高,且第一介电层130所对应的存储电容能有较佳的效能,但本发明不以此为限。在本实施例中,开口OP1、OP2仅需贯穿厚度较薄的第一介电层130以及第一绝缘层120,因此,较容易在不过度伤害硅层110的前提下使第一蚀刻工艺蚀刻停止于硅层110,有效改善因过度蚀刻造成的问题。
请参考图1C,形成第一转接电极TE1以及第二转接电极TE2于第一介电层130上。第一转接电极TE1以及第二转接电极TE2分别填入两个开口OP1、OP2中。第一转接电极TE1连接硅层110的掺杂区112,且第二转接电极TE2连接硅层110的掺杂区114。
在本实施例中,第二转接电极TE2于基板100上的正投影重叠于电容电极CE1于基板100上的正投影,且第一介电层130夹置于第二转接电极TE2与电容电极CE1之间,因此,第二转接电极TE2与电容电极CE1之间具有电容(例如为存储电容)。
在本实施例中,第一转接电极TE1与第二转接电极TE2为同一膜层。举例来说,先形成金属材料层(未示出)在第一介电层130上及两个开口OP1、OP2中,而后对金属材料层进行光刻蚀刻工艺,以形成第一转接电极TE1以及第二转接电极TE2,但本发明不限于此。第一转接电极TE1和第二转接电极TE2的材料例如是金属材料、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或其它合适的材料或是金属材料与其它导电材料的堆叠层。
形成第二介电层132于第一转接电极TE1以及第二转接电极TE2上。在本实施例中,第二介电层132可覆盖第一转接电极TE1、第二转接电极TE2以及第一介电层130。第二介电层132的厚度例如介于0.1微米至1.5微米。在本实施例中,第二介电层132的材料可例如包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料或其它合适的材料或上述的组合,但本发明不以此为限。
可选择地形成介电层134在第二介电层132上。介电层134的厚度例如介于0.1微米至1.5微米。在本实施例中,介电层134的材料例如包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料或其它合适的材料或上述的组合,但本发明不以此为限。
请参考图1D,形成金属氧化物通道层140于第二介电层132上方。在本实施例中,金属氧化物通道层140形成于介电层134上。在本实施例中,金属氧化物通道层140包括两个导电区142、144以及位在两个导电区142、144之间的半导体区146。在另一实施例中,金属氧化物通道层140的导电区142、144例如是导体或半导体。
金属氧化物通道层140的材料例如是铟镓锌氧化物(Indium Gallium ZincOxide,IGZO)、铟锌氧化物、铟氧化物、锌氧化物、铟钛氧化物或锌钛氧化物等,但不以此为限。在一些实施例中,例如通过掺杂工艺或等离子体处理工艺(例如为氢等离子体处理工艺或其他等离子体处理工艺)以使导电区142、144与半导体区146具有不同的导电率,但本发明不以此为限。
形成第二栅极G2于基板100上方。在本实施例中,形成第二栅极G2于金属氧化物通道层140上。在本实施例中,第二栅极G2与金属氧化物通道层140之间还夹有第二绝缘层122,第二栅极G2与第二绝缘层122例如是于同一道图案化工艺中形成。在本实施例中,第二栅极G2与第二绝缘层122例如可作为等离子体处理工艺的掩模,换句话说,金属氧化物通道层140的半导体区146于基板100上的正投影与第二栅极G2于基板100上的正投影具有相同形状。在其他实施例中,第二栅极G2与第二绝缘层122亦可通过不同道图案化工艺所形成,换句话说,第二绝缘层122于基板100上的正投影与第二栅极G2于基板100上的正投影可以具有不同形状。
请参考图1E,形成第三介电层136于金属氧化物通道层140上。第三介电层136可覆盖第二介电层132、介电层134、金属氧化物通道层140以及第二栅极G2。在本实施例中,第二栅极G2位在金属氧化物通道层140与第三介电层136之间。
在本实施例中,第三介电层136的材料例如包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料或其它合适的材料或上述的组合,但本发明不以此为限。
执行第二蚀刻工艺以形成至少贯穿第二介电层132的两个第一通孔212、214。在本实施例中,第二蚀刻工艺是于形成第三介电层136之后执行,且第一通孔212、214贯穿第二介电层132、介电层134以及第三介电层136。第一通孔212暴露出第一转接电极TE1,且第二通孔214暴露出第二转接电极TE2。在其他实施例中,当第二栅极G2与第二绝缘层122亦可通过不同道图案化工艺所形成时,第二绝缘层122的面积大于第二栅极G2,且第二蚀刻工艺,且第一通孔212、214可贯穿第二介电层132、介电层134、第二绝缘层122以及第三介电层136。
在第二蚀刻工艺中,由于介电层(第二介电层132、介电层134以及第三介电层136)与第一转接电极TE1的蚀刻选择比高,且介电层(第二介电层132、介电层134以及第三介电层136)与第二转接电极TE2的蚀刻选择比高,因此第一转接电极TE1与第二转接电极TE2可分别作为第一通孔212、214的蚀刻中止层。
基于前述,由于设置了可作为蚀刻中止层的第一转接电极TE1与第二转接电极TE2,即使第二蚀刻工艺需要蚀刻厚度较厚的第二介电层132、介电层134以及第三介电层136,硅层110仍然不会在第二蚀刻工艺中受损。换句话说,第二蚀刻工艺能够有较高的蚀刻裕度(Etching Margin)。
在本实施例中,在第二蚀刻工艺时,还可形成至少贯穿第一介电层130以及第二介电层132的第二通孔216。在本实施例中,第二通孔216还贯穿介电层134以及第三介电层136。第二通孔216暴露出电容电极CE1。
在本实施例中,由于介电层(第一介电层130、第二介电层132、介电层134以及第三介电层136)与电容电极CE1的蚀刻选择比高,因此,电容电极CE1可为第二通孔216的蚀刻中止层。
在本实施例中,在第二蚀刻工艺时,还可形成贯穿第三介电层136的两个第三通孔218、220。第三通孔218重叠金属氧化物通道层140的导电区142。第三通孔220重叠金属氧化物通道层140的导电区144。换句话说,第三通孔218暴露出金属氧化物通道层140的导电区142,且第三通孔220暴露出金属氧化物通道层140的导电区144。
虽然在本实施例中,先形成第三介电层136接着才进行第二蚀刻工艺以形成第一通孔212、214,但本发明不以此为限。在其他实施例中,先执行第二蚀刻工艺,接着形成第三介电层136,然后才于第三介电层136中形成通孔。
请参考图1F,分别形成第一源极S1以及第一漏极D1于第一通孔212、214中。在本实施例中,形成第一源极S1以及第一漏极D1于第三介电层136上,其中第一源极S1形成于第一通孔212中,且第一漏极D1形成于第一通孔214中。在本实施例中,第一源极S1直接连接第一转接电极TE1并通过第一转接电极TE1而电性连接至硅层110,且第一漏极D1直接连接第二转接电极TE2并通过第二转接电极TE2而电性连接至硅层110。
形成第二源极S2以及第二漏极D2于金属氧化物通道层140上。在本实施例中,形成第二源极S2以及第二漏极D2于第三介电层136上,其中第二源极S2形成于第二通孔216以及第三通孔218中,且第二漏极D2形成于第三通孔220中。在本实施例中,第二源极S2以及第二漏极D2分别通过第三通孔218以及第三通孔220而电性连接金属氧化物通道层140。第二源极S2通过第二通孔216而电性连接电容电极CE1。
在本实施例中,第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2属于同一膜层。举例来说,可先形成一电极材料层(未示出)在第三介电层136的上方,接着再对电极材料层进行光刻蚀刻工艺,以形成第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2的材料例如是金属材料、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或其它合适的材料、堆叠的金属材料或是金属材料与其它导电材料的堆叠层,但不以此为限。
在本实施例中,第一主动元件包括第一源极S1、第一漏极D1、第一转接电极TE1、第二转接电极TE2、第一栅极G1以及硅层110,且第一主动元件具有高电子迁移率以及可靠度高的优点。第二主动元件包括第二源极S2、第二漏极D2、第二栅极G2以及金属氧化物通道层140,且第二主动元件具有低漏电的优点。
至此,本实施例的主动元件基板10已大致完成。
请参考图1G,形成钝化层150于第三介电层136上。形成平坦层152于钝化层150上。钝化层150覆盖第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。
形成第一电极154于平坦层152上。第一电极154电性连接第一漏极D1。形成像素定义层156于平坦层152上,并形成间隙物158于像素定义层156上。在本实施例中,像素定义层156具有暴露出第一电极154的开口160。形成发光层162于开口160中。形成第二电极164于发光层162上。
至此,已大致完成显示装置1的制作。在本实施例中,显示装置1为有机发光二极管显示装置,但本发明不以此为限。在其他实施例中,主动元件基板10适用于其他电子装置,例如液晶显示装置(liquid crystal display device)、微发光二极管显示装置(microLEDs display device)或其他电子装置。
在此必须说明的是,下述实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参照前述实施例,下述实施例不再重复赘述。
图2是依照本发明另一实施例的一种显示装置的剖面示意图。
请参考图2与图1G,显示装置2与显示装置1的差异在于:显示装置2的主动元件基板20包括保护电极148a、148b。
在本实施例中,在形成第三介电层136前,先执行第二蚀刻工艺以形成第一通孔212、214以及第二通孔216。第一通孔212、214贯穿第二介电层132以及介电层134,第二通孔216贯穿第一介电层130、第二介电层132以及介电层134。
接着分别于第一通孔212、214中形成保护电极148a、148b,且部分金属氧化物通道层140形成于第二通孔216中。
在本实施例中,保护电极148a、148b与金属氧化物通道层140属于同一膜层。换句话说,保护电极148a、148b与金属氧化物通道层140是在同个工艺步骤中形成。在本实施例中,保护电极148a、148b与金属氧化物通道层140的导电区142、144具有相似的导电率,但本发明不以此为限。
形成第二绝缘层122以及第二栅极G2于金属氧化物通道层140上。
在形成第三介电层136之后,执行第三蚀刻工艺以形成贯穿第三介电层136的四个第三通孔232、234、236、240。第三通孔232、234分别暴露出保护电极148a、148b,且第三通孔236、240分别暴露出金属氧化物通道层140的导电区142、144。
形成第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2于第三介电层136上。在本实施例中,第一源极S1位在第三通孔232中,且通过位于第一通孔212中的保护电极148a电性连接至第一转接电极TE1。第一漏极D1位在第三通孔234中,且通过位于第一通孔214中的保护电极148b电性连接至第二转接电极TE2。第二源极S2位在第三通孔236中,且通过位于第二通孔216中的部分金属氧化物通道层140而电性连接至电容电极CE1。
在本实施例中,保护电极148a、148b与金属氧化物通道层140可以避免第一转接电极TE1、第二转接电极TE2以及电容电极CE1的表面受损,借此增加主动元件基板20的良率。
图3是依照本发明又一实施例的一种显示装置的剖面示意图。
请参考图3与图2,显示装置3与显示装置2的差异处在于:显示装置3的主动元件基板30的第二栅极G2位于金属氧化物通道层140与基板100之间。
在本实施例中,第二栅极G2位于基板100上方,且位于第一介电层130与第二介电层132之间。也就是说,本实施例的第二栅极G2、第一转接电极TE1与第二转接电极TE2是在同一工艺步骤完成,但本发明不以此为限。在其他实施例中,第二栅极G2位于第一介电层130与第一绝缘层120之间。
因此,本实施例的主动元件基板30,具有简化工艺的优点。
图4A至图4E是依照本发明又一实施例的一种显示装置4的制造方法的剖面示意图。
请参考图4A,提供基板100。形成绝缘层102于基板100上。形成硅层110于绝缘层102上。形成第一绝缘层120于硅层110上。
形成第一栅极G1、电容电极CE1以及第二栅极G2于第一绝缘层120上。第一栅极G1于基板100上的正投影重叠于硅层110于基板100上的正投影,且不重叠于电容电极CE1于基板100上的正投影以及第二栅极G2于基板100上的正投影。
在本实施例中,第一栅极G1、电容电极CE1以及第二栅极G属于同一膜层。举例来说,可先形成金属材料层(未示出)在第一绝缘层120上,而后对金属材料层进行光刻蚀刻工艺,以形成第一栅极G1、电容电极CE1以及第二栅极G2,但本发明不限于此。
请参考图4B,形成第一介电层130于第一栅极G1上,第一介电层130可覆盖第一栅极G1、电容电极CE1、第二栅极G2以及第一绝缘层120。第一栅极G1、电容电极CE1以及第二栅极G2位于第一绝缘层120与第一介电层130之间。可选地形成第二介电层132以覆盖第一介电层130。
请参考图4C,执行第一蚀刻工艺以形成至少贯穿第一介电层130的两个第一通孔212、214,其中第一通孔212、214暴露出硅层110。在本实施例中,第一通孔212、214贯穿第一绝缘层120、第一介电层130以及第二介电层132。第一通孔212暴露出硅层110的掺杂区112,且第二通孔214暴露硅层110的掺杂区114。
在第一蚀刻工艺时,还可形成贯穿第一介电层130、第二介电层132的第二通孔216。由于电容电极CE1的蚀刻选择比高,因此,电容电极CE1可为第二通孔216的蚀刻中止层。此处,第二通孔216暴露出电容电极CE1。
形成氧化物层140a于第一介电层130上方。在本实施例中,第二介电层132位于第一介电层130与氧化物层140a之间,且氧化物层140a形成于第二介电层132上。氧化物层140a包括保护电极148a、148b以及分离于保护电极148a、148b的金属氧化物通道层140。
保护电极148a填入第一通孔212中,并连接硅层110的掺杂区112。保护电极148b填入第一通孔214中,并连接硅层110的掺杂区114。金属氧化物通道层140填入第二通孔216中,并连接电容电极CE1。在本实施例中,第二栅极G2于基板100上的正投影重叠于氧化物通道层140于基板100上的正投影。
在本实施例中,部分第一介电层130以及部分第二介电层132位于保护电极148b与电容电极CE1之间,因此,保护电极148b与电容电极CE1之间具有电容(例如为存储电容)。
请参考图4D,形成第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2于该氧化物层140a上。在本实施例中,第一源极S1以及第一漏极D1形成于保护电极148a、148b上,且第二源极S2以及第二漏极D2形成于金属氧化物通道层140上。第一源极S1位在第一通孔212中,且通过保护电极148a电性连接硅层110。第一漏极D1位在第一通孔214中,且通过保护电极148b电性连接硅层110。在本实施例中,电容电极CE1重叠第一漏极D1。第二源极S2位在第二通孔216中通过金属氧化物通道层140电性连接电容电极CE1。举例来说,部分金属氧化物通道层140填入第二通孔216中,且连接第二源极S2以及电容电极CE1。
第二源极S2与第二漏极D2直接连接金属氧化物通道层140。
至此,本实施例的主动元件基板40已大致完成。
请参考图4E,形成第三介电层136覆盖第一源极S1、第一漏极D1、第二源极S2、第二漏极D2以及氧化物140a层。形成平坦层152于第三介电层136上。
请继续参考图4E,继续可在主动元件基板40上堆叠第一电极154、像素定义层156、间隙物158、发光层162以及第二电极164,以进一步制作显示装置4。
图5A至图5E是依照本发明又一实施例的一种显示装置的制造方法的剖面示意图。
图5A继续图4B的步骤。请参考图5A,执行第一蚀刻工艺以形成至少贯穿第一介电层130的两个第一通孔212、214,其中两个第一通孔212、214暴露出该硅层110。在本实施例中,第一通孔212、214贯穿第一绝缘层120、第一介电层130以及第二介电层132,其中第一通孔212暴露出硅层110的掺杂区112,且第二通孔214暴露硅层110的掺杂区114。在此步骤中,也同时形成至少贯穿第一介电层130、第二介电层132的第二通孔216,且电容电极CE1可为第二通孔216的蚀刻中止层。此处,第二通孔216暴露出电容电极CE1。
请继续参考图5A。形成氧化物材料层140”于第一介电层130上方,形成金属材料层M在氧化物材料层140”上,且形成光刻胶层300在金属材料层M上。
请参照图5B至图5D,提供半调式掩模(Half-tone mask)310以进行光刻蚀刻工艺。
以半调式掩模310为遮罩图案化光刻胶层300,以形成图案化光刻胶层300’。在本实施例中,图案化光刻胶层300’包括厚度不同的区域。
接着以图案化光刻胶层300为掩模进行蚀刻工艺,以移除部分金属材料层M以及部分氧化物材料层140”。
同步形成两个保护电极148a’、148b’、金属氧化物通道层140’、第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。如此,可有效的减少工艺步骤以及所需掩模,达到简化工艺的作用。在本实施例中,由于金属材料层M对应于第二源极S2以及第二漏极D2之间的位置重叠于部分图案化光刻胶层300’,因此,在第二源极S2以及第二漏极D2之间,对应该部分图案化光刻胶层300’的金属氧化物通道层140’可以在蚀刻工艺后保留下来。
在本实施例中,位在第一通孔212外的保护电极148a的侧壁切齐于第一源极S1的侧壁,且位在第一通孔214外的保护电极148a的侧壁切齐于第一漏极D1的侧壁。在本实施例中,第二源极S2的部分侧壁以及第二漏极D2的部分侧壁切齐于金属氧化物通道层140’的侧壁。
至此,主动元件基板50大致完成。
请参照图5E,形成第三介电层136覆盖第一源极S1、第一漏极D1、第二源极S2、第二漏极D2以及第二介电层132。形成平坦层152于第三介电层136上。
继续可按序形成第一电极154、像素定义层156、间隙物158、发光层162以及第二电极164,以完成显示装置5的制作。
综上所述,本发明的主动元件基板可以改善硅层因为过度蚀刻而出现良率不佳的问题。
虽然本发明已以实施方式公开如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的构思和范围内,当可作些许的变动与润饰,故本发明的保护范围当视权利要求所界定者为准。
Claims (15)
1.一种主动元件基板,包括:
一基板;
一硅层,位在该基板上;
一第一绝缘层,位在该硅层上;
一第一栅极,位在该第一绝缘层上;
一第一介电层,位在该第一栅极上,其中两个开口至少贯穿该第一介电层,且该两个开口重叠于该硅层;
一第一转接电极以及一第二转接电极,分别位在该两个开口中,其中该第一转接电极以及该第二转接电极分别连接该硅层;
一第二介电层,位在该第一转接电极以及该第二转接电极上,其中两个第一通孔至少贯穿该第二介电层,且该第一转接电极以及该第二转接电极为该两个第一通孔的蚀刻中止层;
一金属氧化物通道层,位于该第二介电层上方;
一第二栅极,重叠于该金属氧化物通道层;以及
一第一源极、一第一漏极、一第二源极以及一第二漏极,其中该第一源极以及该第一漏极位在该两个第一通孔中,且该第一源极以及该第一漏极分别电性连接该第一转接电极以及该第二转接电极,其中该第二源极以及该第二漏极电性连接该金属氧化物通道层。
2.如权利要求1所述的主动元件基板,其中该两个开口贯穿该第一绝缘层,且该第一绝缘层的厚度为10纳米至200纳米。
3.如权利要求1所述的主动元件基板,其中该第一介电层的厚度为10纳米至500纳米。
4.如权利要求1所述的主动元件基板,还包括:
两个保护电极,位在该两个第一通孔中,其中该两个保护电极分别连接该第一转接电极以及该第二转接电极。
5.如权利要求4所述的主动元件基板,其中该两个保护电极与该金属氧化物通道层属于同一膜层。
6.如权利要求1所述的主动元件基板,还包括:
一电容电极,位于该第一绝缘层上,且重叠于该第二转接电极,其中该第二源极通过一第二通孔而电性连接该电容电极,且该第二通孔至少贯穿该第一介电层以及该第二介电层。
7.如权利要求6所述的主动元件基板,其中部分该金属氧化物通道层位于该第二通孔中。
8.如权利要求1所述的主动元件基板,其中该第二栅极位在该金属氧化物通道层与该基板之间。
9.如权利要求1所述的主动元件基板,还包括:
一第三介电层,位于该金属氧化物通道层上,其中该第二栅极位在该金属氧化物通道层与该第三介电层之间。
10.如权利要求1所述的主动元件基板,还包括:
一第三介电层,位于该金属氧化物通道层上,其中两个第三通孔至少贯穿该第三介电层,且该两个第一通孔更贯穿该第三介电层,其中、该第二源极以及该第二漏极位于该两个第三通孔中。
11.一种主动元件基板的制造方法,包括:
形成一硅层于一基板上;
形成一第一绝缘层于该硅层上;
形成一第一栅极于该第一绝缘层上;
形成一第一介电层于该第一栅极上;
执行一第一蚀刻工艺以形成至少贯穿该第一介电层的两个开口,其中该两个开口暴露出该硅层;
形成一第一转接电极以及一第二转接电极于该两个开口中,以连接该硅层;
形成一第二介电层于该第一转接电极以及该第二转接电极上;
执行一第二蚀刻工艺以形成至少贯穿该第二介电层的两个第一通孔,其中该第一转接电极以及该第二转接电极为该两个第一通孔的蚀刻中止层;
形成一金属氧化物通道层于该第二介电层上方;
形成一第二栅极于该基板上方;
分别形成一第一源极以及一第一漏极于该两个第一通孔中;以及
形成一第二源极以及一第二漏极于该金属氧化物通道层上。
12.一种主动元件基板的制造方法,包括:
形成一硅层于一基板上;
形成一第一绝缘层于该硅层上;
形成一第一栅极于该第一绝缘层上;
形成一第一介电层于该第一栅极上;
执行一第一蚀刻工艺以形成至少贯穿该第一介电层的两个第一通孔,其中该两个第一通孔暴露出该硅层;
形成一氧化物层于该第一介电层上方,其中该氧化物层包括两个保护电极以及分离于该两个保护电极的一金属氧化物通道层,其中该两个保护电极分别填入该两个第一通孔且连接该硅层;
形成一第一源极以及一第一漏极于该两个保护电极上;以及
形成一第二源极以及一第二漏极于该金属氧化物通道层上。
13.如权利要求12所述的主动元件基板的制造方法,还包括:
形成一氧化物材料层于该第一介电层上方;
形成一金属层在该氧化物材料层上;以及
执行一蚀刻工艺以同步形成该两个保护电极、该金属氧化物通道层、该第一源极、该第一漏极、该第二源极以及该第二漏极。
14.如权利要求12所述的主动元件基板的制造方法,还包括:
形成一电容电极于该第一绝缘层上,其中该电容电极重叠该第一漏极,其中一第二通孔至少贯穿该第一介电层,且该第二源极位在该第二通孔中且电性连接该电容电极。
15.如权利要求14所述的主动元件基板的制造方法,其中部分该金属氧化物通道层填入该第二通孔中,且连接该第二源极以及该电容电极。
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