CN111624532A - Magnetoresistive sensor system - Google Patents
Magnetoresistive sensor system Download PDFInfo
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- CN111624532A CN111624532A CN202010525702.7A CN202010525702A CN111624532A CN 111624532 A CN111624532 A CN 111624532A CN 202010525702 A CN202010525702 A CN 202010525702A CN 111624532 A CN111624532 A CN 111624532A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
- G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
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- G01R33/095—Magnetoresistive devices extraordinary magnetoresistance sensors
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Abstract
The invention discloses a magnetic resistance sensor system, belonging to the technical field of magnetic resistance sensors, comprising: the first AMR magnetoresistive sensor is arranged on the first flat coil and comprises a first signal output end; the second AMR magnetoresistive sensor is arranged on the second flat coil and comprises a second signal output end; the differential amplifier comprises a first input end, a second input end, a feedback end and a voltage output end, wherein the first signal output end is connected with the first input end, and the second signal output end is connected with the second input end; a feedback circuit is arranged between the voltage output ends and outputs a feedback signal to the feedback end; the beneficial effects are that: not only the output rate of data is increased, but also the sensitivity of magnetic field measurement is improved.
Description
Technical Field
The invention relates to the technical field of magnetoresistive sensors, in particular to a dual-heterogeneous magnetoresistive sensor system.
Background
The basic structure of the AMR magnetoresistive sensor is composed of a Wheatstone bridge composed of four magnetoresistances, and the external magnetic field value can be obtained by testing the differential voltage signal output by the two output ends of the bridge. AMR magnetoresistive sensors are well suited for sensing geomagnetism and magnetic fields in the range of tens of gauss, which can be used to detect some ferromagnetic objects such as airplanes, trains, cars, but also has applications including magnetic compasses, rotational position sensing, current sensing, drilling orientation, line position measurement, yaw rate sensors, and head trajectory tracking in virtual reality.
As shown in fig. 1, the conventional magnetoresistive sensor system is usually a single-bridge magnetoresistive sensor system, and the magnetoresistive sensor system needs two stages (SET stage and RESET stage) to complete one magnetic field value measurement when performing magnetic field measurement, and in the two stages, currents in opposite directions are applied to a flat coil located under an AMR magnetoresistive sensor, so that magnetization directions of the magnetoresistive sensor are also opposite to each other, voltage values output by the two stages are recorded, and then subtracted and divided by two to eliminate an offset error, thereby obtaining a voltage signal for representing the magnetic field value; however, the magnetoresistive sensor system takes two cycles at two stages in one magnetic field value measurement process, which results in a low data output rate.
Disclosure of Invention
According to the above problems in the prior art, a magnetoresistive sensor system is provided, in which an AMR magnetoresistive sensor is additionally provided, so that a magnetic field measurement only needs one measurement stage, the output rate of data is increased, and the sensitivity of the magnetic field measurement is improved.
The technical scheme specifically comprises the following steps:
a magnetoresistive sensor system, comprising:
the first AMR magnetoresistive sensor is arranged on the first flat coil and used for sensing a magnetic signal, and comprises a first signal output end;
the second AMR magnetoresistive sensor is arranged on the second flat coil and used for sensing a magnetic signal, and comprises a second signal output end;
the differential amplifier comprises a first input end, a second input end, a feedback end and a voltage output end, wherein the first signal output end is connected with the first input end, and the second signal output end is connected with the second input end;
and a feedback circuit is also arranged between the voltage output ends and outputs a feedback signal to the feedback end.
Preferably, wherein the feedback circuit further comprises:
the two ends of the first resistor are respectively connected with the anode of the voltage output end and the anode of the feedback end;
the two ends of the second resistor are respectively connected with the negative electrode of the voltage output end and the negative electrode of the feedback end;
and two ends of the third resistor are respectively connected with the anode of the feedback end and the cathode of the feedback end.
Preferably, wherein the first AMR magnetoresistive sensor is identical to the second AMR magnetoresistive sensor.
Preferably, the first resistor and the second resistor have the same resistance value.
Preferably, at the same time, the currents flowing in the first flat coil and the second flat coil are equal in magnitude and opposite in direction.
Preferably, wherein the differential amplifier further comprises:
the first differential transistor pair comprises a first field effect transistor and a second field effect transistor, and the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor jointly form the first input end;
the drain electrode of the first bias field effect transistor is respectively connected with the source electrode of the first field effect transistor and the source electrode of the second field effect transistor, the grid electrode of the first bias field effect transistor is connected with a bias voltage, and the source electrode of the first bias field effect transistor is grounded;
the second differential transistor pair comprises a third field effect transistor and a fourth field effect transistor, and the grid electrode of the third field effect transistor and the grid electrode of the fourth field effect transistor jointly form the second input end;
a drain electrode of the second bias field effect transistor is respectively connected with a source electrode of the third field effect transistor and a source electrode of the fourth field effect transistor, a grid electrode of the second bias field effect transistor is connected with the bias voltage, and a source electrode of the second bias field effect transistor is grounded;
the third differential transistor pair comprises a fifth field effect transistor and a sixth field effect transistor, and the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor jointly form the feedback end;
and the drain electrode of the third bias field effect transistor is respectively connected with the source electrode of the fifth field effect transistor and the source electrode of the sixth field effect transistor, the grid electrode of the third bias field effect transistor is connected with the bias voltage, and the source electrode of the third bias field effect transistor is grounded.
A source electrode of the seventh field effect transistor and a source electrode of the eighth field effect transistor are respectively connected with a fixed voltage end, and a grid electrode of the seventh field effect transistor and a grid electrode of the eighth field effect transistor are respectively connected with the bias voltage;
a source electrode of the ninth field effect transistor is simultaneously connected with a drain electrode of the seventh field effect transistor, a drain electrode of the first field effect transistor, a drain electrode of the third field effect transistor and a drain electrode of the fifth field effect transistor, a source electrode of the tenth field effect transistor is simultaneously connected with a drain electrode of the eighth field effect transistor, a drain electrode of the second field effect transistor, a drain electrode of the fourth field effect transistor and a drain electrode of the sixth field effect transistor, and a gate electrode of the ninth field effect transistor and a gate electrode of the tenth field effect transistor are respectively connected with the bias voltage;
the drain electrode of the eleventh field effect transistor is connected with the drain electrode of the ninth field effect transistor through a first connection point, the drain electrode of the twelfth field effect transistor is connected with the drain electrode of the tenth field effect transistor through a second connection point, the first connection point and the second connection point jointly form the voltage output end, and the grid electrode of the eleventh field effect transistor and the grid electrode of the twelfth field effect transistor are respectively connected with the bias voltage;
the drain electrode of the thirteenth field effect transistor is connected with the source electrode of the eleventh field effect transistor, the drain electrode of the fourteenth field effect transistor is connected with the source electrode of the twelfth field effect transistor, the source electrode of the thirteenth field effect transistor and the source electrode of the fourteenth field effect transistor are both grounded, and the grid electrode of the thirteenth field effect transistor and the grid electrode of the fourteenth field effect transistor are respectively connected with the bias voltage.
Preferably, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, and the tenth field effect transistor are PMOS transistors.
Preferably, the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor and the fourteenth field effect transistor are NMOS transistors.
Preferably, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, and the sixth field effect transistor are NMOS transistors.
Preferably, the first bias voltage fet, the second bias voltage fet, and the third bias voltage fet are NMOS transistors.
The beneficial effects of the above technical scheme are that:
the magnetic resistance sensor system is provided, only one measuring stage is needed for magnetic field measurement by additionally adding an AMR magnetic resistance sensor, the output rate of data is increased, and the sensitivity of the magnetic field measurement is improved.
Drawings
FIG. 1 is a schematic diagram of a single bridge resistance magnetoresistive sensor system;
FIG. 2 is a schematic diagram of a magnetoresistive sensor system according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of a differential amplifier according to a preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
A magnetoresistive sensor system, comprising:
the first AMR magnetoresistive sensor 1 is arranged on the first flat coil 2 and used for sensing a magnetic signal, and the first AMR magnetoresistive sensor 1 comprises a first signal output end Vo 1;
the second AMR magnetoresistive sensor 3 is arranged on the second flat coil 4 and used for sensing a magnetic signal, and the second AMR magnetoresistive sensor 3 comprises a second signal output end Vo 2;
the differential amplifier 5 comprises a first input terminal Vin1, a second input terminal Vin2, a feedback terminal Vfb and a voltage output terminal Vout, wherein the first signal output terminal Vo1 is connected to the first input terminal Vin1, and the second signal output terminal Vo2 is connected to the second input terminal Vin 2;
a feedback circuit is further disposed between the voltage output terminals Vout, and the feedback circuit outputs a feedback signal to the feedback terminal Vfb.
As a preferred embodiment, the first slab coil 2 and the second slab coil 4 are both SET/RESET coils of a magnetoresistive sensor system, and are used for performing RESET and SET operations on four magnetoresistors forming a wheatstone bridge in an AMR magnetoresistive sensor, and in a specific measurement process, the first AMR magnetoresistive sensor 1 and the second AMR magnetoresistive sensor 3 are simultaneously subjected to magnetization operations in different directions, that is, currents with equal magnitude and opposite directions are simultaneously applied to the first slab coil 2 and the second slab coil 4, and at this time, signals output by the first signal output Vo1 and the second signal output Vo2 are subtracted from each other, so that a magnetic field signal to be measured is obtained by twice; the differential amplifier 5 is configured to perform an addition/subtraction operation on the signals output by the first signal output Vo1 and the second signal output Vo2 and amplify the signals, where the signals after the operation satisfy the following formula:
Vout＝A*(Vo1-Vo2)；
wherein A is used to indicate the magnification of the signal after passing through the differential amplifier 5,the signal amplification factor is determined by the feedback circuit. Specifically, assume that the output voltage value of the first signal output Vo1 is vsetThe output voltage value of the second signal output terminal Vo2 is vrsetThen v issetAnd vrsetRespectively satisfy the following formula:
vset＝vsig+vos；vrset＝-vsig+vos；
wherein v issigFor characterizing the voltage value, v, of the magnetic field signal to be measuredosThen it is an offset error; the output voltage value of the first signal output terminal Vo1 is subtracted from the output voltage value of the second signal output terminal Vo2 to obtain twice vsig. Therefore, the offset error v can be eliminated by subtracting the output signals of the first and second signal output terminals Vo1 and Vo2 by the differential amplifier 5os(ii) a Therefore, through the technical scheme disclosed by the invention, the detection of the magnetic field signal can be completed only in one time period, namely, one time of current, so that the output rate of data is increased.
In a preferred embodiment of the present invention, the feedback circuit further comprises:
two ends of the first resistor R1 and two ends of the first resistor R1 are respectively connected with the anode of the voltage output end Vout and the anode of the feedback end Vfb;
two ends of the second resistor R2 and two ends of the second resistor R2 are respectively connected with the negative electrode of the voltage output end Vout and the negative electrode of the feedback end Vfb;
two ends of the third resistor R3 and R3 are respectively connected to the positive electrode of the feedback terminal Vfb and the negative electrode of the feedback terminal Vfb.
In a preferred embodiment of the present invention, the first AMR magnetoresistive sensor 1 is identical to the second AMR magnetoresistive sensor 3.
In the preferred embodiment of the present invention, the first resistor R1 and the second resistor R2 have the same resistance.
In the preferred embodiment of the present invention, the currents flowing in the first flat coil 2 and the second flat coil 4 are equal and opposite at the same time.
Specifically, in the above embodiment, the resistances of the first resistor R1, the second resistor R2, and the third resistor R3 and the signal amplification factor a satisfy the following formula:
wherein r is1For indicating the resistance values, R, of the first resistor R1 and the second resistor R22For representing the resistance of the third resistor R3, the magnitudes of the resistances of the first resistor R1, the second resistor R2 and the third resistor R3 determine the signal amplification magnification of the differential amplifier 5.
In the preferred embodiment of the present invention, the differential amplifier 5 further comprises:
a first differential transistor pair, which comprises a first field effect transistor M1 and a second field effect transistor M2, wherein the gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 jointly form a first input terminal Vin 1;
the drain electrode of the first bias field effect transistor Mb1 is respectively connected with the source electrode of the first field effect transistor M1 and the source electrode of the second field effect transistor M2, the grid electrode of the first bias field effect transistor Mb1 is connected with a bias voltage, and the source electrode of the first bias field effect transistor Mb1 is grounded;
a second differential transistor pair, which includes a third fet M3 and a fourth fet M4, wherein the gate of the third fet M3 and the gate of the fourth fet M4 together form a second input terminal Vin 2;
a second bias fet Mb2, a drain of the second bias fet Mb2 is connected to the source of the third fet M3 and the source of the fourth fet M4, respectively, a gate of the second bias fet Mb2 is connected to a bias voltage, and a source of the second bias fet Mb2 is grounded;
a third differential transistor pair, which includes a fifth field effect transistor M5 and a sixth field effect transistor M6, wherein a gate of the fifth field effect transistor M5 and a gate of the sixth field effect transistor M6 jointly form a feedback terminal Vfb;
the drain of the third bias fet Mb3, the drain of the third bias fet Mb3 are connected to the source of the fifth fet M5 and the source of the sixth fet M6, respectively, the gate of the third bias fet Mb3 is connected to the bias voltage, and the source of the third bias fet Mb3 is grounded.
A seventh field effect transistor M7 and an eighth field effect transistor M8, wherein the source of the seventh field effect transistor M7 and the source of the eighth field effect transistor M8 are respectively connected to a fixed voltage terminal, and the gate of the seventh field effect transistor M7 and the gate of the eighth field effect transistor M8 are respectively connected to a bias voltage;
a ninth field effect transistor M9 and a tenth field effect transistor M10, wherein the source of the ninth field effect transistor M9 is connected to the drain of the seventh field effect transistor M7, the drain of the first field effect transistor M1, the drain of the third field effect transistor M3 and the drain of the fifth field effect transistor M5, the source of the tenth field effect transistor M10 is connected to the drain of the eighth field effect transistor M8, the drain of the second field effect transistor M2, the drain of the fourth field effect transistor M4 and the drain of the sixth field effect transistor M6, and the gate of the ninth field effect transistor M9 and the gate of the tenth field effect transistor M10 are connected to bias voltages respectively;
the drain electrode of the eleventh field effect transistor M11 is connected with the drain electrode of the ninth field effect transistor M9 through a first connection point, the drain electrode of the twelfth field effect transistor M12 is connected with the drain electrode of the tenth field effect transistor M10 through a second connection point, the first connection point and the second connection point jointly form a voltage output end Vout, and the grid electrode of the eleventh field effect transistor M11 and the grid electrode of the twelfth field effect transistor M12 are respectively connected with bias voltage;
the source of the thirteenth field effect transistor M13 and the source of the fourteenth field effect transistor M14 are grounded, and the gate of the thirteenth field effect transistor M13 and the gate of the fourteenth field effect transistor M14 are respectively connected with a bias voltage.
In the preferred embodiment of the present invention, the seventh fet M7, the eighth fet M8, the ninth fet M9 and the tenth fet M10 are PMOS transistors.
In the preferred embodiment of the present invention, the eleventh fet M11, the twelfth fet M12, the thirteenth fet M13 and the fourteenth fet M14 are NMOS transistors.
In the preferred embodiment of the present invention, the first fet M1, the second fet M2, the third fet M3, the fourth fet M4, the fifth fet M5 and the sixth fet M6 are NMOS transistors.
In the preferred embodiment of the present invention, the first bias fet Mb1, the second bias fet Mb2, and the third bias fet Mb3 are NMOS transistors.
The beneficial effects of the above technical scheme are that:
the magnetic resistance sensor system is provided, only one measuring stage is needed for magnetic field measurement by additionally adding an AMR magnetic resistance sensor, the output rate of data is increased, and the sensitivity of the magnetic field measurement is improved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A magnetoresistive sensor system, comprising:
the first AMR magnetoresistive sensor is arranged on the first flat coil and used for sensing a magnetic signal, and comprises a first signal output end;
the second AMR magnetoresistive sensor is arranged on the second flat coil and used for sensing a magnetic signal, and comprises a second signal output end;
the differential amplifier comprises a first input end, a second input end, a feedback end and a voltage output end, wherein the first signal output end is connected with the first input end, and the second signal output end is connected with the second input end;
and a feedback circuit is also arranged between the voltage output ends and outputs a feedback signal to the feedback end.
2. The magnetoresistive sensor system of claim 1, wherein the feedback circuit further comprises:
the two ends of the first resistor are respectively connected with the anode of the voltage output end and the anode of the feedback end;
the two ends of the second resistor are respectively connected with the negative electrode of the voltage output end and the negative electrode of the feedback end;
and two ends of the third resistor are respectively connected with the anode of the feedback end and the cathode of the feedback end.
3. A magnetoresistive sensor system according to claim 1, wherein the first AMR magnetoresistive sensor is identical to the second AMR magnetoresistive sensor.
4. A magnetoresistive sensor system according to claim 1, wherein the first and second resistors are of equal resistance.
5. The magnetoresistive sensor system of claim 1, wherein the first plate coil and the second plate coil flow currents of equal magnitude and opposite direction at the same time.
6. The magnetoresistive sensor system of claim 1, wherein the differential amplifier further comprises:
the first differential transistor pair comprises a first field effect transistor and a second field effect transistor, and the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor jointly form the first input end;
the drain electrode of the first bias field effect transistor is respectively connected with the source electrode of the first field effect transistor and the source electrode of the second field effect transistor, the grid electrode of the first bias field effect transistor is connected with a bias voltage, and the source electrode of the first bias field effect transistor is grounded;
the second differential transistor pair comprises a third field effect transistor and a fourth field effect transistor, and the grid electrode of the third field effect transistor and the grid electrode of the fourth field effect transistor jointly form the second input end;
a drain electrode of the second bias field effect transistor is respectively connected with a source electrode of the third field effect transistor and a source electrode of the fourth field effect transistor, a grid electrode of the second bias field effect transistor is connected with the bias voltage, and a source electrode of the second bias field effect transistor is grounded;
the third differential transistor pair comprises a fifth field effect transistor and a sixth field effect transistor, and the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor jointly form the feedback end;
and the drain electrode of the third bias field effect transistor is respectively connected with the source electrode of the fifth field effect transistor and the source electrode of the sixth field effect transistor, the grid electrode of the third bias field effect transistor is connected with the bias voltage, and the source electrode of the third bias field effect transistor is grounded.
A source electrode of the seventh field effect transistor and a source electrode of the eighth field effect transistor are respectively connected with a fixed voltage end, and a grid electrode of the seventh field effect transistor and a grid electrode of the eighth field effect transistor are respectively connected with the bias voltage;
a source electrode of the ninth field effect transistor is simultaneously connected with a drain electrode of the seventh field effect transistor, a drain electrode of the first field effect transistor, a drain electrode of the third field effect transistor and a drain electrode of the fifth field effect transistor, a source electrode of the tenth field effect transistor is simultaneously connected with a drain electrode of the eighth field effect transistor, a drain electrode of the second field effect transistor, a drain electrode of the fourth field effect transistor and a drain electrode of the sixth field effect transistor, and a gate electrode of the ninth field effect transistor and a gate electrode of the tenth field effect transistor are respectively connected with the bias voltage;
the drain electrode of the eleventh field effect transistor is connected with the drain electrode of the ninth field effect transistor through a first connection point, the drain electrode of the twelfth field effect transistor is connected with the drain electrode of the tenth field effect transistor through a second connection point, the first connection point and the second connection point jointly form the voltage output end, and the grid electrode of the eleventh field effect transistor and the grid electrode of the twelfth field effect transistor are respectively connected with the bias voltage;
the drain electrode of the thirteenth field effect transistor is connected with the source electrode of the eleventh field effect transistor, the drain electrode of the fourteenth field effect transistor is connected with the source electrode of the twelfth field effect transistor, the source electrode of the thirteenth field effect transistor and the source electrode of the fourteenth field effect transistor are both grounded, and the grid electrode of the thirteenth field effect transistor and the grid electrode of the fourteenth field effect transistor are respectively connected with the bias voltage.
7. The magnetoresistive sensor system of claim 6, wherein the seventh fet, the eighth fet, the ninth fet, and the tenth fet are PMOS transistors.
8. The magnetoresistive sensor system of claim 7, wherein the eleventh fet, the twelfth fet, the thirteenth fet, and the fourteenth fet are NMOS transistors.
9. The magnetoresistive sensor system of claim 6, wherein the first, second, third, fourth, fifth, and sixth field effect transistors are NMOS transistors.
10. The magnetoresistive sensor system of claim 6, wherein the first bias fet, the second bias fet, and the third bias fet are NMOS transistors.
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