CN111615745A - Method for producing bonded body, temporary fixing member, and laminate - Google Patents

Method for producing bonded body, temporary fixing member, and laminate Download PDF

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Publication number
CN111615745A
CN111615745A CN201980008551.3A CN201980008551A CN111615745A CN 111615745 A CN111615745 A CN 111615745A CN 201980008551 A CN201980008551 A CN 201980008551A CN 111615745 A CN111615745 A CN 111615745A
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CN
China
Prior art keywords
semiconductor element
temporary fixing
fixing member
anisotropic conductive
semiconductor
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Pending
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CN201980008551.3A
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Chinese (zh)
Inventor
斋江俊之
山下广祐
堀田吉则
殿原浩二
黑冈俊次
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Fujifilm Corp
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Fujifilm Corp
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Publication of CN111615745A publication Critical patent/CN111615745A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R11/00—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts
    • H01R11/01—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts characterised by the form or arrangement of the conductive interconnection between the connecting locations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H01L2224/06517—Bonding areas having different functions including bonding areas providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0951—Function
    • H01L2224/09515—Bonding areas having different functions
    • H01L2224/09517—Bonding areas having different functions including bonding areas providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80004—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence

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  • Wire Bonding (AREA)

Abstract

The invention provides a method for manufacturing a bonded body, a temporary fixing member for manufacturing the bonded body and a laminated body, wherein the method can inhibit the position deviation of conductive members and inhibit the bonding obstruction of the conductive members. The method for manufacturing a bonded body includes: a temporary fixing step of temporarily fixing at least two conductive members to each other by providing a temporary fixing member between the at least two conductive members having conductivity; a removing step of removing the temporary fixing member; and a bonding step of bonding at least two conductive members. The temporary fixing member is used in a method for manufacturing a joined body. The laminate is a laminate in which at least two conductive members having conductivity are laminated with a temporary fixing member interposed therebetween.

Description

Method for producing bonded body, temporary fixing member, and laminate
Technical Field
The present invention relates to a method for manufacturing a joined body in which at least two conductive members are joined as a connection target, a temporary fixing member for manufacturing the joined body, and a laminate in which at least two conductive members are laminated, and particularly relates to a method for manufacturing a joined body, a temporary fixing member, and a laminate.
Background
A structure in which a plurality of through holes provided in an insulating base material are filled with a conductive material such as a metal is one of fields that have recently attracted attention also in nanotechnology, and is expected to be used as an anisotropic conductive member, for example.
Anisotropic conductive members are widely used as electrical connection members for electronic components such as semiconductor elements, inspection connectors for performing functional inspection, and the like, because they are inserted between electronic components such as semiconductor elements and circuit boards, and electrical connection between the electronic components and the circuit boards can be obtained only by applying pressure.
In particular, electronic components such as semiconductor elements have been significantly miniaturized. Conventional methods of directly connecting wiring boards such as wire bonding, flip chip bonding, thermocompression bonding, and the like cannot sufficiently ensure electrical connection of electronic components, and therefore, have attracted attention as anisotropic conductive members for electrical connection members.
For example, patent document 1 describes an anisotropic conductive member including: a plurality of conductive paths which penetrate along the thickness direction of the insulating base material, are arranged in an insulated state and are composed of conductive components; and an adhesive layer provided on the surface of the insulating substrate, wherein each of the conductive paths has a protruding portion protruding from the surface of the insulating substrate, and an end portion of the protruding portion of each of the conductive paths is exposed or protrudes from the surface of the adhesive layer. In patent document 1, it is also possible to apply an adhesive layer provided on the surface of an insulating base material of an anisotropic conductive member to temporarily fix the anisotropic conductive member to a wafer, and then to thermally press-bond the anisotropic conductive member using a wafer bonder to perform primary bonding.
Prior art documents
Patent document
Patent document 1: international publication No. 2016/006660
As described above, in patent document 1, when the adhesive layer provided on the surface of the insulating base material of the anisotropic conductive member is applied to temporarily fix the anisotropic conductive member on the wafer and then the main bonding is performed, there is room for improvement in bonding the anisotropic conductive member. For example, if the adhesive layer remains between the electrode to be connected and the anisotropic conductive member, the bonding between the metals is inhibited, and the resistance increases. As described above, the residue of the adhesive layer for temporary fixation becomes a cause of an increase in conductive resistance.
When an adhesive layer is present during bonding, the adhesive layer flows depending on the bonding conditions of the main bonding, and the temporarily fixed state may be deviated and the position may be deviated.
Disclosure of Invention
Technical problem to be solved by the invention
The purpose of the present invention is to provide a method for manufacturing a joined body, a temporary fixing member for manufacturing the joined body, and a laminate body, wherein the positional deviation of conductive members is suppressed, and the inhibition of joining of the conductive members is suppressed.
Means for solving the technical problem
In order to achieve the above object, the present invention provides a method for manufacturing a joined body, comprising: a temporary fixing step of temporarily fixing at least two conductive members to each other by providing a temporary fixing member between the at least two conductive members having conductivity; a removing step of removing the temporary fixing member; and a bonding step of bonding at least two conductive members.
Preferably, the removing step and the bonding step are performed simultaneously.
Preferably, the removing step includes at least one of a step of vaporizing the temporary fixing member and a step of replacing the temporary fixing member with a gas or a filler.
The temporary fixing member is preferably liquid at a temperature of 23 ℃, and more preferably the boiling point of the liquid is 50 ℃ or higher and 250 ℃ or lower.
The conductive member is preferably a member having an electrode or an anisotropic conductive member.
The invention provides a temporary fixing member used for a method for manufacturing a joined body.
The present invention provides a laminate in which the temporary fixing member of the present invention is provided between at least two conductive members having conductivity and laminated.
Effects of the invention
According to the present invention, a method of manufacturing a joined body, a temporary fixing member for manufacturing the joined body, and a laminated body can be obtained, in which positional displacement between conductive members is suppressed and inhibition of joining between the conductive members is suppressed.
Drawings
Fig. 1 is a schematic view of a first example of a multilayer device showing an example of a bonded body according to an embodiment of the present invention.
Fig. 2 is a schematic view of a second example of a multilayer device showing an example of a bonded body according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view showing an example of a structure of a terminal of a semiconductor element of a stacked device that is an example of a joined body according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view showing a step of example 1 of the method for manufacturing a laminated device, which is an example of a joined body according to the embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view showing a step of example 1 of the method for manufacturing a laminated device, which is an example of a joined body according to the embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view showing a step of example 1 of the method for manufacturing a laminated device, which is an example of a joined body according to the embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view showing another example of the structure of a terminal of a semiconductor element of a stacked device that is an example of a joined body according to the embodiment of the present invention.
Fig. 8 is a schematic view of example 3 of a multilayer device showing an example of a junction body according to an embodiment of the present invention.
Fig. 9 is a schematic view showing a 4 th example of a laminated device as an example of a bonded body according to the embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view showing a step of example 2 of a method for manufacturing a laminated device, which is an example of a bonded body according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view showing a step of example 2 of a method for manufacturing a laminated device, which is an example of a bonded body according to an embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view showing a step of example 2 of a method for manufacturing a laminated device, which is an example of a joined body according to an embodiment of the present invention.
Fig. 13 is an enlarged schematic cross-sectional view showing a step of example 2 of a method for manufacturing a stacked device, which is an example of a bonded body according to the embodiment of the present invention.
Fig. 14 is a schematic plan view showing an example of the anisotropic conductive member used in the joined body according to the embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view showing an example of the anisotropic conductive member used in the joined body according to the embodiment of the present invention.
Fig. 16 is a schematic perspective view showing an example of an alignment mark of a semiconductor element used in the bonded body according to the embodiment of the present invention.
Fig. 17 is a schematic view showing an example of an alignment mark of a first semiconductor wafer used in a bonded body according to the embodiment of the present invention.
Fig. 18 is a schematic view showing a step of example 3 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 19 is a schematic view showing a step of example 3 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 20 is a schematic view showing a step of example 3 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 21 is a schematic view showing a step of example 3 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 22 is a schematic view showing a step of example 4 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 23 is a schematic view showing a step of example 4 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 24 is a schematic view showing a step of example 4 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 25 is a schematic view showing a step of example 4 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 26 is a schematic perspective view showing another example of the alignment mark of the semiconductor element used in the bonded body according to the embodiment of the present invention.
Fig. 27 is a schematic view showing a step of example 5 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 28 is a schematic view showing a step of example 5 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 29 is a schematic view showing a step of example 5 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 30 is a schematic view showing a step of example 5 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 31 is a schematic diagram showing a step of the first modification 1 of example 5 of the method for manufacturing a stacked device as an example of the bonded body according to the embodiment of the present invention.
Fig. 32 is a schematic diagram showing a step of a second modification example 2 of 5 th example of a method for manufacturing a laminated device, which is an example of a bonded body according to an embodiment of the present invention.
Fig. 33 is a schematic view showing a step of the method for manufacturing a stacked device according to example 6 of the bonded body according to the embodiment of the present invention.
Fig. 34 is a schematic view showing a step of example 6 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 35 is a schematic view showing a step of example 6 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 36 is a schematic view showing a step of example 6 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 37 is a schematic diagram showing a step of the first modification 1 of example 6 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 38 is a schematic view showing a step of the 2 nd modification example of the 6 th example of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 39 is a schematic view showing a step of example 7 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 40 is a schematic view showing a step of example 7 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 41 is a schematic view showing a step of example 7 of the method for manufacturing a stacked device, which is an example of the bonded body according to the embodiment of the present invention.
Fig. 42 is a schematic view showing a step of the method for manufacturing a stacked device according to example 8 of the bonded body according to the embodiment of the present invention.
Fig. 43 is a schematic view showing a step of the method for manufacturing a stacked device according to example 8 of the bonded body according to the embodiment of the present invention.
Fig. 44 is a schematic view showing a step of the method for manufacturing a stacked device according to example 8 of the bonded body according to the embodiment of the present invention.
Fig. 45 is a graph showing example 1 of the main joining conditions of the joined body according to the embodiment of the present invention.
Fig. 46 is a graph showing example 2 of the main joining conditions of the joined body according to the embodiment of the present invention.
Fig. 47 is a graph showing example 3 of the main joining conditions of the joined body according to the embodiment of the present invention.
FIG. 48 is a graph showing example 4 of the main joining conditions of the joined body according to the embodiment of the present invention.
Fig. 49 is a diagram showing an example 5 of the main joining conditions of the joined body according to the embodiment of the present invention.
Fig. 50 is a graph showing example 6 of the main joining conditions of the joined body according to the embodiment of the present invention.
Fig. 51 is a graph showing a 7 th example of the main joining conditions of the joined body according to the embodiment of the present invention.
Fig. 52 is a schematic view showing a 5 th example of a stacked device which is an example of a joined body according to the embodiment of the present invention.
Fig. 53 is a schematic view of example 6 of a multilayer device showing an example of a junction body according to the embodiment of the present invention.
Fig. 54 is a schematic view showing a 7 th example of a stacked device which is an example of a bonded body according to the embodiment of the present invention.
Fig. 55 is a schematic view showing an 8 th example of a stacked device which is an example of a bonded body according to the embodiment of the present invention.
Fig. 56 is a schematic view showing a 9 th example of a stacked device which is an example of a joined body according to the embodiment of the present invention.
Fig. 57 is a schematic view showing a 10 th example of a stacked device which is an example of a bonded body according to the embodiment of the present invention.
Detailed Description
Hereinafter, a method for producing a joined body, a temporary fixing member, and a laminate according to the present invention will be described in detail with reference to preferred embodiments shown in the drawings.
The drawings described below are exemplary drawings for describing the present invention, and the present invention is not limited to the drawings described below.
In the following, "to" indicating a numerical range means values included on both sides. For example, 1 being the numerical value α 1 to the numerical value β 1 means that the range of 1 is a range including the numerical value α 1 and the numerical value β 1, and when represented by a mathematical symbol, α 1 ≦ β 1.
The angle such as "orthogonal" is not particularly limited, and includes an error range generally allowed in the technical field. The temperature is also within the range of an error that is generally allowed in the art. The temperature is 23 ℃ unless otherwise specified in the specification.
Also, "identical" includes the error range generally allowed in the art. Further, "all" and "entire" include error ranges that are generally allowed in the art.
(conjugant)
The joining body is a joining body in which at least two conductive members can be joined in an electrically conductive manner to each other. The joined body can be obtained by a method for producing a joined body described later.
The conductive member is a member having an electrode or an anisotropic conductive member. As the member having an electrode, for example, a semiconductor element which is a single body and exerts a specific function can be exemplified, but a member which exerts a specific function by combining a plurality of elements is also included in the member having an electrode. The member having an electrode also includes a member for transmitting an electric signal such as a wiring member.
The anisotropic conductive member will be described in detail later, but has an electrically conductive member only in a specific direction.
In the following, the bonded body will be described by taking a semiconductor element as an example of a conductive member, and a laminated device as an example of the bonded body.
The joining means a state in which objects are joined to each other so as to ensure electrical conduction therebetween. In the case of joining, the objects remain permanently joined to each other. The bonding in the above-described bonding step is also referred to as final bonding.
[ laminated device ]
Fig. 1 is a schematic view showing a 1 st example of a laminated device which is an example of a junction body according to an embodiment of the present invention, and fig. 2 is a schematic view showing a 2 nd example of a laminated device which is an example of a junction body according to an embodiment of the present invention.
The laminated device has at least two conductive members, and includes, for example, a member having an electrode, an anisotropic conductive member, or the like. The stacked device is, for example, completed by one and performs a specific function by a single body. As described above, the laminated device is a bonded body.
The stacked device 10 shown in fig. 1 is, for example, bonded by stacking the semiconductor element 12 and the semiconductor element 14 in the stacking direction Ds, and directly connects the semiconductor element 12 and the semiconductor element 14. For example, semiconductor element 12 is the same size as semiconductor element 14. The stacked semiconductor elements 12 and 14 constitute a joined body 17 in which a plurality of semiconductors are electrically connected. Both semiconductor elements 12, 14 may have the same structure or different structures.
The stacked device 10 is not limited to the embodiment shown in fig. 1, and, like the stacked device 10 shown in fig. 2, for example, the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 may be stacked and bonded in the stacking direction Ds, and the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 may be directly electrically connected. The joined body 17 is constituted by the 3 semiconductor elements 12, 14, 16. The 3 semiconductor elements 12, 14, and 16 may have the same structure or different structures.
For example, as shown in fig. 3, each of the semiconductor elements 12 and 14 has a plurality of terminals 30. Although the semiconductor element 16 is not described, the semiconductor element 16 has the same structure as the semiconductor elements 12 and 14, for example.
As shown in fig. 3, the semiconductor elements 12 and 14 include a semiconductor layer 32, a rewiring layer 34, and a passivation layer 36. The rewiring layer 34 and the passivation layer 36 are electrically insulating layers. An element region (not shown) in which a circuit or the like that performs a specific function is formed is provided on the front surface 32a of the semiconductor layer 32. The element region will be described later. The surface 32a of the semiconductor layer 32 corresponds to the surface of the semiconductor on which the terminal 30 is provided.
A rewiring layer 34 is provided on the surface 32a of the semiconductor layer 32. The rewiring layer 34 is provided with a wiring 37 electrically connected to the element region of the semiconductor layer 32. The wiring 37 is provided with a pad 38, and the wiring 37 is electrically connected to the pad 38. The wiring 37 and the pad 38 can transmit and receive signals to and from the element region, and can supply a voltage to the element region.
A passivation layer 36 is provided on the surface 34a of the rewiring layer 34. In the passivation layer 36, a terminal 30a is provided on a pad 38 provided on the wiring 37. The terminal 30a is electrically connected to the semiconductor layer 32.
Further, the rewiring layer 34 is provided with only the pads 38, although the wires 37 are not provided. The terminal 30b is provided on the pad 38 where the wiring 37 is not provided. The terminal 30b is not electrically connected to the semiconductor layer 32.
The end face 30c of the terminal 30a and the end face 30c of the terminal 30b both coincide with the surface 36a of the passivation layer 36, i.e., maintain a so-called coplanar state, and the terminal 30a and the terminal 30b do not protrude from the surface 36a of the passivation layer 36. The terminals 30a and 30b shown in fig. 3 are formed on the same plane as the surface 36a of the passivation layer 36 by, for example, polishing.
For example, when the semiconductor element 12 and the semiconductor element 14 having the structure shown in fig. 3 are bonded, as shown in fig. 6, the terminals 30a corresponding to each other are directly connected to each other, and the terminals 30b corresponding to each other are directly connected to each other. As described above, the semiconductor element 12 and the semiconductor element 14 are electrically connected to each other through the terminal 30a, and are not electrically connected but physically connected through the terminal 30 b.
[ method for manufacturing a laminated device ]
Next, a method for manufacturing the multilayer device 10 shown in fig. 1 will be described by taking the bonding of the semiconductor element 12 and the semiconductor element 14 shown in fig. 3 as an example. The method of manufacturing the laminated device 10 is an example of a method of manufacturing a bonded body.
Fig. 4 to 6 are schematic cross-sectional views showing an example 1 of a method for manufacturing a laminated device, which is an example of a bonded body according to an embodiment of the present invention, in order of steps. In fig. 4 to 6, the same components as those of the stacked device 10 and the semiconductor elements 12 and 14 shown in fig. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The method of manufacturing the stacked device 10 shown in fig. 4 to 6 relates to a Chip-on-Chip (Chip).
As shown in fig. 4, the semiconductor element 12 and the semiconductor element 14 are disposed to face the terminals 30, respectively.
For example, the positions of the terminals 30a and 30b of the semiconductor elements 12 and 14 are aligned by aligning the semiconductor elements 12 and 14 with alignment marks (not shown). In addition, aligning the above positions is also referred to as aligning.
In fig. 4, the semiconductor element 12 is located below, and therefore the temporary fixing member 13 is provided on the surface 36a of the passivation layer 36 of the semiconductor element 12.
As shown in fig. 5, in a state where semiconductor element 12 and semiconductor element 14 are aligned, semiconductor element 12 and semiconductor element 14 are brought close to each other and brought into contact with each other, and semiconductor element 12 and semiconductor element 14 are temporarily fixed to each other by temporary fixing member 13. This temporarily fixed state is a laminated body 19.
The temporary fixing by the temporary fixing member 13 utilizes the surface tension of the temporary fixing member 13. The temporary fixation maintains the aligned state, but is not a permanently fixed state. As described later, for example, a member that is liquid at a temperature of 23 ℃ is used as the temporary fixing member 13. The temporary fixing member 13 is preferably liquid because it can be easily supplied to the surface 36a of the passivation layer 36 of the semiconductor element 12, for example.
The step of providing the temporary fixing member 13 between the semiconductor element 12 and the semiconductor element 14 and temporarily fixing the semiconductor element 12 and the semiconductor element 14 to each other by the temporary fixing member 13 shown in fig. 4 corresponds to a temporary fixing step of temporarily fixing at least two conductive members to each other by providing a temporary fixing member between at least two conductive members having conductivity. The temporary fixing member 13 will be described in detail later.
Next, the temporary fixing member 13 is removed. The step of removing the temporary fixing member 13 is a removal step.
The removal process of the temporary fixing member 13 will be described in detail later.
Next, as shown in fig. 6, semiconductor element 12 and semiconductor element 14 are bonded. Thereby, the stacked device 10 shown in fig. 1 can be obtained. The step of bonding at least two conductive members such as the semiconductor element 12 and the semiconductor element 14 is referred to as a bonding step. In the joining process, at least two conductive members are joined under, for example, predetermined joining conditions.
The temporary fixing member 13 is a member that is removed after bonding, and the temporary fixing member 13 is not present between the semiconductor element 12 and the semiconductor element 14 after bonding. Therefore, the stacked device 10 shown in fig. 1 and 2 does not include the temporary fixing member 13, and the temporary fixing member 13 does not exist between the semiconductor element 12 and the semiconductor element 14. With this structure, the terminals are in direct contact with each other, and the resistance is reduced. Since the temporary fixing members 13 are used to perform bonding in the temporarily fixed state, the positional deviation between the semiconductor element 12 and the semiconductor element 14 is suppressed at the time of bonding, and the accuracy of alignment between the semiconductor element 12 and the semiconductor element 14 is improved.
The semiconductor element is not limited to the above-described terminals 30a and 30b shown in fig. 3 and the surface 36a of the passivation layer 36 being flush with each other, but may protrude from the surface 36a of the passivation layer 36 as shown in fig. 7. In this case, the protrusion amount, i.e., the depression amount of the terminal 30a and the terminal 30b of the passivation layer 36 with respect to the surface 36a is, for example, 200nm or more and 1 μm or less.
When the amount of dishing is less than 200nm, the dishing is substantially the same as the structure without the protrusion shown in fig. 3, and it is necessary to polish with high precision. On the other hand, if the amount of dishing 6 exceeds 1 μm, it is necessary to use a solder ball or the like for bonding, as in a normal structure in which a pad electrode is provided.
In the structure shown in fig. 7, the terminals 30a and 30b protrude with respect to the surface 36a of the passivation layer 36, and therefore, a resin layer 39 for protecting the terminals 30a and 30b may be provided on the surface 36a of the passivation layer 36.
The recess 6 is obtained by acquiring images of the semiconductor elements 12 and 14 including the cross sections of the terminals 30a and 30b, and acquiring the outlines of the terminals 30a and 30b by image analysis, thereby detecting the end surfaces 30c and 30c of the terminals 30a and 30 b. The amount of recess can be obtained by determining the distance from the surface 36a of the passivation layer 36 to the end face 30c of the terminal 30a and the distance from the end face 30c of the terminal 30 b.
The end face 30c of the terminal 30a and the end face 30c of the terminal 30b are both surfaces located farthest from the surface 36a of the passivation layer 36, and are generally surfaces called upper surfaces.
The semiconductor layer 32 is not particularly limited as long as it is a semiconductor, and is made of silicon or the like, but is not limited thereto, and may be silicon carbide, germanium, gallium arsenide, gallium nitride, or the like.
The rewiring layer 34 is made of an electrically insulating material, for example, polyimide.
The passivation layer 36 is also made of an electrically insulating material, for example, silicon nitride (SiN) or polyimide.
The wiring 37 and the pad 38 are made of a conductive material, for example, copper, a copper alloy, aluminum, or an aluminum alloy.
The terminals 30a and 30b are made of a conductive material, for example, a metal or an alloy, as in the case of the wiring 37 and the land 38. Specifically, the terminals 30a and 30b are made of copper, copper alloy, aluminum alloy, or the like, for example.
The terminals 30a and 30b are not limited to those made of metal or alloy as long as they have conductivity, and materials called terminals or electrode pads in the field of semiconductor devices can be appropriately used.
[ laminated device having anisotropically conductive Member ]
Next, example 2 of the stacked device will be described. In example 2 of the laminated device, the conductive member includes an anisotropic conductive member.
Fig. 8 is a schematic view showing a 2 nd example of a laminated device that is an example of a junction body according to an embodiment of the present invention, and fig. 9 is a schematic view showing a 2 nd example of a laminated device that is an example of a junction body according to an embodiment of the present invention. In fig. 8 and 9, the same components as those of the stacked device 10 and the semiconductor elements 12 and 14 shown in fig. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The stacked device 10 shown in fig. 8 is a stacked device in which, for example, a semiconductor element 12, an anisotropic conductive member 15, and a semiconductor element 14 are bonded in this order and electrically connected. The bonded body 17 is composed of the stacked semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14.
The stacked device 10 is a system in which 1 semiconductor element 14 is bonded to 1 semiconductor element 12, but is not limited to this. As in the multilayer device 10 shown in fig. 9, 3 semiconductor elements 12, 14, and 16 may be bonded to each other with an anisotropic conductive member 15 interposed therebetween. The laminated device 10 is constituted by 3 semiconductor elements 12, 14, 16 and two anisotropic conductive members 15. The semiconductor element 12, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are stacked to form a joined body 17.
[ method for producing laminated device having anisotropically conductive Member ]
Next, a method for manufacturing the laminated device 10 having the anisotropic conductive member 15 shown in fig. 8 will be described.
Fig. 10 to 12 are schematic cross-sectional views showing, in order of steps, a method for manufacturing a stacked device, which is an example of a bonded body according to an embodiment of the present invention, as an example of a method for manufacturing a stacked device. Fig. 13 is an enlarged schematic cross-sectional view showing a step of example 2 of a method for manufacturing a stacked device, which is an example of a bonded body according to an embodiment of the present invention.
In fig. 10 to 13, the same components as those of the stacked device 10 and the semiconductor elements 12 and 14 shown in fig. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The 2 nd example of the method for manufacturing the stacked device 10 shown in fig. 10 to 13 relates to a Chip-on-Chip (Chip-on-Chip).
In manufacturing the laminated device 10 having the anisotropic conductive member 15 shown in fig. 8, first, the semiconductor element 12, the semiconductor element 14, and the anisotropic conductive member 15 shown in fig. 10 are prepared. The semiconductor element 12 is an element in which a plurality of electrodes 22 are provided in a semiconductor element portion 20, for example, and the electrodes 22 are used for exchanging signals with the outside or transmitting and receiving voltages or currents. Each electrode 22 is electrically insulated by an insulating layer 24. The electrode 22 protrudes more than the surface 24a of the insulating layer 24, for example.
The structure of the semiconductor element 14 is the same as that of the semiconductor element 12. The semiconductor element 14 is an element provided with a plurality of electrodes 23 on the interposer substrate 21, for example, and the electrodes 23 are used for exchanging signals with the outside or transmitting and receiving voltage or current. Each electrode 23 is electrically insulated by an insulating layer 25. The electrode 23 protrudes more than the surface 25a of the insulating layer 25, for example. The interposer substrate 21 has, for example, a lead wiring layer, and the laminated device 10 is electrically connected to the outside through the electrodes 23.
The anisotropic conductive member 15 includes a plurality of conductive paths 42 having conductivity (see fig. 10 and 13). For example, the anisotropic conductive member 15 does not have a member having an adhesive function such as an adhesive layer. The anisotropic conductive member 15 will be described in detail later.
As shown in fig. 10, the semiconductor element 12 and the semiconductor element 14 are arranged to face the electrodes 23 and 22 with the anisotropic conductive member 15 interposed therebetween. The temporary fixing member 13 is disposed between the semiconductor element 12 and the anisotropic conductive member 15, and the temporary fixing member 13 is disposed between the anisotropic conductive member 15 and the semiconductor element 14.
At this time, alignment is performed using alignment marks (not shown) provided on the semiconductor elements 12 and 14 and the anisotropic conductive member 15, respectively.
The alignment using the alignment mark is not particularly limited as long as, for example, an image or a reflection image of the alignment mark can be acquired to obtain positional information of the alignment mark, and a known alignment method can be appropriately used.
Next, as shown in fig. 11, the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are stacked close to the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14, and temporarily fixed by the temporary fixing member 13 in a state where the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are aligned. This temporarily fixed state is a laminated body 19.
Next, the temporary fixing member 13 is removed from the temporarily fixed state shown in fig. 11. The method of removing the temporary fixing member 13 will be described later.
Next, the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded. As a result, as shown in fig. 12 and 13, the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded to each other in a state where the temporary fixing member 13 is not present, thereby obtaining the multilayer device 10.
As shown in fig. 13, in the laminated device 10 manufactured in the bonding step, no member is present between the electrode 22 and the conductive path 42 of the anisotropic conductive member 15. With this structure, the electrode 22 is in direct contact with the conductive path 42, and the resistance becomes small.
Since the semiconductor element 12 and the anisotropic conductive member 15 are bonded while being temporarily fixed by the temporary fixing member 13, the positional deviation between the semiconductor element 12 and the anisotropic conductive member 15 is suppressed during the bonding, and the accuracy of alignment between the semiconductor element 12 and the anisotropic conductive member 15 is improved.
In the semiconductor element 14 and the anisotropic conductive member 15, the electrode 22 is in direct contact with the conductive via 42 and the resistance is reduced, and the positional deviation between the semiconductor element 14 and the anisotropic conductive member 15 is suppressed at the time of bonding, as in the case of bonding the semiconductor element 12 and the anisotropic conductive member 15, so that the accuracy of alignment between the semiconductor element 12 and the anisotropic conductive member 15 is improved.
[ Anisotropic conductive Member ]
Next, the anisotropic conductive member will be described.
Fig. 14 is a schematic plan view showing an example of the anisotropic conductive member used in the joined body according to the embodiment of the present invention, and fig. 15 is a schematic cross-sectional view showing an example of the anisotropic conductive member used in the joined body according to the embodiment of the present invention.
As shown in fig. 14 and 15, the anisotropic conductive member 15 includes: an insulating base material 40 made of an inorganic material; and a plurality of conductive paths 42 that penetrate through the insulating base material 40 in the thickness direction D (see fig. 15) and are provided in an electrically insulated state from each other. The conductive path 42 is formed by filling a conductive material in a through hole 41 formed in the insulating base material 40 and extending in the thickness direction D, and has conductivity.
The term "electrically insulated from each other" means that the conductive paths present in the insulating base material have sufficiently low conductivity with each other in the insulating base material.
The conductive paths 42 of the anisotropic conductive member 15 are electrically insulated from each other, have very low conductivity in the direction x perpendicular to the thickness direction D (see fig. 15) of the insulating base material 40, and have conductivity in the thickness direction D. As described above, the anisotropic conductive member 15 is a member exhibiting anisotropic conductivity.
As shown in fig. 15, the insulating base material 40 is provided to penetrate through the conductive paths 42 in the thickness direction D while being electrically insulated from each other.
As shown in fig. 15, the conductive path 42 has a protruding portion 42a protruding in the thickness direction D from the front surface 40a of the insulating base material 40 and a protruding portion 42b protruding in the thickness direction D from the rear surface 40 b. The anisotropic conductive member 15 may further include a resin layer 43 provided on the front surface 40a and the back surface 40b of the insulating substrate 40. The resin layer 43 is preferably not in contact with the front end of the protruding portion 42a or the front end of the protruding portion 42 b.
The height Hd of the protruding portion 42a and the height Hd of the protruding portion 42b are preferably 6nm or more, and more preferably 30nm to 500 nm.
The height Hd of the protruding portion 42a is a length from the surface 40a of the insulating base material 40. The height Hd of the protruding portion 42b is a length from the rear surface 40b of the insulating base material 40.
Further, although fig. 15 shows the insulating substrate 40 having the resin layers 43 on the front surface 40a and the back surface 40b, the present invention is not limited to this, and the insulating substrate 40 may have a structure having the resin layer 43 on at least one surface thereof, or may have a structure having no resin layer 43 on both surfaces thereof. The anisotropic conductive member 15 shown in fig. 10 has no resin layer 43.
Similarly, the conductive path 42 in fig. 15 has the protruding portion 42a and the protruding portion 42b at both ends, but the present invention is not limited to this, and the conductive path may have a structure having a protruding portion on the surface of the insulating substrate 40 on at least the side having the resin layer 43.
The thickness h of the anisotropic conductive member 15 shown in fig. 15 is, for example, 30 μm or less. Further, the Total Thickness Variation (TTV) of the anisotropic conductive member 15 is preferably 10 μm or less. Further, ttv (total Thickness variation) ═ TMax-TMin。TMaxIs the maximum value of the distance (thickness) from the back surface reference in the flatness application area. T isMinIs the minimum value of the distance (thickness) from the back surface reference in the flatness application area.
Here, the thickness h of the anisotropic conductive member 15 is an average value of 10 points measured in a region corresponding to the thickness h.
A preferable measurement method of the thickness h of the anisotropic conductive member 15 is a method of obtaining the contour shape of the anisotropic conductive member 15 by observation with a field emission type scanning electron microscope at a magnification of 20 ten thousand times, and measuring 10 points in the region corresponding to the thickness h of the anisotropic conductive member 15 in the contour shape to obtain an average value of the measurement values of 10 points.
The ttv (total Thickness variation) of the anisotropic conductive member 15 is a value obtained by cutting the anisotropic conductive member 15 from a cut piece for each support 47 and observing the cross-sectional shape of the anisotropic conductive member 15.
As shown in fig. 15, the anisotropic conductive member 15 is provided on a support 47 for transportation, conveyance, transportation, storage, and the like. A release layer 44 is provided between the support 47 and the anisotropic conductive member 15. The support 47 and the anisotropic conductive member 15 are detachably bonded via the peeling layer 44. As described above, the anisotropic conductive member 15 is provided on the support 47 via the peeling layer 44 and is referred to as an anisotropic conductive material 49.
The support 47 supports the anisotropic conductive member 15 and is made of, for example, a silicon substrate. As the support 47, for example, SiC, SiN, GaN, and alumina (Al) can be used in addition to the silicon substrate2O3) Ceramic substrates, glass substrates, fiber-reinforced plastic substrates, and metal substrates. The fiber-reinforced plastic substrate also includes an FR-4(flame retardant Type 4) substrate and the like as a printed wiring board.
As the support 47, a flexible and transparent material can be used. Examples of the flexible and transparent support 47 include plastic films such as PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), PE (polyethylene), PP (polypropylene), polystyrene, polyvinyl chloride, polyvinylidene chloride, and TAC (triacetyl cellulose).
Here, the term "transparent" means that the transmittance is 80% or more based on the wavelength of light used for alignment. Therefore, the transmittance in the entire visible light region of 400 to 800nm wavelength may be low, but the transmittance in the entire visible light region of 400 to 800nm wavelength is preferably 80% or more. The transmittance was measured by a spectrophotometer.
The release layer 44 is preferably a layer in which a support layer 45 and a release agent 46 are laminated. The release agent 46 is in contact with the anisotropic conductive member 15, and the support 47 is separated from the anisotropic conductive member 15 from the release layer 44. For example, the support 47 is removed from the anisotropic conductive member 15 by heating to a predetermined temperature, whereby the adhesive force of the release agent 46 is weakened.
As the release agent 46, for example, revalph (registered trademark) manufactured by NITTO DENKO corporation and SOMATAC (registered trademark) manufactured by SOMAR corporation can be used.
The anisotropic conductive member 15 will be described in further detail below.
[ insulating base Material ]
The insulating base material is made of an inorganic material, and is not particularly limited as long as it has a resistivity (about 1014 Ω · cm) similar to that of an insulating base material constituting a conventionally known anisotropic conductive film or the like.
The term "composed of an inorganic material" is defined to distinguish the inorganic material from a polymer material constituting a resin layer described later, and is not limited to an insulating base material composed of only an inorganic material, and the inorganic material is a main component (50 mass% or more).
Examples of the insulating substrate include a metal oxide substrate, a metal nitride substrate, a glass substrate, a ceramic substrate such as silicon carbide or silicon nitride, a carbon substrate such as diamond-like carbon, a polyimide substrate, and a composite material thereof. As the insulating base material, for example, a film may be formed on an organic material having a through-hole from an inorganic material containing 50 mass% or more of a ceramic material or a carbon material.
The insulating base material is preferably a metal oxide base material, and more preferably an anodized film of a valve metal, because micropores having a desired average pore diameter are formed as through holes to facilitate formation of a conductive path described later.
Specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among these, an anodized film (substrate) of aluminum is preferable because of its good dimensional stability and relatively low cost.
The interval between the conductive paths in the insulating substrate is preferably 5nm to 800nm, more preferably 10nm to 200nm, and still more preferably 50nm to 140 nm. When the interval between the conductive paths in the insulating base material is within this range, the insulating base material functions as an insulating partition wall sufficiently.
The interval between the conductive paths is a width w between the adjacent conductive paths, and the average value of 10 points is measured for the width between the adjacent conductive paths by observing the cross section of the anisotropic conductive member at a magnification of 20 ten thousand times with an electrolytic emission scanning electron microscope.
[ conductive path ]
The plurality of conductive vias are comprised of a conductive material.
< conductive Material >
The conductive material constituting the conductive path is not particularly limited as long as it has a resistivity of 103 Ω · cm or less, and specific examples thereof include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), indium-doped tin oxide (ITO), and the like.
Among them, from the viewpoint of conductivity, copper, gold, aluminum, and nickel are preferable, and copper and gold are more preferable.
< protruding portion >
When the anisotropic conductive member and the electrode are electrically or physically bonded by a method such as pressure bonding, the aspect ratio of the protruding portion of the conductive path (the height of the protruding portion/the diameter of the protruding portion) is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and still more preferably 1 to 10, from the viewpoint of sufficiently ensuring the insulation in the surface direction when the protruding portion collapses.
From the viewpoint of following the surface shape of the semiconductor component to be connected, the height of the protruding portion of the conductive path is preferably 20nm or more, and more preferably 100nm to 500nm, as described above.
The height of the protruding portion of the conductive path is an average value of 10 points measured by observing a cross section of the anisotropic conductive member at a magnification of 2 ten thousand times by an electrolytic emission scanning electron microscope.
The diameter of the protruding portion of the conductive path is an average value of 10 points measured by observing the cross section of the anisotropic conductive member with an electrolytic emission scanning electron microscope.
< other shapes >
The conductive path is columnar, and the diameter d of the conductive path is the same as the diameter of the protruding portion, preferably more than 5nm and 10 μm or less, more preferably 20nm to 1000nm, and further preferably 100nm or less.
The conductive paths are present in a state of being electrically insulated from each other by the insulating base material, but the density thereof is preferably 2 ten thousand/mm2More preferably 200 ten thousand/mm or more2More preferably 1000 ten thousand/mm or more2More than 5000 ten thousand/mm is particularly preferable2More than, most preferably 1 hundred million/mm2The above.
The distance p between the centers of adjacent conductive paths is preferably 20nm to 500nm, more preferably 40nm to 200nm, and still more preferably 50nm to 140 nm.
[ resin layer ]
The resin layer may be provided on the front and back surfaces of the insulating base material, for example, so as to embed the conductive path. The resin layer can be the same as NCP (Non Conductive Paste) described later. The resin layer may be a member having a bonding function.
< shape >
The thickness of the resin layer is larger than the height of the protruding portion of the conductive path, and preferably 1 μm to 5 μm for the reason of protecting the conductive path.
[ other methods for manufacturing a laminated device ]
Next, a method of manufacturing a Chip-on-Wafer (Chip-on-Wafer) will be described as a method of manufacturing a stacked device.
In a method for manufacturing chips on a wafer, a semiconductor element and a semiconductor wafer are used as a conductive member. First, a semiconductor element and a semiconductor wafer will be explained.
Fig. 16 is a schematic perspective view showing an example of an alignment mark of a semiconductor element used in the bonded body according to the embodiment of the present invention.
As shown in fig. 16, alignment marks 52 are provided on the surface 14a of the semiconductor element 14, for example, at the corners of the element region 50 and the element region 50. On the surface 14a of the semiconductor element 14, 4 alignment marks 52 are provided. The surface 14a is provided with a terminal 30 shown in fig. 3. The surface 14a is opposed to a surface 60a (refer to fig. 17) of the first semiconductor wafer 60 (refer to fig. 17).
In addition, at least two alignment marks 52 may be provided. As will be described later, for example, when the anisotropic conductive member 15 is provided in the element region 50, the alignment mark 52 is preferably provided outside the element region 50 in order to easily recognize the alignment mark 52.
Fig. 17 is a schematic view showing an example of an alignment mark of a first semiconductor wafer used in a bonded body according to the embodiment of the present invention.
As shown in fig. 17, the first semiconductor wafer 60 includes a plurality of element regions 62. The four corners of the element region 62 are provided with alignment marks 64, respectively. A total of 4 alignment marks 64 are provided in the element region 62. The element region 62 is a region where the semiconductor element 14 is bonded. The element region 50 of the semiconductor element 14 is joined to the element region 62 to form the stacked device 10. The alignment mark 64 has the same structure as the alignment mark 52 described above. At least two alignment marks 64 may be provided.
Fig. 18 to 21 are schematic diagrams showing a method for manufacturing a stacked device, which is an example of a bonded body according to an embodiment of the present invention, in step order, as example No. 3. In fig. 18 to 21, the same components as those of the stacked device 10 and the semiconductor elements 12 and 14 shown in fig. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The alignment of the first semiconductor wafer 60 and the semiconductor device 14 is performed using the alignment mark 64 (refer to fig. 17) of the first semiconductor wafer 60 and the alignment mark 52 (refer to fig. 16) of the semiconductor device 14.
For alignment using the alignment marks, for example, the alignment marks 64 (see fig. 17) of the first semiconductor wafer 60 and the alignment marks 52 (see fig. 16) of the semiconductor device 14 are simultaneously captured, and based on the image of the alignment mark 64 (see fig. 17) of the first semiconductor wafer 60 and the image of the alignment mark 52 (see fig. 16) of the semiconductor device 14, the positional information of the alignment mark 64 (see fig. 17) of the first semiconductor wafer 60 and the positional information of the alignment mark 52 (see fig. 16) of the semiconductor device 14 are obtained to perform alignment.
In the alignment, the configuration is not particularly limited, and a known imaging device can be suitably used, as long as digital image data can be obtained for an image or a reflection image of the alignment mark 64 (see fig. 17) of the first semiconductor wafer 60 and an image or a reflection image of the alignment mark 52 (see fig. 16) of the semiconductor element 14.
As shown in fig. 18, after the first semiconductor wafer 60 and the semiconductor element 14 are aligned, the temporary fixing member 13 is provided between the first semiconductor wafer 60 and the semiconductor element 14, for example, on the surface 60a of the first semiconductor wafer 60.
The temporary fixing member 13 may be provided for each semiconductor element 14, but is not limited thereto, and the temporary fixing member 13 may be provided on the entire surface of the front surface 60a of the first semiconductor wafer 60, for example.
As shown in fig. 19, the semiconductor elements 14 are brought into close contact with the front surface 60a of the first semiconductor wafer 60, and all the semiconductor elements 14 are temporarily fixed by the temporary fixing member 13 in a state where the first semiconductor wafer 60 and the semiconductor elements 14 are aligned. This temporarily fixed state is a laminated body 19.
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, all the semiconductor elements 14 are bonded to the first semiconductor wafer 60 in a state of being temporarily fixed without the temporary fixing member 13, for example, under predetermined bonding conditions. As a result, the element region 50 (see fig. 16) of the semiconductor element 14 and the element region (not shown) of the first semiconductor wafer 60 are bonded to each other, and the semiconductor element 14 and the first semiconductor wafer 60 are brought into a state of ensuring electrical conduction with each other, thereby forming a bonded body 17 of the semiconductor element 14 and the first semiconductor wafer 60, as shown in fig. 20.
Next, the first semiconductor wafer 60 to which the semiconductor element 14 shown in fig. 20 is bonded is diced into individual element regions as shown in fig. 21 by, for example, dicing, laser scribing, or the like. Thus, the stacked device 10 in which the semiconductor element 12 and the semiconductor element 14 are bonded can be obtained.
The dicing is not limited to dicing, and laser scribing may be used.
In the step of bonding the semiconductor element 12 to the first semiconductor wafer 60, the plurality of semiconductor elements 14 are temporarily fixed and then all are bonded together, but the present invention is not limited thereto, and the semiconductor elements 14 may be bonded to the first semiconductor wafer 60 one by one.
The transportation, selection, etc. of the semiconductor element 14 and the first semiconductor wafer 60, and the temporary fixing and the main bonding can be realized by using a known semiconductor manufacturing apparatus.
Further, by performing the joining together as described above, the working time can be reduced, and the productivity can be improved.
The bonding method is not particularly limited to the above method, and DBI (Direct Bond interconnect) and SAB (Surface Activated Bond) can be used.
In the DBI, a silicon oxide film is laminated on the semiconductor element 14 and the first semiconductor wafer 60, and chemical mechanical polishing is performed. Then, the silicon oxide film interface is activated by plasma treatment, and the semiconductor element 14 and the first semiconductor wafer 60 are bonded to each other by being brought into contact with each other.
In the SAB, the bonding surfaces of the semiconductor device 14 and the first semiconductor wafer 60 are activated by surface treatment in vacuum. In this state, the semiconductor element 14 and the first semiconductor wafer 60 are bonded to each other by contact in a normal temperature environment. For the surface treatment, ion irradiation or neutral atom beam irradiation of an inert gas such as argon gas is used.
In the temporary fixing, only the good of the semiconductor element 14 and the good portion in the first semiconductor wafer 60 are bonded so as to inspect the first semiconductor wafer 60 and the semiconductor element 14 and separate the good and the defective in advance, whereby the manufacturing loss can be reduced. A Good semiconductor device with guaranteed quality is called KGD (Known Good Die).
The timing of providing the temporary fixing member 13 is described after the alignment of the first semiconductor wafer 60 and the semiconductor element 14, but the temporary fixing member 13 may be provided before the alignment as long as the temporary fixing member 13 does not interfere with the detection of the alignment mark. In the manufacturing method of the stacked device 10 described below, the timing of providing the temporary fixing member 13 may be before or after the alignment.
The method of providing the temporary fixing member 13 is not particularly limited as long as the temporary fixing member 13 can be provided at a predetermined position. For example, when the temporary fixing member 13 is liquid or fixed, the temporary fixing member 13 is supplied to a predetermined place in the atmospheric environment. In order to improve productivity, the temporary fixing member 13 is preferably liquid at a temperature of 23 ℃.
As described above, the stacked device 10 has a structure including 3 semiconductor elements 12, 14, and 16. In this case, the semiconductor element 14 has a structure having a terminal (not shown) and an alignment mark (not shown) on the back surface 14 b. The semiconductor element 16 bonded to the semiconductor element 14 has an element region (not shown) and an alignment mark (not shown) on the front surface 16 a.
Fig. 22 to 25 are schematic views showing a method for manufacturing a stacked device, which is an example of a bonded body according to an embodiment of the present invention, in order of steps, according to example 4. In fig. 22 to 25, the same components as those in fig. 18 to 21 are denoted by the same reference numerals, and detailed description thereof will be omitted.
As shown in fig. 19, in a state where all the semiconductor elements 14 are temporarily fixed to the element region of the first semiconductor wafer 60, the semiconductor elements 16 are aligned with respect to the semiconductor elements 14 using the alignment marks (not shown) of the back surfaces 14b of the semiconductor elements 14 and the alignment marks (not shown) of the semiconductor elements 16 as shown in fig. 22. Further, the temporary fixing member 13 is disposed between the semiconductor element 14 and the semiconductor element 16, for example, on the back surface 14b of the semiconductor element 14. The semiconductor element 16 is brought into close contact with the semiconductor element 14, and the semiconductor element 14 and the semiconductor element 16 are temporarily fixed by the temporary fixing member 13. Thus, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are temporarily fixed by the temporary fixing member 13 in a state of being aligned. The temporarily fixed state is a laminated body (not shown).
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later. The temporary fixation using the temporary fixation member 13 is not limited to the state shown in fig. 19.
For example, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are prepared, and as shown in fig. 23, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are aligned using the alignment marks. After the alignment, the temporary fixing member 13 is provided between the first semiconductor wafer 60 and the semiconductor element 14, for example, on the surface 60a of the first semiconductor wafer 60. Between the semiconductor element 14 and the semiconductor element 16, for example, a temporary fixing member 13 is provided on the back surface 14b of the semiconductor element 14.
For example, the first semiconductor wafer 60 is temporarily fixed by the temporary fixing member 13 in a state where the semiconductor element 14 and the semiconductor element 16 are brought close to and brought into contact with each other and the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are aligned.
As described above, after the temporary fixing member 13 is removed, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are bonded in an aligned and temporarily fixed state. As a result, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are electrically connected to each other, and as shown in fig. 24, a joined body 17 of the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 is formed.
Next, as shown in fig. 25, the first semiconductor wafer 60 shown in fig. 24, to which the semiconductor elements 14 and 16 are bonded, is diced into individual element regions by dicing, laser scribing, or the like, for example. Thus, the stacked device 10 in which the semiconductor element 12 and the semiconductor element 14 are bonded can be obtained. The slicing can be performed in the manner described above.
Next, a method for manufacturing the laminated device 10 using the anisotropic conductive member 15 formed by the chip on the wafer will be described.
The method of manufacturing the laminated device 10 using the anisotropic conductive member 15 uses, for example, the semiconductor element 14 shown in fig. 26.
Fig. 26 is a schematic perspective view showing another example of the alignment mark of the semiconductor element used in the bonded body according to the embodiment of the present invention.
In the semiconductor element 14 shown in fig. 26, the anisotropic conductive member 15 is provided on an element region (not shown) on the front surface 14 a. As in the semiconductor element 14 shown in fig. 16, alignment marks 52 are provided at four corners of the front surface 14a of the semiconductor element 14, and a total of 4 alignment marks 52 are provided. At least two alignment marks 52 may be provided. The surface 14a is provided with a terminal 30 shown in fig. 3.
Fig. 27 to 30 are schematic views showing a method for manufacturing a stacked device, which is an example of a bonded body according to an embodiment of the present invention, in a process sequence, as example 5. In fig. 27 to 30, the same components as those in fig. 18 to 21 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The manufacturing method of the stacked device 10 shown in fig. 18 to 21 is different from the manufacturing method of the stacked device 10 shown in fig. 18 to 21 in that the anisotropic conductive member 15 is provided in the semiconductor element 14 in example 5 of the manufacturing method of the stacked device 10 using the anisotropic conductive member 15, and the steps other than this are the same as the manufacturing method of the stacked device 10 using the anisotropic conductive member 15.
As shown in fig. 27, the temporary fixing member 13 is provided on the surface 60a of the first semiconductor wafer 60 in a state in which the semiconductor element 14 is disposed on the surface 60a of the first semiconductor wafer 60 toward the anisotropic conductive member 15 and alignment is performed using the alignment mark. The temporary fixing member 13 may be provided on the entire surface 60a of the first semiconductor wafer 60 as described above.
Next, as shown in fig. 28, the first semiconductor wafer 60 and the semiconductor element 14 provided with the anisotropic conductive member 15 are temporarily fixed by the temporary fixing member 13 in a state of being aligned. The temporarily fixed state is a laminated body (not shown).
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the first semiconductor wafer 60 and the semiconductor element 14 are bonded under predetermined bonding conditions with the anisotropic conductive member 15 interposed therebetween in a state where the temporary fixing member 13 is not present. As a result, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 are electrically connected to each other, and as shown in fig. 29, a joined body 17 of the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is formed. In this case, since the temporary fixing member 13 is not present and the joining is performed, there is no resistance reduction due to the inhibition of the electric conduction.
Next, as shown in fig. 30, the first semiconductor wafer 60 shown in fig. 29 to which the semiconductor elements 14 and the anisotropic conductive members 15 are bonded is diced into individual element regions by, for example, dicing, laser scribing, or the like. This makes it possible to obtain a multilayer device 10 in which the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded. The slicing can be performed in the manner described above.
In the step of bonding the semiconductor element 12 to the element region, the plurality of semiconductor elements 14 are temporarily fixed and then all of them are bonded together, but the present invention is not limited to this, and the semiconductor elements 14 may be bonded to the element region of the first semiconductor wafer 60 one by one. By performing the joining together as described above, the working time can be reduced and the productivity can be improved.
As shown in fig. 27, the semiconductor element 14 may not be provided with the anisotropic conductive member 15, but the temporary fixing member 13 may be provided between the first semiconductor wafer 60 and the anisotropic conductive member 15, and the semiconductor element 14 may not be provided with the anisotropic conductive member 15, instead of using the semiconductor element 14 and the first semiconductor wafer 60 provided with the anisotropic conductive member 15.
Fig. 31 is a schematic view showing a step of the 1 st modification 1 of the 5 th modification of the method for manufacturing a stacked device as an example of the bonded body according to the embodiment of the present invention, and fig. 32 is a schematic view showing a step of the 2 nd modification 2 of the 5 th modification of the method for manufacturing a stacked device as an example of the bonded body according to the embodiment of the present invention. In fig. 31 and 32, the same components as those of the temporary fixing member 13, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 shown in fig. 26 to 30 are denoted by the same reference numerals, and detailed description thereof will be omitted.
As shown in fig. 31, the semiconductor element 14 and the anisotropic conductive member 15 are provided separately. The semiconductor element 14 and the first semiconductor wafer 60 are arranged to face each other with the anisotropic conductive member 15 interposed therebetween. The temporary fixing member 13 is disposed between the semiconductor element 14 and the anisotropic conductive member 15, and the temporary fixing member 13 is disposed between the anisotropic conductive member 15 and the first semiconductor wafer 60. At this time, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 are aligned.
In this case, next, the first semiconductor wafer 60, the anisotropic conductive member 15, and the semiconductor element 14 are temporarily fixed by the temporary fixing member 13 in a state of being aligned. The temporarily fixed state is a laminated body (not shown). As described above, the temporary fixing member 13 is removed. Next, the first semiconductor wafer 60 and the semiconductor element 14 are bonded under predetermined bonding conditions with the anisotropic conductive member 15 interposed therebetween in a state where the temporary fixing member 13 is not present. As shown in fig. 29, a bonded body 17 of the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is formed. Next, as shown in fig. 30, by dicing, the laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded can be obtained.
After the semiconductor element 14 and the first semiconductor wafer 60 are arranged to face each other with the anisotropic conductive member 15 interposed therebetween and aligned, the temporary fixing member 13 is arranged between the semiconductor element 14 and the anisotropic conductive member 15, and the temporary fixing member 13 is arranged between the anisotropic conductive member 15 and the first semiconductor wafer 60. At this time, as shown in fig. 32, the temporary fixing member 13 may be provided on the entire surface of the front surface 60a of the first semiconductor wafer 60. In this case, as described above, after the temporary fixing is performed by the temporary fixing member 13 in the aligned state, the temporary fixing member 13 is removed. Next, the first semiconductor wafer 60 and the semiconductor element 14 are bonded under predetermined bonding conditions with the anisotropic conductive member 15 interposed therebetween in a state where the temporary fixing member 13 is not present. As shown in fig. 29, a bonded body 17 of the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is formed. Next, as shown in fig. 30, by dicing, the laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded can be obtained.
As described above, when the stacked device 10 having the structure of 3 semiconductor elements 12, 14, and 16 is manufactured, the semiconductor element 14 is configured to have the terminals (not shown) and the alignment marks (not shown) on the rear surface 14b as described above. The semiconductor element 16 bonded to the semiconductor element 14 has an element region (not shown) and an alignment mark (not shown) on the front surface 16 a. The semiconductor element 16 is provided with an anisotropic conductive member 15 in advance, similarly to the semiconductor element 14.
Fig. 33 to 36 are schematic views showing a method for manufacturing a multilayer device, which is an example of a bonded body according to an embodiment of the present invention, in example 6 in order of steps. In fig. 33 to 36, the same components as those in fig. 22 to 25 are denoted by the same reference numerals, and detailed description thereof will be omitted.
As shown in fig. 28, in a state where all the semiconductor elements 14 are temporarily fixed to the element region of the first semiconductor wafer 60, as shown in fig. 33, the semiconductor elements 16 are aligned with respect to the semiconductor elements 14 using the alignment marks (not shown) of the back surfaces 14b of the semiconductor elements 14 and the alignment marks (not shown) of the semiconductor elements 16. The temporary fixing member 13 is disposed on the back surface 14b of the semiconductor element 14. The semiconductor element 16 is brought into close contact with the semiconductor element 14, and the semiconductor element 14 and the semiconductor element 16 provided with the anisotropic conductive member 15 are temporarily fixed by the temporary fixing member 13. Thus, the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15, and the semiconductor element 16 provided with the anisotropic conductive member 15 are temporarily fixed by the temporary fixing member 13 in a state of being aligned. The temporarily fixed state is a laminated body (not shown).
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later. The temporary fixation using the temporary fixation member 13 is not limited to the state shown in fig. 29.
For example, the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15, and the semiconductor element 16 provided with the anisotropic conductive member 15 are prepared, and as shown in fig. 34, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are aligned using the alignment marks. After the alignment, a temporary fixing member 13 is provided, for example, on the surface 60a of the first semiconductor wafer 60 between the first semiconductor wafer 60 and the semiconductor element 14 provided with the anisotropic conductive member 15. Between the semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15, for example, the temporary fixing member 13 is provided on the back surface 14b of the semiconductor element 14.
For example, the semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15 are brought into contact with each other in close proximity to the first semiconductor wafer 60, and temporarily fixed by the temporary fixing member 13 while aligning the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15, and the semiconductor element 16 provided with the anisotropic conductive member 15.
After the temporary fixing members 13 are removed as described above, the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15, and the semiconductor element 16 provided with the anisotropic conductive member 15 are aligned and bonded in a temporarily fixed state. As a result, the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are electrically connected to each other, and as shown in fig. 35, a joined body 17 of the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 is formed.
Next, as shown in fig. 36, the first semiconductor wafer 60 shown in fig. 35, to which the semiconductor elements 14 and 16 are bonded, is diced into individual element regions by dicing, laser scribing, or the like, for example. Thus, the stacked device 10 in which the semiconductor element 12 and the semiconductor element 14 are bonded can be obtained. The slicing can be performed in the manner described above.
As shown in fig. 34, the use of the semiconductor element 14 and the first semiconductor wafer 60 provided with the anisotropic conductive member 15 is not limited to the case where the temporary fixing member 13 is provided between the anisotropic conductive member 15 and the semiconductor element 14 and the case where the temporary fixing member 13 is provided between the first semiconductor wafer 60 and the anisotropic conductive member 15, and the semiconductor element 14 may be configured without the anisotropic conductive member 15.
Fig. 37 is a schematic diagram showing a step of the 1 st modification 1 of the 6 th modification of the method for manufacturing a stacked device as an example of the bonded body according to the embodiment of the present invention, and fig. 38 is a schematic diagram showing a step of the 2 nd modification 2 of the 6 th modification of the method for manufacturing a stacked device as an example of the bonded body according to the embodiment of the present invention. In fig. 37 and 38, the same components as those of the temporary fixing member 13, the semiconductor element 14, the anisotropic conductive member 15, the semiconductor element 16, and the first semiconductor wafer 60 shown in fig. 31 to 36 are denoted by the same reference numerals, and detailed description thereof will be omitted.
As shown in fig. 37, the semiconductor element 14 and the anisotropic conductive member 15 are provided separately. The semiconductor element 14 and the first semiconductor wafer 60 are arranged to face each other with the anisotropic conductive member 15 interposed therebetween, and the anisotropic conductive member 15, the semiconductor element 14, and the semiconductor element 16 are arranged to face each other.
The temporary fixing members 13 are disposed between the semiconductor element 16 and the anisotropic conductive member 15, between the semiconductor element 14 and the anisotropic conductive member 15, and between the anisotropic conductive member 15 and the first semiconductor wafer 60, respectively. At this time, the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are aligned.
In this case, next, the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are temporarily fixed by the temporary fixing member 13 in a state of being aligned. The temporarily fixed state is a laminated body (not shown). As described above, the temporary fixing member 13 is removed. Next, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are bonded under predetermined bonding conditions with the anisotropic conductive member 15 interposed therebetween in a state where the temporary fixing member 13 is not present. As shown in fig. 35, the bonded body 17 of the semiconductor element 16, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is constituted. Next, as shown in fig. 36, by dicing, the laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are bonded can be obtained.
The semiconductor element 14 and the first semiconductor wafer 60 are arranged to face each other with the anisotropic conductive member 15 interposed therebetween, and the semiconductor element 14 and the semiconductor element 16 are arranged to face each other with the anisotropic conductive member 15 interposed therebetween and aligned. Next, the temporary fixing members 13 are disposed between the semiconductor element 16 and the anisotropic conductive member 15, between the semiconductor element 14 and the anisotropic conductive member 15, and between the anisotropic conductive member 15 and the first semiconductor wafer 60, respectively. At this time, as shown in fig. 38, the temporary fixing member 13 may be provided on the entire surface of the front surface 60a of the first semiconductor wafer 60. In this case, as described above, after the temporary fixing by the temporary fixing member 13 in the aligned state, the temporary fixing member 13 is removed. Next, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are bonded under predetermined bonding conditions with the anisotropic conductive member 15 interposed therebetween in a state where the temporary fixing member 13 is not present. As shown in fig. 35, the bonded body 17 of the semiconductor element 16, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is constituted. Next, as shown in fig. 36, by dicing, the laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are bonded can be obtained.
Next, a method of manufacturing the stacked device 10 based on a Wafer-on-Wafer (Wafer-on-Wafer) will be described.
Fig. 39 to 41 are schematic views showing a method for manufacturing a stacked device according to an example of a bonded body according to an embodiment of the present invention, in order of steps, according to example 7. In fig. 39 to 41, the same components as those in fig. 18 to 21 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The 7 th example of the method of manufacturing a stacked device is a method of manufacturing the stacked device 10 shown in fig. 1.
The method of manufacturing the stacked device 10 according to example 7 is the same as that according to example 3 of the method of manufacturing the stacked device 10 shown in fig. 18 to 21, except that the second semiconductor wafer 70 is used instead of the semiconductor element 14. Therefore, a detailed description of the manufacturing method common to example 1 of the manufacturing method of the stacked device is omitted.
First, a first semiconductor wafer 60 and a second semiconductor wafer 70 having a plurality of element regions (not shown) and alignment marks (not shown) are prepared. The device region is disposed on the surface 70a of the second semiconductor wafer 70.
Next, as shown in fig. 39, the front surface 60a of the first semiconductor wafer 60 and the front surface 70a of the second semiconductor wafer 70 are opposed to each other. Then, the alignment of the second semiconductor wafer 70 with respect to the first semiconductor wafer 60 is performed using the alignment mark of the first semiconductor wafer 60 and the alignment mark of the second semiconductor wafer 70.
Next, the temporary fixing member 13 is disposed between the first semiconductor wafer 60 and the second semiconductor wafer 70, for example, on the front surface 60a of the first semiconductor wafer 60.
Next, the first semiconductor wafer 60 and the second semiconductor wafer 70 are temporarily fixed by the temporary fixing member 13 in a state of being aligned.
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded under predetermined bonding conditions in a state where the temporary fixing member 13 is not present. Thereby, the first semiconductor wafer 60 and the second semiconductor wafer 70 are brought into a state of ensuring electrical conduction with each other, and the joined body 17 of the first semiconductor wafer 60 and the second semiconductor wafer 70 shown in fig. 40 is constituted. In this case, since the temporary fixing member 13 is not present and the joining is performed, there is no resistance reduction due to the inhibition of the electric conduction.
Next, as shown in fig. 40, the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded to each other, and then diced into individual element regions by dicing, laser scribing, or the like. As a result, as shown in fig. 41, a stacked device 10 in which the semiconductor element 12 and the semiconductor element 14 are bonded can be obtained. As described above, the stacked device 10 can also be obtained using the wafer-on-wafer. The slicing can be performed in the manner described above.
As shown in fig. 40, when a semiconductor wafer to be thinned is present in the first semiconductor wafer 60 and the second semiconductor wafer 70 in the state where the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded, the semiconductor wafer can be thinned by Chemical Mechanical Polishing (CMP) or the like.
In example 7 of the method for manufacturing a multilayer device, a two-layer structure in which semiconductor element 12 and semiconductor element 14 are stacked was described as an example, but the present invention is not limited thereto, and may be 3 or more layers. In this case, an alignment mark (not shown) and an element region (not shown) are provided on the back surface 70b of the second semiconductor wafer 70. The terminals (not shown) on the back surface 70b are electrically connected to the element regions on the front surface 70 a. By configuring the second semiconductor wafer 70 as described above, after the 3 rd semiconductor wafer (not shown) is aligned, the temporary fixing member 13 is provided between the second semiconductor wafer 70 and the 3 rd semiconductor wafer, for example, on the back surface 70b of the second semiconductor wafer 70, and is temporarily fixed using the temporary fixing member 13. Then, the 3 rd semiconductor wafer is bonded by removing the temporary fixing member 13, whereby the stacked device 10 having 3 or more layers can be obtained.
Next, a method for manufacturing the laminated device 10 having the anisotropic conductive member 15 by using a Wafer-on-Wafer (Wafer-on-Wafer) will be described.
Fig. 42 to 44 are schematic views showing an example of a method for manufacturing a laminated device, which is an example of a bonded body according to the embodiment of the present invention, in order of process steps, in fig. 8. In fig. 42 to 44, the same components as those in fig. 39 to 41 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The 8 th example of the method of manufacturing a stacked device is a method of manufacturing the stacked device 10 shown in fig. 8.
The method of manufacturing a stacked device is the same as that of example 7 except that the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded to each other with the anisotropic conductive member 15 interposed therebetween in example 8 of the method of manufacturing a stacked device, as compared with example 7 of the method of manufacturing a stacked device 10 shown in fig. 39 to 41. Therefore, a detailed description of the manufacturing method common to example 3 of the manufacturing method of the stacked device is omitted. Since the anisotropic conductive member 15 is described above, detailed description thereof is omitted.
First, as in example 7 of the method for manufacturing the multilayer device 10, a first semiconductor wafer 60 and a second semiconductor wafer 70 provided with a plurality of element regions (not shown) and alignment marks (not shown) are prepared. Although the anisotropic conductive member 15 may be provided on either the front surface 60a of the first semiconductor wafer 60 or the front surface 70a of the second semiconductor wafer 70, the anisotropic conductive member 15 is provided on the front surface 70a of the second semiconductor wafer 70 in fig. 42.
Next, as shown in fig. 42, the front surface 60a of the first semiconductor wafer 60 and the front surface 70a of the second semiconductor wafer 70 are opposed to each other. Then, the alignment of the second semiconductor wafer 70 with respect to the first semiconductor wafer 60 is performed using the alignment mark of the first semiconductor wafer 60 and the alignment mark of the second semiconductor wafer 70.
Next, the temporary fixing member 13 is disposed between the first semiconductor wafer 60 and the second semiconductor wafer 70, for example, on the front surface 60a of the first semiconductor wafer 60.
Next, the first semiconductor wafer 60 and the second semiconductor wafer 70 provided with the anisotropic conductive member 15 are temporarily fixed by the temporary fixing member 13 in a state of being aligned.
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the first semiconductor wafer 60, the anisotropic conductive member 15, and the second semiconductor wafer 70 are bonded under predetermined bonding conditions in a state where the temporary fixing member 13 is not present. Thereby, the first semiconductor wafer 60, the anisotropic conductive member 15, and the second semiconductor wafer 70 are electrically connected to each other, and the joined body 17 of the first semiconductor wafer 60, the anisotropic conductive member 15, and the second semiconductor wafer 70 shown in fig. 43 is formed. In this case, since the temporary fixing member 13 is not present and is joined, there is no resistance reduction due to the inhibition of electric conduction.
Next, as shown in fig. 44, the first semiconductor wafer 60 and the second semiconductor wafer 70 provided with the anisotropic conductive member 15 are bonded, and then diced into individual element regions by dicing, laser scribing, or the like. This makes it possible to obtain a multilayer device 10 in which the semiconductor element 12 and the semiconductor element 14 are bonded to each other with the anisotropic conductive member 15 shown in fig. 44 interposed therebetween. As described above, the stacked device 10 can also be obtained using the wafer-on-wafer. The slicing can be performed in the manner described above.
As shown in fig. 44, when a semiconductor wafer to be thinned is present in the first semiconductor wafer 60 and the second semiconductor wafer 70 in the state where the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded, the semiconductor wafer can be thinned by Chemical Mechanical Polishing (CMP) or the like.
In example 8 of the method for manufacturing a multilayer device, a two-layer structure in which semiconductor element 12 and semiconductor element 14 are stacked has been described as an example, but the present invention is not limited to this, and as described above, it is needless to say that the number of layers may be 3 or more. In this case, an alignment mark (not shown) and an element region (not shown) are provided on the back surface 70b of the second semiconductor wafer 70. The terminals (not shown) on the back surface 70b are electrically connected to the element regions on the front surface 70 a. By configuring the second semiconductor wafer 70 as described above, after the 3 rd semiconductor wafer (not shown) is aligned, the temporary fixing member 13 is provided between the second semiconductor wafer 70 and the 3 rd semiconductor wafer, for example, on the back surface 70b of the second semiconductor wafer 70, and is temporarily fixed using the temporary fixing member 13. Then, the 3 rd semiconductor wafer is bonded by removing the temporary fixing member 13, whereby the stacked device 10 having 3 or more layers can be obtained.
As described above, by temporarily fixing the temporary fixing members 13 by using the temporary fixing members 13 removed last, a bonding failure due to the temporary fixing members 13 can be prevented.
In addition, as described above, by configuring the multilayer device 10 to include the anisotropic conductive member 15, even if the semiconductor element has irregularities, the protrusions 42a and 42b can be used as buffer layers to absorb the irregularities. Since the protruding portions 42a and 42b function as buffer layers, a high surface quality is not required for the surface of the semiconductor element having the element region. Therefore, smoothing such as polishing is not required, production cost can be suppressed, and production time can be shortened.
Further, since the stacked device 10 can be manufactured using the chips on the wafer, only the good product of the semiconductor wafer is bonded to the good product portion in the semiconductor wafer, and thus the yield can be maintained and the manufacturing loss can be reduced.
Next, the semiconductor element 14 provided with the anisotropic conductive member 15 will be described.
The semiconductor element 14 provided with the anisotropic conductive member 15 can be formed using the anisotropic conductive member 15 of the anisotropic conductive material 49 shown in fig. 15 and a semiconductor wafer provided with a plurality of element regions (not shown). As described above, the element region is provided with an alignment mark (not shown) and a terminal (not shown) for alignment. In the anisotropic conductive material 49, the anisotropic conductive member 15 is formed in a pattern aligned with the element region.
First, the anisotropic conductive member 15 of the anisotropic conductive material 49 is bonded to the element region of the semiconductor wafer by applying a predetermined pressure, heating to a predetermined temperature, and holding for a predetermined time.
Next, the support 47 of the anisotropic conductive material 49 is removed, and only the anisotropic conductive member 15 is bonded to the semiconductor wafer. In this case, the anisotropic conductive material 49 is heated to a predetermined temperature, the adhesive force of the release agent 46 of the release layer 44 is reduced, and the support 47 is removed from the release layer 44 of the anisotropic conductive material 49. Next, the semiconductor wafer is diced into the element regions, thereby obtaining a plurality of semiconductor elements 14.
Although the semiconductor element 14 provided with the anisotropic conductive member 15 has been described as an example, the semiconductor element 16 provided with the anisotropic conductive member 15 and the second semiconductor wafer 70 provided with the anisotropic conductive member 15 may be provided with the anisotropic conductive member 15 in the same manner as the semiconductor element 14 provided with the anisotropic conductive member 15.
The semiconductor element 14 provided with the anisotropic conductive member 15 in advance, the first semiconductor wafer 60 provided with the anisotropic conductive member 15 in advance, and the second semiconductor wafer 70 provided with the anisotropic conductive member 15 in advance are used, but the present invention is not limited thereto, and the laminated device 10 can be manufactured by disposing the anisotropic conductive member 15 alone.
The following describes a method for producing a bonded body more specifically.
[ temporary fixing procedure ]
The temporary fixing in the temporary fixing step is to fix the joined objects in a state of being aligned with the joined objects. The temporary fixation maintains the aligned state, but is not a permanently fixed state. In the temporary fixing, at least two conductive members are temporarily fixed to each other using a temporary fixing member by using the surface tension of the temporary fixing member.
In the temporary fixing step, at least two conductive members are brought into close contact with each other to perform temporary fixing. In this case, the pressure condition of the conductive member is not particularly limited, but is preferably 10MPa or less, more preferably 5MPa or less, and particularly preferably 1 MPa.
Similarly, the temperature conditions in the temporary fixing step are not particularly limited, but are preferably 0 to 300 ℃, more preferably 10 to 200 ℃, and particularly preferably room temperature (23 ℃) to 100 ℃. In addition, when the temperature in the temporary fixing step is higher than the boiling point of the temporary fixing member, the temporary fixing step is performed while removing the temporary fixing member.
In the temporary bonding step including temporarily bonding the semiconductor elements 14, 16 and the first semiconductor wafer 60 to each other, devices of companies such as Toray Engineering co, ltd, shi uyakogyo co, ltd, SHINKAWA ltd, Yamaha Motor co, ltd, and the like can be used.
[ temporary fixing Member ]
The temporary fixing member is a member that temporarily fixes at least two conductive members to each other by using surface tension, and is finally removed. Therefore, the temporary fixing member 13 is not present in the joined body such as the laminated device 10. Since the temporary fixing member is removed last as described above, for example, when the temporary fixing member is removed after being vaporized, it is preferable that no component remains.
The temporary fixing member is preferably liquid at a temperature of 23 ℃, and in this case, the boiling point of the liquid is preferably 50 ℃ or more and 250 ℃ or less. When the temporary fixing member is a liquid or a solid, the composition is not limited to a single composition, and a mixture may be used.
The fact that the solution is a liquid at a temperature of 23 ℃ is based on physical property data.
The temporary fixing member is preferably a liquid at a temperature of 23 ℃, because the temporary fixing member can be easily supplied to a predetermined place under atmospheric pressure. However, as the means for supplying the temporary fixing member, a known means for supplying a droplet may be used, and for example, the temporary fixing member may be supplied by an ink jet method. By using multi-head ink jetting, in the case of Wafer-on-Chip, the temporary fixing member can be disposed well in the element region on the surface of the semiconductor Wafer.
When the temporary fixing member is liquid at a temperature of 23 ℃, the resistance indicating the conductivity after the bonding becomes small. On the other hand, when the temporary fixing member is solid at a temperature of 23 ℃, the resistance indicating the conductivity after the bonding becomes large.
If the boiling point of the liquid is less than 50 ℃, the temporary fixing member may be removed in a step other than the removal step. If the boiling point of the liquid exceeds 250 ℃, the temporary fixing member is removed to vaporize it, so that a high temperature is required, and the bonding step and the removal step may not be performed simultaneously by the bonding conditions. Further, if the boiling point is high, the temporary fixing member is likely to remain, and the resistance indicating the conductivity after the bonding becomes large. The temporary fixing member is preferably subjected to the joining step and the removal step at the same time, and the temperature is preferably 60 ℃ to 180 ℃ as the boiling point of the liquid in view of the electrical conductivity after joining.
Examples of the temporary fixing member include acetone (boiling point 56 ℃ C.), isopropanol (boiling point 82 ℃ C.), ethyl lactate (boiling point 154 ℃ C.), ethanol (boiling point 78 ℃ C.), water (boiling point 100 ℃ C.), propylene glycol monomethyl ether acetate (boiling point 146 ℃ C.), ethylene glycol (boiling point 197 ℃ C.), diethylene glycol monobutyl ether acetate (boiling point 245 ℃ C.), diethylene glycol dibutyl ether (boiling point 256 ℃ C.) and tert-butanol (boiling point 82 ℃ C.).
In the example of the temporary fixing member, t-butanol is solid at a temperature of 23 ℃, but otherwise, it is liquid at a temperature of 23 ℃.
In the member which is liquid at a temperature of 23 ℃, the boiling point is 250 ℃ or lower, except diethylene glycol dibutyl ether (boiling point 256 ℃). In addition, the boiling points are catalog values.
[ removal Process ]
The temporary fixing member is preferably a liquid at a temperature of 23 ℃ as described above, and the boiling point of the liquid is preferably 50 ℃ or higher and 250 ℃ or lower.
When the temporary fixing member 13 is a liquid, a method of vaporizing the temporary fixing member 13 can be used as a method of removing the temporary fixing member 13.
When the temporary fixing member is vaporized, for example, in a state where the semiconductor element 12 and the semiconductor element 14 are temporarily fixed by the temporary fixing member 13, the temporary fixing member 13 is disposed in an evaporated temperature environment or a reduced pressure environment.
When the temporary fixing member is disposed in the temperature environment of evaporation and the bonding step in the subsequent step is performed in the temperature environment of evaporation of the temporary fixing member, the temporary fixing member is removed in the course of performing the bonding step. In this case, the removing step and the bonding step are performed simultaneously.
When the temporary fixing member is disposed in a reduced pressure environment and the bonding step in the subsequent step is performed in a reduced pressure environment, the temporary fixing member is removed in the step of performing the bonding step. In this case, the removing step and the bonding step are performed simultaneously. As described above, the simultaneous execution of the removing step and the bonding step means that the removing step and the bonding step are executed in 1 step.
By performing the removal step and the bonding step simultaneously, the positional deviation can be further suppressed, and the accuracy of alignment of the conductive members, for example, the semiconductor element 12 and the semiconductor element 14 can be further improved.
Further, by performing the removing step and the bonding step at the same time, the manufacturing method and the manufacturing equipment can be simplified, and the working time can be reduced.
As a method for removing the temporary fixing member 13, in addition to this, there is a method of replacing the temporary fixing member with a gas or a filler. When the temporary fixing member is replaced with the gas, for example, the temporary fixing member 13 is disposed in a reduced pressure atmosphere and discharged in a state where the semiconductor element 12 and the semiconductor element 14 are temporarily fixed. Thereby, the temporary fixing member is replaced with the gas in the depressurized environment. If the gas in the reduced pressure environment is air, the temporary fixing member is replaced with air, and if the gas in the reduced pressure environment is an inert gas such as argon gas or nitrogen gas, the temporary fixing member is replaced with an inert gas.
When the temporary fixing member 13 is replaced with the filler, the filler is filled in place of the temporary fixing member when the temporary fixing member 13 is discharged, whereby the temporary fixing member can be replaced with the filler.
The step of removing the temporary fixing member may include at least one of a step of vaporizing the temporary fixing member, a step of replacing the temporary fixing member with a gas, and a step of replacing the temporary fixing member with a filler.
The gas for replacing the temporary fixing member 13 is, for example, air, or an inert gas such as argon or nitrogen.
The filler for replacing the temporary fixing member 13 is, for example, NCP (Non Conductive Paste) or underfill (underfill). The filler will be described in detail below.
As the filler, a filler containing a polymer material, a curing agent, and an inorganic filler can be used.
Examples of the polymer material include bisphenol a type epoxy resins, bisphenol F type epoxy resins, phenol novolac type epoxy resins, alicyclic epoxy resins, siloxane based epoxy resins, biphenyl type epoxy resins, glycidyl ester type epoxy resins, glycidyl amine type epoxy resins, hydantoin type epoxy resins, and naphthalene ring-containing epoxy resins. In the epoxy resin composition, the compounds exemplified herein may be used alone or in combination of two or more. (A) The content of the component (B) is preferably 5 to 30% by mass, and more preferably 12 to 26% by mass based on the total weight of the epoxy resin composition.
Examples of the curing agent include chain aliphatic amines, cyclic aliphatic amines, aliphatic aromatic amines, and aromatic amines. In the epoxy resin composition, the compounds exemplified herein may be used alone or in combination of two or more. (B) The amine group of component (a) is contained preferably in an amount of 0.7 to 1.5 equivalents, more preferably 0.8 to 1.2 equivalents, based on 1 equivalent of the epoxy group of component (a).
Examples of the inorganic filler include silica (silica), alumina (alumina), aluminum nitride, acidified magnesium, silicon nitride, zinc oxide, and boron nitride. Among them, silicon dioxide, aluminum oxide, and aluminum nitride are preferable. In the epoxy resin composition, the compounds exemplified herein may be used alone or in combination of two or more. (C) The content of the component (B) is preferably 40 to 85% by mass, and more preferably 60 to 80% by mass based on the total weight of the epoxy resin composition. (C) The material and content of the component(s) are adjusted to obtain a desired thermal conductivity (e.g., 0.3W/m ℃ or higher, preferably 1.0W/m ℃ or higher, and more preferably 1.5W/m ℃ or higher).
The filler may further contain an amine alkylene oxide adduct, a silane coupling agent, or the like as an additive.
<NCP>
NCP is an example of a filler that replaces the temporary fixing member 13.
The NCP preferably exhibits fluidity at a temperature in the range of 50 ℃ to 200 ℃ and cures at 200 ℃ or higher.
The composition of NCP will be described below. The NCP contains a polymer material. The NCP may also contain an antioxidant material.
< Polymer Material >)
The polymer material contained in the NCP is not particularly limited, but is preferably a thermosetting resin because a gap between conductive members such as a semiconductor element and an anisotropic conductive member can be effectively embedded and adhesion between the conductive members can be further improved.
Specific examples of the thermosetting resin include epoxy resin, phenol resin, polyimide resin, polyester resin, polyurethane resin, bismaleimide resin, melamine resin, and isocyanate resin.
Among them, polyimide resin and/or epoxy resin is preferably used for the reason that insulation reliability is further improved and chemical resistance is excellent.
< Oxidation-resistant Material >
Specific examples of the antioxidant contained in NCP include 1, 2, 3, 4-tetrazole, 5-amino-1, 2, 3, 4-tetrazole, 5-methyl-1, 2, 3, 4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1, 2, 3-triazole, 4-amino-1, 2, 3-triazole, 4, 5-diamino-1, 2, 3-triazole, 4-carboxy-1H-1, 2, 3-triazole, 4, 5-dicarboxy-1H-1, 2, 3-triazole, 1H-1, 2, 3-triazole-4-acetic acid, 4-carboxy-5-carboxymethyl-1H-1, 2, 3-triazole, 1, 2, 4-triazole, 3-amino-1, 2, 4-triazole, 3, 5-diamino-1, 2, 4-triazole, 3-carboxy-1, 2, 4-triazole, 3, 5-dicarboxyl-1, 2, 4-triazole, 1, 2, 4-triazole-3-acetic acid, 1H-benzotriazole-5-carboxylic acid, benzofuran, 2, 1, 3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole, 2-mercaptobenzoxazole, melamine and derivatives of these.
Of these, benzotriazole and its derivatives are preferred.
Examples of the benzotriazole derivative include substituted benzotriazoles having a hydroxyl group, an alkoxy group (e.g., methoxy group, ethoxy group, etc.), an amino group, a nitro group, an alkyl group (e.g., methyl group, ethyl group, butyl group, etc.), a halogen atom (e.g., fluorine, chlorine, bromine, iodine, etc.), and the like on the benzene ring of benzotriazole. Further, naphthalene triazole, naphthalene bistriazole, and similarly substituted naphthalene triazole, substituted naphthalene bistriazole, and the like can be given.
Further, as other examples of the antioxidant material contained in the NCP, a higher fatty acid copper, a phenol compound, an alkanolamine, a hydroquinone, a copper chelating agent, an organic amine, an organic ammonium salt, and the like are given as general antioxidants.
The content of the antioxidant material contained in the NCP is not particularly limited, but is preferably 0.0001 mass% or more, and more preferably 0.001 mass% or more, with respect to the total mass of the NCP, from the viewpoint of the anticorrosive effect. Further, from the reason that an appropriate resistance is obtained in the main bonding process, it is preferably 5.0 mass% or less, and more preferably 2.5 mass% or less.
< migration preventing Material >)
In NCP, it is preferable to contain a migration preventing material for the reason that the insulation reliability is further improved by trapping metal ions and halogen ions that can be contained in NCP and metal ions originating from semiconductor devices and semiconductor wafers.
As the migration preventing material, for example, an ion exchanger can be used, specifically, a mixture of a cation exchanger and an anion exchanger or only a cation exchanger can be used.
The cation exchanger and the anion exchanger can be appropriately selected from, for example, an inorganic ion exchanger and an organic ion exchanger, which will be described later.
((inorganic ion exchanger))
Examples of the inorganic ion exchanger include hydrous oxides of metals represented by hydrous zirconia.
As the kind of metal, for example, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth, and the like are known in addition to zirconium.
Wherein the zirconium is cationic Cu2+、Al3+Has exchange capability. And, iron-based is also for Ag+、Cu2+Has exchange capability.
Similarly, tin-based, titanium-based, and antimony-based cation exchangers.
On the other hand, bismuth has an ability to exchange anions for Cl.
The zirconium system exhibits anion exchange ability depending on conditions. The same applies to aluminum and tin.
Other inorganic ion exchangers known include acidic salts of polyvalent metals such as zirconium phosphate, heteropoly acid salts such as ammonium phosphomolybdate, and insoluble ferrocyanide compounds.
Some of these inorganic ion exchangers are commercially available, for example, in various grades under the product name "IXE" known as TOAGOSEI co.
In addition to synthetic products, powders of inorganic ion exchangers such as natural zeolites and montmorillonites can be used.
((organic ion exchanger))
In the organic ion exchanger, the cation exchanger may be crosslinked polystyrene having a sulfonic acid group, and may be a cation exchanger having a carboxylic acid group, a phosphonic acid group, or a phosphinic acid group.
Further, examples of the anion exchanger include crosslinked polystyrene having a quaternary ammonium group, a quaternary phosphonium group, or a tertiary phosphonium group.
The inorganic ion exchanger and the organic ion exchanger may be appropriately selected in consideration of the kind of the cation and the anion to be captured and the exchange capacity for the ion. Of course, a mixture of an inorganic ion exchanger and an organic ion exchanger may be used.
Since the manufacturing process of the electronic component includes a heating process, an inorganic ion exchanger is preferable.
In addition, the mixing ratio of the migration preventing material to the polymer material is, for example, preferably 10 mass% or less, more preferably 5 mass% or less, and still more preferably 2.5 mass% or less, from the viewpoint of mechanical strength. In addition, from the viewpoint of suppressing migration when bonding the semiconductor element or the semiconductor wafer and the anisotropic conductive member, the migration preventing material is preferably 0.01 mass% or more.
< inorganic Filler >
The NCP preferably contains an inorganic filler.
The inorganic filler is not particularly limited, and may be appropriately selected from known inorganic fillers, and examples thereof include kaolin, barium sulfate, barium titanate, silica powder, fine-powder silica, fumed silica, amorphous silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, alumina, aluminum hydroxide, mica, aluminum nitride, zirconia, yttrium oxide, silicon carbide, and silicon nitride.
In the bonding, the inorganic filler preferably has an average particle diameter larger than the interval between the conductive paths, from the viewpoint of preventing the inorganic filler from entering between the conductive paths and further improving the conduction reliability.
The average particle diameter of the inorganic filler is preferably 30nm to 10 μm, more preferably 80nm to 1 μm.
The average particle diameter is a primary particle diameter measured by a laser diffraction/scattering particle diameter measuring apparatus (NIKKISO co., ltd., Microtrac MT 3300).
< curing agent >
The NCP may also contain a curing agent.
When the curing agent is contained, it is more preferable to contain the curing agent that is liquid at ordinary temperature without using the curing agent that is solid at ordinary temperature, from the viewpoint of suppressing poor bonding with the surface shape of the anisotropic conductive member to be connected.
The phrase "solid at ordinary temperature" refers to a substance that is solid at 25 ℃, for example, a substance having a melting point higher than 25 ℃.
Specific examples of the curing agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, imidazole derivatives such as aliphatic amines and 4-methylimidazole, carboxylic acid anhydrides such as dicyanodiamide, tetramethylguanidine, thiourea-added amine and methylhexahydrophthalic anhydride, carboxylic acid hydrazide, carboxylic acid amide, polyphenol compounds, novolak resins and polythiols, and from these curing agents, a curing agent that is liquid at 25 ℃ can be suitably selected and used. One curing agent may be used alone, or two or more curing agents may be used simultaneously.
The NCP may contain various additives such as a dispersant, a buffer, and a viscosity modifier, which are generally added to a resin insulating film of a semiconductor package, within a range not to impair the characteristics thereof.
[ joining procedure ]
As described above, the joining in the joining step is also referred to as main joining. In the main bonding, the environment, heating temperature, pressure (load), and processing time during the main bonding are used as control factors, but conditions to be applied to a device such as a semiconductor element to be used can be selected.
The temperature condition in the main joining is not particularly limited, but is preferably a temperature higher than the temperature for temporary fixation, more specifically, 150 to 350 ℃, and particularly, 200 to 300 ℃.
The pressure condition in the main bonding is not particularly limited, but is preferably 30MPa or less, and more preferably 0.1 to 20 MPa.
The time for the main joining is not particularly limited, but is preferably 1 second to 60 minutes, and more preferably 5 seconds to 10 minutes.
As the device used for the primary bonding, for example, a wafer bonding device of companies such as MITSUBISHI HEA VYINDUSTRIES MACHINEs TOOL co, LTD, Bondtech co, LTD, PMT corporation, ayumindusry co, LTD, Tokyo Electron Limited (TEL), EVG, SU SS MicroTec AG (SUSS), musshino joining co, LTD, and the like can be used.
The atmosphere at the time of the main bonding may be selected from an inert atmosphere such as a nitrogen atmosphere and a reduced pressure atmosphere including a vacuum atmosphere, including an atmospheric air.
The heating temperature is not particularly limited to the above, and can be variously selected from the temperatures of 100 to 400 ℃, and the heating rate can be selected from the range of 10 ℃/min to 10 ℃/sec depending on the performance of the heating stage and the heating method. The same is true with respect to cooling. Further, the heating may be performed stepwise, or the heating temperature may be sequentially increased in several stages to perform the bonding.
The pressure (load) is not particularly limited to the above-described embodiment, and rapid pressurization or gradual pressurization can be selected according to physical properties such as strength of the joining target.
The environment, the respective holding times and the changing times of heating and pressurizing at the time of the final bonding can be appropriately set. The order can be changed as appropriate. For example, the following order can be combined: after the vacuum state, the first stage pressurization is performed, the heating is performed to increase the temperature, the second stage pressurization is performed to maintain a certain time, the cooling is performed while unloading, and the pressure is returned to the atmosphere in a stage of a certain temperature or lower.
This sequence can be replaced by various combinations, and the heating may be performed in a vacuum state after pressurization in the atmosphere, or vacuum, pressurization, and heating may be performed together. Examples of such combinations are shown in fig. 45 to 51.
In addition, when the bonding is performed, the yield of the bonding can be improved by using a mechanism for independently controlling the pressure distribution and the heating distribution in the surface.
The temporary fixation can be modified in the same manner, and for example, oxidation of the electrode surface of the semiconductor element can be suppressed by performing the temporary fixation in an inert atmosphere. In addition, the joining can be performed while applying ultrasonic waves.
Fig. 45 to 51 are diagrams showing examples 1 to 7 of the main joining conditions of the joined body according to the embodiment. Fig. 45 to 51 show the environment, heating temperature, pressure (load) and processing time during bonding, wherein symbol V denotes vacuum degree, symbol L denotes load, and symbol T denotes temperature. In fig. 45 to 51, the high degree of vacuum indicates that the pressure is low.
As for the environment, heating temperature, and load at the time of bonding, for example, as shown in fig. 45 to 47, the temperature may be increased after applying the load in a state where the pressure is reduced. As shown in fig. 48, 50, and 51, the time when the load is applied and the time when the temperature is raised may be combined. As shown in fig. 49, a load is applied after the temperature is increased. As shown in fig. 48 and 49, the time of reducing the pressure and the time of increasing the temperature may be combined.
As shown in fig. 45, 46, and 50, the temperature may be increased stepwise, or heating may be performed in two stages as shown in fig. 51. As shown in fig. 47 and 50, the load may be applied stepwise.
Further, as shown in fig. 45, 47, 49, 50 and 51, the timing of reducing the pressure may be the timing of applying the load after reducing the pressure, or as shown in fig. 46 and 48, the timing of reducing the pressure and the timing of applying the load may be combined. In this case, the pressure reduction and the joining are performed simultaneously.
(laminated device)
Hereinafter, a laminated device having an anisotropic conductive member, which is an example of a laminated device of a joined body according to an embodiment of the present invention, will be further described.
Fig. 52 is a schematic view showing a 5 th example of a laminated device that is an example of a junction body according to an embodiment of the present invention, and fig. 53 is a schematic view showing a 6 th example of a laminated device that is an example of a junction body according to an embodiment of the present invention.
The joined body constitutes the laminated device and a part of the laminated device. The semiconductor element described later is, for example, a member having a conductive region of a bonded body and bonded to an anisotropic conductive member. The conductive region corresponds to a terminal or the like responsible for the conduction of the semiconductor element.
The laminated device 10 is not limited to the above configuration, and may be configured to laminate and bond the semiconductor element 84, the semiconductor element 86, and the semiconductor element 88 in the lamination direction Ds using the interposer 87 and the anisotropic conductive member 82, and to be electrically connected, as in the laminated device 80 shown in fig. 52. The anisotropic conductive member 82 has, for example, the same structure as the anisotropic conductive member 15.
Further, like the multilayer device 80 shown in fig. 53, it can also function as an optical sensor. The stacked device 80 shown in fig. 53 is formed by stacking a semiconductor element 110 and a sensor chip 112 in a stacking direction Ds via an anisotropic conductive member 82. Further, a lens 114 is provided on the sensor chip 112.
The semiconductor element 110 is provided with a logic circuit, and the structure thereof is not particularly limited as long as the logic circuit can process a signal obtained by the sensor chip 112.
The sensor chip 112 has a photosensor that detects light. The light sensor is not particularly limited as long as it can detect light, and for example, a ccd (charge Coupled device) image sensor or a cmos (complementary metal oxide semiconductor) image sensor can be used.
The structure of the lens 114 is not particularly limited as long as it can condense light on the sensor chip 112, and, for example, a microlens can be used.
The semiconductor element 84, the semiconductor element 86, and the semiconductor element 88 have an element region (not shown). The element region includes the semiconductor elements 12, 14, and 16, the first semiconductor wafer 60, the second semiconductor wafer 70, and the 3 rd semiconductor wafer, and is a region where various element structure circuits and the like are formed, such as a capacitor, a resistor, and a coil, which function as electronic elements. The element region includes, for example, a region where a memory circuit such as a flash memory, a logic circuit such as a microprocessor and an FPGA (field-programmable gate array) are formed, and a region where a communication module such as a wireless tag and wiring are formed. In the element region, a transmission circuit or a MEMS (Micro Electro Mechanical Systems) may be formed. MEMS are for example sensors, actuators, antennas and the like. The sensor includes various sensors such as acceleration, sound, and light.
As described above, the element region is provided with the element structure circuit and the like, and the semiconductor element is provided with, for example, a rewiring layer (not shown).
In the stacked device, for example, a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit can be used. The semiconductor element may be provided with all memory circuits, or may be provided with all logic circuits. The combination of semiconductor elements in the stacked device 80 may be a combination of a sensor, an actuator, an antenna, and the like, a memory circuit, and a logic circuit, and is appropriately determined according to the application of the stacked device 80, and the like.
[ semiconductor element ]
The semiconductor element is used for the semiconductor package and the stacked device. The semiconductor element is not particularly limited, and examples thereof include, in addition to the above-described embodiments, a logic LSI (Large Scale Integration) (e.g., an ASIC (Application Specific Integrated Circuit), an FPGA (field programmable Gate Array), an ASSP (Application Specific standard product), etc.), a microprocessor (e.g., a CPU (Central Processing Unit), a GPU (Graphics Processing Unit, etc.), a Memory (e.g., a DRAM (Dynamic random access Memory), an HMC (Hybrid Memory Cube), an MRAM (magnetic RAM, magnetic Memory) and a Phase-Change RAM (Phase-Change Memory), a resistive Memory (flash Memory), a flash Memory (flash Memory), a Ferroelectric random access RAM (random access Memory), a Ferroelectric random access RAM (NAND-random access Memory), a NAND flash Memory, etc.), light emitting diodes), (e.g., Micro flash lamps for mobile terminals, vehicle-mounted, projector light sources, LCD backlights, general lighting, etc.), power/devices, analog ICs (Integrated circuits), (e.g., DC (Direct Current) -DC (Direct Current) converters, Insulated Gate Bipolar Transistors (IGBTs), etc.), MEMS (Micro fluidic Mechanical Systems, Micro electro Mechanical Systems), (e.g., acceleration sensors, pressure sensors, vibrators, gyro sensors, etc.), wireless (e.g., GPS (global positioning System, global positioning System), FM (Frequency Modulation), NFC (near field communication ), RFEM (RF Expansion Module, radio Frequency Expansion Module), c (Monolithic Microwave Integrated Circuit), WLAN (wireless local area network, etc.), discrete lighting elements, mmi (discrete lighting, backside Illumination), a connection image sensor), a camera module, a CMOS (Complementary Metal Oxide Semiconductor), a Passive device, a SAW (Surface Acoustic Wave) filter, a RF (Radio Frequency) filter, an RFIPD (Radio Frequency Integrated Passive device), a BB (Broadband), and the like.
The semiconductor element is completed by 1, for example, and is a single semiconductor element and can perform a specific function such as a circuit or a sensor.
The multilayer device is not limited to the 1-to-many mode in which a plurality of semiconductor elements are bonded to 1 semiconductor element, and may be a mode in which a plurality of semiconductor elements and a plurality of semiconductor elements are bonded to each other, that is, a plurality-to-plurality mode.
Fig. 54 is a schematic view showing a 7 th example of a laminated device that is an example of a junction body according to an embodiment of the present invention, fig. 55 is a schematic view showing an 8 th example of a laminated device that is an example of a junction body according to an embodiment of the present invention, fig. 56 is a schematic view showing a 9 th example of a laminated device that is an example of a junction body according to an embodiment of the present invention, and fig. 57 is a schematic view showing a 10 th example of a laminated device that is an example of a junction body according to an embodiment of the present invention.
As a plurality-to-plurality embodiment, as shown in fig. 54, for example, a stacked device 80a is exemplified, and the stacked device 80a is an embodiment in which a semiconductor element 86 and a semiconductor element 88 are bonded to 1 semiconductor element 84 using an anisotropic conductive member 82 and are electrically connected to each other. The semiconductor element 84 may have an interposer function.
Further, for example, a plurality of devices such as a logic chip having a logic circuit and a memory chip can be stacked on a device having an interposer function. In this case, bonding can be performed even if the electrode size differs for each device.
In the multilayer device 80b shown in fig. 55, although the electrodes 118 are not the same in size and are mixed with electrodes having different sizes, the semiconductor element 86 and the semiconductor element 88 are bonded to 1 semiconductor element 84 by using the anisotropic conductive member 82 and electrically connected to each other. Further, the semiconductor element 116 and the semiconductor element 86 are bonded and electrically connected to each other by using the anisotropic conductive member 82. Semiconductor element 117 is bonded and electrically connected across semiconductor element 86 and semiconductor element 88 using anisotropic conductive member 82.
As in the multilayer device 80c shown in fig. 56, a semiconductor element 86 and a semiconductor element 88 are bonded to 1 semiconductor element 84 by using an anisotropic conductive member 82 and electrically connected. Further, the semiconductor element 116 and the semiconductor element 117 may be bonded to the semiconductor element 86 by using the anisotropic conductive member 82, and the semiconductor element 121 and the semiconductor element 88 may be bonded and electrically connected by using the anisotropic conductive member 82.
In the case of the above-described structure, a light-Emitting element such as a VCSEL (Vertical Cavity Surface Emitting Laser) and a light-receiving element such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor are stacked on a Surface of a device including an optical waveguide, whereby the device can also correspond to a silicon photonics of a desired high frequency.
For example, as in a stacked device 80d shown in fig. 57, a semiconductor element 86 and a semiconductor element 88 are bonded and electrically connected to 1 semiconductor element 84 by using an anisotropic conductive member 82. Further, the semiconductor element 116 and the semiconductor element 117 are bonded to the semiconductor element 86 by using the anisotropic conductive member 82, and the semiconductor element 121 and the semiconductor element 88 are bonded and electrically connected by using the anisotropic conductive member 82. The semiconductor element 84 is provided with an optical waveguide 123. A light emitting element 125 is provided on the semiconductor element 88, and a light receiving element 126 is provided on the semiconductor element 86. The light Lo output from the light emitting element 125 of the semiconductor element 88 passes through the optical waveguide 123 of the semiconductor element 84 and is output to the light receiving element 126 of the semiconductor element 86 as output light Ld. This makes it possible to respond to the above-described silicon photonics.
In the anisotropic conductive member 82, a hole 122 is formed in a portion corresponding to the optical path of the light Lo and the emitted light Ld.
The present invention is basically constituted as described above. Although the method for producing the joined body, the temporary fixing member, and the laminate of the present invention have been described in detail above, the present invention is not limited to the above embodiments, and various improvements and modifications may be made without departing from the scope of the present invention.
Examples
The features of the present invention will be described in further detail below with reference to examples. The materials, reagents, amounts of substances, ratios thereof, operations and the like shown in the following examples can be appropriately modified without departing from the spirit of the present invention. Therefore, the scope of the present invention is not limited to the following examples.
In this example, an anisotropic conductive member and a semiconductor member shown below were bonded as a conductive member, and a bonded body of examples 1 to 11 and comparative examples 1 and 2 shown below was prepared, and resistance and positional deviation were evaluated. The results of the resistance and the positional deviation are shown in table 1 below.
Hereinafter, the resistance as an evaluation item will be described.
The resistance was evaluated using a conductive resistance. The conductive resistance will be explained below.
< evaluation of resistance >
The probe was brought into contact with the lead wiring pad of the daisy chain pattern portion of the interposer, and conduction evaluation was performed in the atmosphere. The resistance value was measured using a SourceMeter manufactured by KEITHLEY as a measuring device.
Based on the results of the resistance values, evaluation was performed using the evaluation criteria shown below. The evaluation results are shown in the column of the resistance in table 1 below.
"A": the resistance value is 10 times lower than the designed resistance
"B": the resistance value is more than 10 times and less than 100 times of the designed resistance
"C": the resistance value is more than 100 times and less than 1000 times of the designed resistance
"D": the resistance value is more than 1000 times of the design resistance
Hereinafter, positional deviation as an evaluation item will be described.
Regarding the positional deviation, the deviation of the alignment mark was evaluated by observation based on an IR microscope (infrared microscope).
< positional deviation >
The degree of scale mark deviation in four directions of the alignment mark, which is located at both the chip and the interposer, was evaluated using an IR microscope. Based on the results of the microscopic observation, evaluation was performed by the criteria shown below. The evaluation results are shown in the column of positional deviation in table 1 below.
"A": the position deviation is less than 5 μm
"B": the position deviation is more than 5 μm and less than 10 μm
"C": the position deviation is more than 10 μm
A Test Element Group chip (TEG) is used for a semiconductor component.
< TEG chip >
A TEG chip having Cu pads and an interposer were prepared. The inside of these includes a daisy chain pattern for measuring the conductive resistance and a comb pattern for measuring the insulation resistance. The insulating layers of these are made of SiN. As the TEG chip, a chip having a chip size of 8mm square and a ratio of an electrode area (copper pillar) to a chip area of 25% was prepared. The diameter of the electrodes was set to 5 μm, the height was set to 7 μm, and the thickness of the insulating layer present between the electrodes was set to 2 μm. The TEG chip corresponds to a semiconductor component. Since the interposer includes the extraction wiring in the periphery, a chip having a size of four sides of 10mm is prepared.
In addition, at the time of bonding, a TEG chip, an anisotropic conductive member, and an interposer were stacked in this order, and bonding was performed under a bonding condition of a die bonder (DB250, manufactured by Shibuya Kogyo co., ltd.) at a temperature of 270 ℃ for 10 minutes. At this time, alignment and bonding are performed by alignment marks formed in advance on corners of the chip so as to prevent the TEG chip from being positionally deviated from Cu pads of the interposer. In addition, as described later, temporary fixing using a temporary fixing member may be performed before the joining.
The anisotropic conductive member will be described below.
[ Anisotropic conductive Member ]
< production of aluminum substrate >
The use of a catalyst containing Si: 0.06 mass%, Fe: 0.30 mass%, Cu: 0.005 mass%, Mn: 0.001 mass%, Mg: 0.001 mass%, Zn: 0.001 mass%, Ti: 0.03 mass%, and the balance being aluminum alloy of Al and unavoidable impurities, a molten metal was prepared. Subsequently, molten metal treatment and filtration were carried out, and ingots having a thickness of 500mm and a width of 1200mm were produced by a DC (Direct Chill) casting method.
Next, the surface of the ingot was cut by a surface cutting machine at an average thickness of 10mm, and then soaked at 550 ℃ for 5 hours, and cooled to 400 ℃ to produce a rolled sheet having a thickness of 2.7mm by using a hot rolling mill.
Further, after heat treatment at 500 ℃ using a continuous annealing machine, the aluminum substrate was finished to a thickness of 1.0mm by cold rolling, thereby obtaining an aluminum substrate of JIS (Japanese Industrial Standard) 1050 material.
After the aluminum substrate was formed into a wafer shape having a diameter of 200mm (8 inches), the following treatments were performed.
< electropolishing treatment >
The above aluminum substrate was subjected to an electrolytic polishing treatment using an electrolytic polishing liquid having the following composition under conditions of a voltage of 25V, a liquid temperature of 65 ℃ and a liquid flow rate of 3.0 m/min.
The cathode was a carbon electrode, and GP0110-30R (manufactured by Takasago, Ltd.) was used as a power source. Further, the flow rate of the electrolyte was measured by using a vortex flow monitor FLM22-10PCW (manufactured by As One Corporation).
(electrolytic polishing composition)
85% by mass of phosphoric acid (Wako Pure Chemical Industries, Ltd., reagent) 660mL
160mL of pure water
150mL of sulfuric acid
Ethylene glycol 30mL
< anodic Oxidation treatment step >
Next, the anodized aluminum substrate after the electrolytic polishing treatment was subjected to an anodization treatment by a self-ordering method in the order described in Japanese patent application laid-open No. 2007-204802.
The aluminum substrate after the electrolytic polishing treatment was subjected to a pre-anodization treatment for 5 hours using an electrolytic solution of 0.50mol/L oxalic acid at a voltage of 40V, a liquid temperature of 16 ℃ and a liquid flow rate of 3.0 m/min.
Thereafter, the aluminum substrate after the pre-anodization was subjected to a stripping treatment by immersing the substrate in a mixed aqueous solution of 0.2mol/L chromic anhydride and 0.6mo ],/L phosphoric acid (liquid temperature: 50 ℃ C.) for 12 hours.
Thereafter, a re-anodization treatment was performed for 3 hours and 45 minutes using an electrolytic solution of 0.50mol/L oxalic acid under conditions of a voltage of 40V, a liquid temperature of 16 ℃ and a liquid flow rate of 3.0 m/min, thereby obtaining an anodized film having a thickness of 30 μm.
In the pre-anodizing treatment and the re-anodizing treatment, the cathodes were stainless steel electrodes, and GP0110 to 30R (manufactured by Takasago, Ltd.) was used as a power source. The cooling apparatus used NeoCool BD36 (manufactured by Yamatoscientific Co., Ltd.) and the stirring and heating apparatus used Pairsterr PS-100 (manufactured by TOKYO RIKAKIKAICO., LTD.). In addition, the flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by As One Corporation).
< Barrier layer removal step >
Next, under the same treatment liquid and treatment conditions as those of the anodic oxidation treatment, the voltage was continuously decreased from 40V to 0V at a voltage decrease rate of 0.2V/sec, and electrolytic treatment (electrolytic removal treatment) was performed.
Thereafter, an etching treatment (etching removal treatment) was performed in 5 mass% phosphoric acid at 30 ℃ for 30 minutes, so that the barrier layer present at the bottom of the micropores of the anodized film was removed, and aluminum was exposed through the micropores.
Wherein the average pore diameter of micropores present in the anodic oxide film after the barrier layer removal step is 60 nm. Further, a surface photograph (magnification: 50000 times) was taken by an FE-SEM (Field emission-Scanning Electron Microscope) and the average pore diameter was calculated as an average value of the measured 50 points.
The average thickness of the anodized film after the barrier layer removing step was 80 μm. The anodized film was cut by FIB (Focused Ion Beam) in the thickness direction, and a surface photograph (magnification: 50000 times) was taken by FE-SEM of the cross section thereof, and the average thickness was calculated as an average value of 10 points measured.
And, the density of micropores present in the anodic oxide film is about 1 hundred million/mm2. Further, the disclosure of Japanese patent application laid-open No. 2008-270158<0168>And<0169>the method described in paragraph, wherein the density of the micropores is measured and calculated.
The degree of order of micropores present in the anodized film was 92%. Further, a surface photograph was taken by FE-SEM (magnification 20000 times), and the degree of order was measured and calculated by the method described in paragraphs <0024> to <0027> of japanese patent application laid-open No. 2008-270158.
< Metal filling Process >
Next, electrolytic plating was performed using the aluminum substrate as a cathode and platinum as a cathode.
Specifically, a metal-filled microstructure filled with copper in the interior of micropores was produced by performing constant current electrolysis using a copper plating solution having the composition shown below.
Here, the plating apparatus manufactured by Yamamoto-MS co., Ltd and the power supply manufactured by HOKUTO DENKO CORPORATION (HZ-3000) were used, and after cyclic voltammetry was performed in the plating solution to check the deposition potential, the treatment was performed by constant current electrolysis under the conditions shown below.
(composition and conditions of copper plating solution)
100g/L copper sulfate
50g/L sulfuric acid
Hydrochloric acid 15g/L
Temperature 25 deg.C
Current density 10A/dm2
The surface of the anodized film after filling the micropores with the metal was observed by FE-SEM, and the pore sealing ratio (number of sealed micropores/1000) was calculated by observing the presence or absence of sealing due to the metal in 1000 micropores, and the result was 96%.
The anodized film after filling the metal in the micropores was cut in the thickness direction by FIB, and the inside of the micropores was confirmed by taking a surface photograph (magnification 50000 times) of the cross section thereof by FE-SEM, thereby confirming that the inside of the sealed micropores was completely filled with the metal.
< substrate removing step >
Next, the aluminum substrate was dissolved and removed by immersing in a 20 mass% aqueous solution of mercuric chloride (mercuric chloride) at 20 ℃ for 3 hours, thereby producing a metal-filled microstructure.
< trimming Process >
The metal-filled microstructure after the substrate removal step was immersed in an aqueous sodium hydroxide solution (concentration: 5 mass%, liquid temperature: 20 ℃), the immersion time was adjusted so that the height of the protruding portion became 500nm, and the surface of the aluminum anodic oxide film was selectively dissolved, followed by washing with water and drying, thereby producing an anisotropic conductive member in which copper pillars, which are conductive paths, were protruded.
(example 1)
In example 1, after the interposer, the anisotropic conductive member, and the TEG chip were aligned, isopropyl alcohol (boiling point 82 ℃) was placed as a temporary fixing member between the interposer and the anisotropic conductive member, and between the anisotropic conductive member and the TEG chip, and the temporary fixing was performed with isopropyl alcohol, and then, the removal and bonding of isopropyl alcohol were performed simultaneously, thereby producing a bonded body. In example 1, the temporary fixing member was replaced with gas during the bonding.
In example 1, since isopropyl alcohol was used as the temporary fixing member, and after the temporary fixing was performed at a temperature of 50 ℃ for 1 minute, the joining was performed at a temperature of 270 ℃ for 10 minutes, isopropyl alcohol having a boiling point of 82 ℃ at the time of joining was vaporized and removed.
(example 2)
Example 2 is the same as example 1 except that the removal step and the bonding step of the temporary fixing member, and the removal step of the temporary fixing member are not performed simultaneously, and the step of replacing the temporary fixing member with a gas are different from example 1.
In example 2, when the temporary fixation was performed, the temporary fixation was performed at a temperature of 150 ℃ for 1 minute, and the bonding was performed after the removal of the isopropyl alcohol by vaporization.
(example 3)
Example 3 is the same as example 1 except that the removal step and the bonding step of the temporary fixing member are not performed simultaneously, and the removal step of the temporary fixing member is a vaporization step, compared with example 1.
In example 3, when the temporary fixation was performed, the temporary fixation was performed at a temperature of 100 ℃ for 1 minute, and after the isopropyl alcohol was evaporated and removed, the filler was filled, and then the bonding was performed.
As the filler, 10g of the filler was added to a dispenser by using U8410-73CF3 (trade name) manufactured by NAMICS CORPORATION, and dispensing was performed in a Toray Engineering Co., Ltd., vacuum dispenser (model FS2500) manufactured by Ltd., which was set at a pressure of 130Pa and a temperature of 100 ℃.
(example 4)
Example 4 is the same as example 1 except that the removal step and the bonding step of the temporary fixing member, and the removal step of the temporary fixing member are not performed simultaneously as compared with example 1, and the step of replacing the temporary fixing member with the filler are not performed simultaneously.
As the filler, 10g of the filler was added to a dispenser by using U8443-14 (product number) manufactured by NAMICS CORPORATION, and dispensed by a Toray Engineering Co., Ltd., vacuum dispenser (model FS2500) manufactured by Ltd., which was set at a pressure of 130Pa and a temperature of 50 ℃.
(example 5)
Example 5 was the same as example 1 except that t-butanol (boiling point 82 ℃ C.) was used as a temporary fixing member, compared with example 1. In addition, tert-butanol is a solid at a temperature of 23 ℃.
(example 6)
Example 6 was the same as example 1 except that diethylene glycol dibutyl ether (boiling point 256 ℃) was used as a temporary fixing member, compared with example 1. Additionally, diethylene glycol dibutyl ether is a liquid at a temperature of 23 ℃.
(example 7)
Example 7 was the same as example 1 except that acetone (boiling point 56 ℃) was used as a temporary fixing member, compared with example 1. In addition, acetone is liquid at a temperature of 23 ℃.
(example 8)
Example 8 was the same as example 1 except that ethyl lactate (boiling point: 154 ℃) was used as a temporary fixing member, compared with example 1. In addition, ethyl lactate is liquid at a temperature of 23 ℃.
(example 9)
Example 9 was the same as example 1 except that propylene glycol monomethyl ether acetate (boiling point: 146 ℃) was used as a temporary fixing member, as compared with example 1. In addition, propylene glycol monomethyl ether acetate is liquid at a temperature of 23 ℃.
(example 10)
Example 10 was the same as example 1 except that ethylene glycol (boiling point 197 ℃ C.) was used as a temporary fixing member, compared with example 1. In addition, ethylene glycol is liquid at a temperature of 23 ℃.
(example 11)
Example 11 was the same as example 1 except that diethylene glycol monobutyl ether acetate (boiling point 245 ℃) was used as a temporary fixing member, compared with example 1. In addition, diethylene glycol monobutyl ether acetate is liquid at a temperature of 23 ℃.
Comparative example 1
In comparative example 1, the TEG chip, the anisotropic conductive member, and the interposer were bonded without using the temporary fixing member.
Comparative example 2
Comparative example 2 is the same as example 1 except that ncp (non Conductive paste) was used as the temporary fixing member and the temporary fixing member was not removed, although the joining was performed, as compared with example 1.
[ Table 1]
Figure BDA0002585356290000501
As shown in table 1, the results of the resistances of examples 1 to 11 were better than those of comparative examples 1 and 2. In addition, the positional deviation is small in examples 1 to 11 as compared with comparative example 1 in which the temporary fixing member is not used.
In example 1, the removal step and the bonding step of the temporary fixing member were performed simultaneously, and the electric resistance and the positional deviation were evaluated well.
In example 2, the temporary fixing member was replaced with gas, and the removal step and the bonding step of the temporary fixing member were not performed at the same time, so the evaluation of the electric resistance was lower than that in example 1.
In example 3, the temporary fixing member was removed by vaporization, and the removal step and the bonding step of the temporary fixing member were not performed at the same time, so the evaluation of the electric resistance was slightly lower than that in example 1.
In example 4, the temporary fixing member was replaced with the filler, and the removal step and the bonding step of the temporary fixing member were not performed at the same time, so the evaluation of the electric resistance was slightly lower than that in example 1.
In example 5, the temporary fixing member was solid at a temperature of 23 ℃, and therefore the evaluation of the electric resistance was low as compared with example 1.
In example 6, the temporary fixing member having a boiling point exceeding 250 ℃ was used, and therefore the evaluation of the electric resistance and the positional deviation was low as compared with example 1.
In example 7, the temporary fixing member was liquid at a temperature of 23 ℃, but the boiling point of the liquid was close to 50 ℃, and the evaluation of the electric resistance was slightly lower than that in example 1.
In examples 8 and 9, the temporary fixing member was liquid at a temperature of 23 ℃ and the boiling point of the liquid was 140 ℃ or higher and 160 ℃ or lower, and the evaluation of the electric resistance was the same as in example 1.
In examples 10 and 11, the temporary fixing member was liquid at a temperature of 23 ℃, but the boiling point of the liquid exceeded 190 ℃, and the evaluation of the electric resistance was slightly lower than that in example 1.
In examples 6, 8, and 9 to 11, the boiling point of the temporary fixing member exceeded 140 ℃, and was higher than that of the temporary fixing members in examples 1 to 5 and 7. When the boiling point of the temporary fixing member is high, the evaluation of the positional deviation is slightly low.
Description of the symbols
10-stacked device, 12, 14, 16-semiconductor element, 13-temporary fixing member, 14a, 16a, 22a, 24a, 25a, 32a, 34a, 36a, 40 a-surface, 14b, 40 b-back surface, 15-anisotropic conductive member, 17-assembly, 19-laminate, 20-semiconductor element section, 21-interposer substrate, 22, 23-electrode, 24, 25-insulating layer, 30a, 30 b-terminal, 30 c-end surface, 32-semiconductor layer, 34-rewiring layer, 36-passivation layer, 37-wiring, 38-pad, 39-resin layer, 40-insulating substrate, 41-through hole, 42-conductive path, 42a, 42 b-protrusion, 43-resin layer, 44-peeling layer, 45-support layer, 46-peeling agent, 47-support, 49-anisotropic conductive material, 50-element region, 52-alignment mark, 60-first semiconductor wafer, 60a, 70 a-surface, 62-element region, 64-alignment mark, 70-second semiconductor wafer, 70 b-back surface, 80a, 80b, 80c, 80D-stacked device, 82-anisotropic conductive member, 84, 86, 88-semiconductor element, 87-interposer, 110, 116, 117, 121-semiconductor element, 112-sensor chip, 114-lens, 118-electrode, 122-hole, 123-optical waveguide, 125-light emitting element, 126-light receiving element, D-thickness direction, ds-stacking direction, Ld-emitted light, Lo-light, h-thickness, Hd-height, distance between p-centers, t-thickness, width between w-conductors, x-direction, -dishing amount.

Claims (9)

1. A method of manufacturing a joined body, comprising:
a temporary fixing step of temporarily fixing at least two conductive members to each other by providing a temporary fixing member between the at least two conductive members;
a removing step of removing the temporary fixing member; and
and a bonding step of bonding at least two of the conductive members.
2. The junction body manufacturing method according to claim 1, wherein,
the removing step and the bonding step are performed simultaneously.
3. The junction body manufacturing method according to claim 1 or 2, wherein,
the removing step includes at least one of a step of vaporizing the temporary fixing member and a step of replacing the temporary fixing member with a gas or a filler.
4. The junction body manufacturing method according to any one of claims 1 to 3, wherein,
the temporary fixing member is liquid at a temperature of 23 ℃.
5. The junction body manufacturing method according to claim 4, wherein,
the boiling point of the liquid is 50 ℃ or higher and 250 ℃ or lower.
6. The junction body manufacturing method according to any one of claims 1 to 5, wherein,
the conductive member is a member having an electrode or an anisotropic conductive member.
7. A temporary fixing member used in the method of manufacturing a joined body according to any one of claims 1 to 6.
8. A laminate in which the temporary fixing member according to claim 7 is provided and laminated between at least two conductive members having conductivity.
9. The laminate according to claim 8, wherein,
the conductive member is a member having an electrode or an anisotropic conductive member.
CN201980008551.3A 2018-02-23 2019-02-12 Method for producing bonded body, temporary fixing member, and laminate Pending CN111615745A (en)

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