CN111613605A - 包括桥接管芯的***级封装 - Google Patents

包括桥接管芯的***级封装 Download PDF

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Publication number
CN111613605A
CN111613605A CN201911036691.XA CN201911036691A CN111613605A CN 111613605 A CN111613605 A CN 111613605A CN 201911036691 A CN201911036691 A CN 201911036691A CN 111613605 A CN111613605 A CN 111613605A
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China
Prior art keywords
semiconductor chip
package
rdl
bridge die
chip
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CN201911036691.XA
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English (en)
Inventor
成基俊
金钟薰
金载敏
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SK Hynix Inc
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SK Hynix Inc
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Publication of CN111613605A publication Critical patent/CN111613605A/zh
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Abstract

包括桥接管芯的***级封装。一种***级封装包括再分配线RDL结构、第一半导体芯片、第二半导体芯片、第二子封装、第一桥接管芯和第二桥接管芯。该RDL结构包括第一RDL图案，第一半导体芯片的第一芯片焊盘电连接至第一RDL图案。第二半导体芯片层叠在第一半导体芯片上，使得第二半导体芯片突出越过第一半导体芯片的侧表面，其中，设置在第二半导体芯片的突起上的第二芯片焊盘通过第一桥接管芯电连接到第一RDL图案。第二桥接管芯被设置为将第二子封装电连接到第一半导体芯片。

Description

包括桥接管芯的***级封装
技术领域
本公开涉及半导体封装技术，更具体地，涉及包括桥接管芯的***级封装。
背景技术
近来，大量努力集中在将多个半导体芯片集成到单个半导体封装中。即，已尝试增加封装集成密度以实现利用多功能操作高速处理大量数据的高性能半导体封装。例如，***级封装(SiP)技术可被视为实现高性能半导体封装的有吸引力的候选。包括在各个SiP中的多个半导体芯片并排设置。然而，这可导致难以减小SiP的宽度。因此，已提出将多个半导体芯片设置在SiP封装中的各种技术以减小SiP的尺寸。
发明内容
根据实施方式，一种***级封装包括第一子封装以及安装在第一子封装上的第二子封装。第一子封装包括再分配线(RDL)结构，该RDL结构具有第一RDL图案和第二RDL图案。第一子封装还包括第一半导体芯片，该第一半导体芯片设置在RDL结构上，使得第一半导体芯片的电连接到第一RDL图案的第一芯片焊盘面向RDL结构。第一子封装还包括第二半导体芯片，该第二半导体芯片层叠在第一半导体芯片上，使得第二半导体芯片突出越过第一半导体芯片的侧表面，其中，设置在第二半导体芯片的突起上的第二芯片焊盘面向RDL结构。第一子封装另外包括第一桥接管芯，该第一桥接管芯设置在RDL结构上以支撑第二半导体芯片的突起，其中，第一桥接管芯包括由第一通孔穿透的第一主体，其中，第一通孔将第二芯片焊盘电连接到第一RDL图案。第一子封装还包括第二桥接管芯，该第二桥接管芯设置在RDL结构上并且与第一半导体芯片间隔开，其中，该第二桥接管芯包括由第二通孔穿透的第二主体，其中，第二通孔将第二子封装电连接到第二RDL图案。第一子封装还包括模制层，该模制层设置在RDL结构上以覆盖第一半导体芯片和第一桥接管芯并且围绕第二半导体芯片和第二桥接管芯。
根据另一实施方式，一种***级封装包括第一子封装以及安装在第一子封装上的第二子封装。第一子封装包括再分配线(RDL)结构，该RDL结构包括第一RDL图案和第二RDL图案。第一子封装还包括第一半导体芯片，该第一半导体芯片设置在RDL结构上，使得第一半导体芯片的电连接到第一RDL图案的第一芯片焊盘面向RDL结构。第一子封装还包括第二半导体芯片，该第二半导体芯片层叠在第一半导体芯片上，使得第二半导体芯片突出越过第一半导体芯片的侧表面，其中，设置在第二半导体芯片的突起上的第二芯片焊盘面向RDL结构。第一子封装另外包括第一桥接管芯，该第一桥接管芯设置在RDL结构上以支撑第二半导体芯片的突起，其中，该第一桥接管芯包括由第一通孔穿透的第一模制材料基板，其中，第一通孔将第二芯片焊盘电连接到第一RDL图案。第一子封装还包括第二桥接管芯，该第二桥接管芯设置在RDL结构上并且与第一半导体芯片间隔开，其中，该第二桥接管芯包括由第二通孔穿透的第二模制材料基板，其中，第二通孔将第二子封装电连接到第二RDL图案。第一子封装还包括模制层，该模制层设置在RDL结构上以覆盖第一半导体芯片和第一桥接管芯并且围绕第二半导体芯片和第二桥接管芯。
附图说明
图1是示出根据实施方式的***级封装(SiP)的横截面图。
图2是示出图1的一部分(包括第一桥接管芯)的放大横截面图。
图3是示出将图2所示的半导体芯片彼此连接的电路径的立体图。
图4是示出图1的一部分(包括第二桥接管芯)的放大横截面图。
图5是示出图1的一部分(包括第一桥接管芯和第二桥接管芯)的放大横截面图。
图6是示出图5所示的第一桥接管芯和第二桥接管芯的柱状凸块的平面图。
图7是示出图1所示的半导体芯片之间的连接部分的放大横截面图。
图8是示出根据另一实施方式的SiP的横截面图。
图9是示出根据另一实施方式的SiP的横截面图。
图10是示出采用包括根据实施方式的至少一个SiP的存储卡的电子***的框图。
图11是示出包括根据实施方式的至少一个SiP的另一电子***的框图。
具体实施方式
本文所使用的术语可对应于考虑其在实施方式中的功能而选择的词语，术语的含义可被解释为根据实施方式所属领域的普通技术人员而不同。如果详细定义，则可根据定义来解释术语。除非另外定义，否则本文所使用的术语(包括技术术语和科学术语)具有实施方式所属领域的普通技术人员通常理解的相同含义。
将理解，尽管本文中可使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件相区分，而非用于仅限定元件本身或者意指特定顺序。
还将理解，当元件或层被称为在另一元件或层“上”、“上方”、“下面”、“下方”或“外侧”时，该元件或层可与另一元件或层直接接触，或者可存在中间元件或层。用于描述元件或层之间的关系的其它词语应该以类似的方式解释(例如，“在...之间”与“直接在...之间”或者“相邻”与“直接相邻”)。
诸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“顶部”、“底部”等的空间相对术语可用于描述元件和/或特征与另一元件和/或特征的关系(例如，如图中所示)。将理解，除了附图中所描绘的取向之外，空间相对术语旨在涵盖装置在使用和/或操作中的不同取向。例如，当附图中的装置翻转时，被描述为在其它元件或特征下面和/或之下的元件将被取向为在其它元件或特征上面。装置可按照其它方式取向(旋转90度或处于其它取向)并且相应地解释本文中所使用的空间相对描述符。
***级封装(SiP)可对应于半导体封装，并且半导体封装可包括诸如半导体芯片或半导体管芯的电子器件。半导体芯片或半导体管芯可通过使用划片工艺将诸如晶圆的半导体基板分离成多片来获得。半导体芯片可对应于存储器芯片、逻辑芯片、专用集成电路(ASIC)芯片、应用处理器(AP)、图形处理单元(GPU)、中央处理单元(CPU)或***芯片(SoC)。存储器芯片可包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可包括集成在半导体基板上的逻辑电路。半导体封装可用在诸如移动电话的通信***、与生物技术或保健关联的电子***或可穿戴电子***中。半导体封装可适用于物联网(IoT)。
贯穿说明书，相同的标号表示相同的元件。即使标号未参照一幅图提及或描述，该标号也可参照另一幅图提及或描述。另外，即使标号未在一幅图中示出，其也可参照另一幅图提及或描述。
图1是示出根据实施方式的***级封装(SiP)10的横截面图。
参照图1，SiP 10可被实现为具有层叠封装(PoP)形状。SiP 10可被配置为包括第一子封装SP1以及安装在第一子封装SP1上的第二子封装SP2。第一子封装SP1可包括再分配线(RDL)结构100、第一半导体芯片300、第二半导体芯片400、第一桥接管芯501、第二桥接管芯505和模制层700。
RDL结构100可对应于电连接到第一半导体芯片300和第二半导体芯片400的互连结构。在另一实施方式中，印刷电路板(PCB)可用作互连结构。
第一半导体芯片300可设置在RDL结构100上。第二半导体芯片400可层叠在第一半导体芯片300的与RDL结构100相对的表面上以与第一半导体芯片300交叠。第二半导体芯片400可层叠在第一半导体芯片300上以具有突起435，突起435对应于从与第一半导体芯片300的侧表面对准的垂直线横向突出的伸出物(overhang)。第一桥接管芯501可设置在RDL结构100上以支撑第二半导体芯片400的突起435。第一桥接管芯501可设置在第二半导体芯片400的突起435与RDL结构100之间，并且可被设置为在与突起435相同的方向上与第一半导体芯片300横向间隔开。
模制层700可设置在RDL结构100上。模制层700可形成为覆盖第一半导体芯片300和第一桥接管芯501。模制层700可延伸以覆盖第二半导体芯片400。模制层700可形成为围绕并保护第二半导体芯片400并露出第二半导体芯片400的与第一半导体芯片300相对的第二表面402。在模制层700形成为露出第二半导体芯片400的第二表面402的情况下，来自第二半导体芯片400和第一半导体芯片300的由于SiP 10的操作而生成的热可通过第二半导体芯片400的第二表面402更容易地消散到外部空间。模制层700可被设置为围绕并保护第二桥接管芯505。模制层700可由各种模制材料或包封材料中的任一种形成。例如，模制层700可由环氧模制料(EMC)材料形成。
图2是示出图1的一部分(包括第一桥接管芯501)的放大横截面图。
参照图1和图2，RDL结构100可包括第一RDL图案120。各个第一RDL图案120可被设置为具有与第一半导体芯片300的一部分交叠的第一端以及与第一桥接管芯501的一部分交叠的第二端。
第一半导体芯片300可包括第一组的芯片焊盘310。第一半导体芯片300可设置在RDL结构100上，使得第一半导体芯片300的第一芯片焊盘312电连接到第一RDL图案120的第一端。第一芯片焊盘312可被包括在第一组的芯片焊盘310中。第一半导体芯片300可按照倒装芯片形式安装在RDL结构100上，使得第一半导体芯片300的第一组的芯片焊盘310面向RDL结构100。
第一组的内连接器610可设置在第一半导体芯片300与RDL结构100之间以将第一半导体芯片300电连接到RDL结构100。第一组的内连接器610可以是导电凸块或焊料凸块。第一组的内连接器610中的第五内连接器612可接合到第一RDL图案120的一部分以将第一芯片焊盘312电连接到第一RDL图案120。第五内连接器612可以是第一组的内连接器610中的任一个。
第二半导体芯片400可包括设置在第二半导体芯片400的突起435上的第二组的芯片焊盘410。第二半导体芯片400可按照倒装芯片形式安装在第一半导体芯片300上。因此，设置在突起435上的第二组的芯片焊盘410中的第二芯片焊盘412可面向RDL结构100。由于第二芯片焊盘412设置在突起435上，所以第二芯片焊盘412可能不与第一半导体芯片300垂直地交叠以在第一半导体芯片300的外侧区域中露出。第二芯片焊盘412可以是第二组的芯片焊盘410中的任一个。
第一桥接管芯501可设置在RDL结构100上以与第二半导体芯片400的突起435交叠。第一桥接管芯501可被配置为包括第一主体510以及穿透第一主体510的多个通孔520。尽管图中未示出，绝缘层可另外设置在第一主体510与各个通孔520之间以将通孔520与第一主体510电绝缘。通孔520中的第一通孔522可被设置为与第二芯片焊盘412交叠，并且可电连接到第二半导体芯片400的第二芯片焊盘412。第一通孔522可以是通孔520中的任一个。第一通孔522可被设置为与第一RDL图案120的一部分交叠，并且可电连接到与第一通孔522交叠的第一RDL图案120。第一通孔522可被设置为在垂直方向上将第二芯片焊盘412电连接到第一RDL图案120。
第一桥接管芯501还可包括多个柱状凸块530。柱状凸块530可设置在第一主体510上以从第一主体510的顶表面突出。第一柱状凸块532可连接到第一通孔522的顶部。第一柱状凸块532可以是柱状凸块530中的任一个。
第三组的内连接器630可设置在第一桥接管芯501与第二半导体芯片400之间以将第一桥接管芯501电连接到第二半导体芯片400。第一桥接管芯501可通过第三组的内连接器630接合到第二半导体芯片400，并且可通过第三组的内连接器630电连接到第二半导体芯片400。第二内连接器632可将第二芯片焊盘412电连接到第一柱状凸块532。第二内连接器632可以是第三组的内连接器630中的任一个。第一桥接管芯501还可包括设置在第一主体510的底表面上通孔焊盘540。第一通孔焊盘542可连接到第一通孔522的底部。第一通孔焊盘542可以是通孔焊盘540中的任一个。
第二组的内连接器620可设置在第一桥接管芯501与RDL结构100之间以将第一桥接管芯501电连接到RDL结构100。第一桥接管芯501可通过第二组的内连接器620接合到RDL结构100，并且可通过第二组的内连接器620电连接到RDL结构100。第一内连接器622可接合并且电联接到第一通孔焊盘542。第一内连接器622可以是第二组的内连接器620中的任一个。第一内连接器622可接合到第一RDL图案120的一部分以将第一通孔焊盘542电连接到第一RDL图案120。
图3是示出将图2所示的第一半导体芯片300和第二半导体芯片400彼此电连接的第一电路径P1的立体图。
参照图2和图3，第一桥接管芯501在结构上支撑第二半导体芯片400的突起435并且还提供将第二半导体芯片400电连接到第一半导体芯片300的第一电路径P1的一部分。第一电路径P1可被配置为包括第二半导体芯片400的第二芯片焊盘412、第二内连接器632、第一柱状凸块532、第一通孔522、第一通孔焊盘542、第一内连接器622、第一RDL图案120、第五内连接器612和第一半导体芯片300的第一芯片焊盘312。
第一半导体芯片300可以是执行数据的逻辑运算的处理器。例如，第一半导体芯片300可包括诸如执行逻辑运算的应用处理器的***芯片(SoC)。第二半导体芯片400可以是存储数据的存储器半导体芯片。存储器半导体芯片可以是高速缓存存储器芯片，其暂时存储并提供在SoC的逻辑运算中使用的数据。第二半导体芯片400可被配置为包括DRAM装置。
第一半导体芯片300的第一组的芯片焊盘310可均匀地设置在第一半导体芯片300的第一表面301的整个区域上，如图3所示。第二半导体芯片400的第二组的芯片焊盘410可设置在第二半导体芯片400的突起435上。第二半导体芯片400的第二组的芯片焊盘410可设置在第二半导体芯片400的相对于第一半导体芯片300外伸(不交叠)的部分(即，突起435)上。第二半导体芯片400的第二组的芯片焊盘410可设置在第二半导体芯片400的***区域430上。设置有第二组的芯片焊盘410的***区域430可位于第二半导体芯片400的突起435的第一表面401上。
第二半导体芯片400可与第一半导体芯片300部分地交叠。第二半导体芯片400的除了突起435之外的其它区域可与第一半导体芯片300交叠。第二半导体芯片400的所述其它区域可由第一半导体芯片300共享。因此，第二半导体芯片400的第二组的芯片焊盘410可能不设置在第二半导体芯片400的所述其它区域上。
第一芯片焊盘312可通过第一电路径P1电连接到第二芯片焊盘412。第一芯片焊盘312可以是第一组的芯片焊盘310中的一个。尽管图3将第一电路径P1示出为单个路径，但SiP 10可包括多个第一电路径P1。在这种情况下，第一组的芯片焊盘310可分别通过多个第一电路径P1电连接到第二组的芯片焊盘410。在实施方式中，多个第一电路径P1中的每一个可被配置为包括第二半导体芯片400的第二组的芯片焊盘410中的一个、第三组的内连接器630中的一个、柱状凸块530中的一个、通孔520中的一个、通孔焊盘540中的一个、第二组的内连接器620中的一个、第一RDL图案120中的一个、第一组的内连接器610中的一个以及第一半导体芯片300的第一组的芯片焊盘310中的一个。由于第二半导体芯片400通过多个第一电路径P1电连接到第一半导体芯片300，所以可在第一半导体芯片300和第二半导体芯片400之间提供多个输入/输出(I/O)路径。即，由于两个相邻的半导体芯片通过与I/O路径对应的多个短信号路径彼此电连接，所以与通过单个路径相比，可通过多个路径在两个相邻的半导体芯片之间同时发送相对更多的数据。因此，可使用并行路径以给定速度从第一半导体芯片300向第二半导体芯片400发送更大量的数据，或者反之亦然。如果第一半导体芯片300是处理器芯片并且第二半导体芯片400是存储器芯片，则第一半导体芯片300可与充当高性能高速缓存存储器的第二半导体芯片400一起操作。因此，可改进包括第一半导体芯片300和第二半导体芯片400的SiP 10的操作速度和性能。
再参照图2，第二半导体芯片400还可包括第三芯片焊盘411，第三芯片焊盘411设置在突起435上以与第二芯片焊盘412间隔开。第一桥接管芯501还可包括第三柱状凸块531，第三柱状凸块531被设置为基本上与第三芯片焊盘411交叠。第一桥接管芯501还可包括第三通孔521，第三通孔521电连接到第三柱状凸块531并被设置为与第一通孔522间隔开。第一桥接管芯501还可包括电连接到第三通孔521的第三通孔焊盘541。
RDL结构100还可包括第三RDL图案110，第三RDL图案110被设置为与第一RDL图案120间隔开。第三RDL图案110可被设置为具有与第三通孔焊盘541交叠的部分。第三RDL图案110可通过第五RDL图案140电连接到第一外连接器210。第一外连接器210可以是连接到RDL结构100的多个外连接器200中的一个。外连接器200可充当将SiP 10电连接到外部装置的连接端子或连接引脚。外连接器200可以是诸如焊球的连接构件。
RDL结构100还可包括设置在第五RDL图案140与第三RDL图案110之间的第一介电层191。第五RDL图案140和第三RDL图案110可设置在第一介电层191上。第五RDL图案140可基本上穿透第一介电层191以连接到第三RDL图案110。RDL结构100还可包括第二介电层193，第二介电层193设置在第一介电层191的与外连接器200相对的表面上以将第三RDL图案110与第一RDL图案120电隔离。RDL结构100还可包括第三介电层195，第三介电层195设置在第一介电层191的与第一半导体芯片300相对的表面上以将第五RDL图案140与SiP 10的外部空间电隔离。第一外连接器210可基本上穿透第三介电层195以连接到第五RDL图案140。
第六内连接器621可接合到第三RDL图案110以将第三通孔焊盘541电连接到第三RDL图案110。第六内连接器621可以是将第一桥接管芯501电连接到RDL结构100的第二组的内连接器620中的任一个。第七内连接器631可将第三柱状凸块531电连接到第三芯片焊盘411。第七内连接器631可以是将第一桥接管芯501电连接到第二半导体芯片400的第三组的内连接器630中的任一个。
参照图2和图3，第二电路径P2可被设置为包括第一外连接器210、第五RDL图案140、第三RDL图案110、第六内连接器621、第三通孔焊盘541、第三通孔521、第三柱状凸块531、第七内连接器631和第三芯片焊盘411。第二电路径P2可以是将第二半导体芯片400电连接到第一外连接器210的路径。与第一电路径P1不同，第二电路径P2可能不电连接到第一半导体芯片300。第一电路径P1可将第一半导体芯片300和第二半导体芯片400彼此电连接，使得第一半导体芯片300和第二半导体芯片400彼此通信。相比之下，第二电路径P2可用作将电源电压或接地电压供应给第二半导体芯片400的电路径。
再参照图2，RDL结构100还可包括第四RDL图案130，第四RDL图案130被设置为与第一RDL图案120和第三RDL图案110间隔开。第四RDL图案130可被设置为与第一半导体芯片300交叠。第四RDL图案130可通过第六RDL图案150电连接到第二外连接器230。第一半导体芯片300还可包括第四芯片焊盘313，第四芯片焊盘313被设置为与第一芯片焊盘312间隔开。第三内连接器613可被设置为将第四芯片焊盘313电连接到第四RDL图案130。第三内连接器613可以是将第一半导体芯片300电连接到RDL结构100的第一组的内连接器610中的任一个。
第三电路径P3可被设置为包括第四芯片焊盘313、第三内连接器613、第四RDL图案130、第六RDL图案150和第二外连接器230。第三电路径P3可以是将第一半导体芯片300电连接到第二外连接器230的电路径。第一半导体芯片300可通过第三电路径P3与外部装置通信，或者可通过第三电路径P3从外部装置接收电力。
图4是示出图1的一部分(包括第二桥接管芯505)的放大横截面图。
参照图1和图4，第二桥接管芯505可设置在RDL结构100上以与第一半导体芯片300间隔开。第二桥接管芯505可将第二子封装SP2电连接到第二RDL图案170。RDL结构100可包括第二RDL图案170，第二RDL图案170被设置为与第一RDL图案120间隔开。第二RDL图案170可具有与第二桥接管芯505交叠的第一端并且可延伸以具有与第一半导体芯片300交叠的第二端。
第二桥接管芯505可被配置为包括第二主体515以及穿透第二主体515的多个通孔525。第二桥接管芯505的多个通孔525可包括第二通孔527。第二通孔527可被设置为与第二RDL图案170的第一端交叠并且可电连接到第二RDL图案170的第一端。
第二桥接管芯505还可包括多个通孔焊盘545，多个通孔焊盘545设置在第二主体515的与第二子封装SP2相对的表面上。第二通孔焊盘547可连接到第二通孔527的底部。第二通孔焊盘547可以是多个通孔焊盘545中的任一个。
多个内连接器625可设置在第二桥接管芯505与RDL结构100之间以将第二桥接管芯505电连接到RDL结构100。第二桥接管芯505可通过内连接器625接合到和电连接到RDL结构100。第八内连接器627可接合到并且电连接到第二通孔焊盘547。第八内连接器627可以是内连接器625中的任一个。第八内连接器627可接合到并且电连接到第二RDL图案170的第一端。
第一半导体芯片300的第五芯片焊盘317可通过第四内连接器617电连接到第二RDL图案170的第二端。第四内连接器617可以是将第一半导体芯片300电连接到RDL结构100的第一组的内连接器610中的任一个。第五芯片焊盘317可以是第一半导体芯片300的第一组的芯片焊盘310中的任一个。
第二桥接管芯505还可包括多个柱状凸块535。第二柱状凸块537可设置在第二主体515上以从第二主体515的顶表面突出。第二柱状凸块537可连接到第二通孔527的顶部。第二柱状凸块537可以是第二桥接管芯505的多个柱状凸块535中的任一个。
第二柱状凸块537可设置在模制层700的顶表面700S与第二主体515之间以基本上穿透模制层700。第二柱状凸块537的顶表面537S可在模制层700的顶表面700S处露出。柱状凸块535之间的空间(例如，第二柱状凸块537和与第二柱状凸块537相邻的第四柱状凸块538之间的空间)可由模制层700填充。第一互连器257可接合到第二柱状凸块537的顶表面537S。第一互连器257可以是将第二桥接管芯505电连接到第二子封装SP2的多个互连器250中的任一个。多个互连器250可以是诸如焊球的连接构件。
尽管图中未示出，第二子封装SP2可被设置为包括：半导体管芯，其包括集成电路；内部互连线，其用于半导体管芯中的组件之间的电连接；以及模制层，其保护半导体管芯。
第四电路径P4可被设置为包括第一互连器257、第二柱状凸块537、第二通孔527、第八内连接器627、第二RDL图案170、第四内连接器617和第五芯片焊盘317。第四电路径P4可充当将第二子封装SP2电连接到第一半导体芯片300的电路径。
RDL结构100还可包括第七RDL图案180，第七RDL图案180与第二RDL图案170间隔开。第七RDL图案180可电连接到第八RDL图案190，并且第八RDL图案190可电连接到第三外连接器270。第三外连接器270可以是外连接器200中的任一个。
第二桥接管芯505还可包括第四通孔528，第四通孔528被设置为与第二通孔527间隔开。第二桥接管芯505还可包括连接到第四通孔528的第四柱状凸块538和第四通孔焊盘548。第九内连接器628可被设置为将第四通孔焊盘548电连接到第七RDL图案180。第九内连接器628可以是内连接器625中的任一个。第二互连器258可将第四柱状凸块538电连接到第二子封装SP2。第二互连器258可以是互连器250中的任一个。
第二互连器258、第四柱状凸块538、第四通孔528、第四通孔焊盘548、第七RDL图案180、第八RDL图案190和第三外连接器270可构成第五电路径P5。第五电路径P5可以是将电源电压或接地电压供应给第二子封装SP2的电路径。
图5是示出图1的一部分(包括第一桥接管芯501和第二桥接管芯505)的放大横截面图。这里，由于两个桥接管芯505在结构上相似，所以给予图1的最右桥接管芯505及其组件与图1的最左桥接管芯505及其组件相同的标号。图6是示出图5所示的第一桥接管芯501和第二桥接管芯505的柱状凸块530和535的平面图。
参照图1和图5，第一桥接管芯501的第一主体510可对应于诸如硅基板的半导体基板。第二桥接管芯505的第二主体515也可对应于半导体基板(例如，硅基板)。由于第一桥接管芯501的第一主体510和第二桥接管芯505的第二主体515包括硅材料，所以可使用应用于硅晶圆的光刻工艺来形成通孔520和525。
第一桥接管芯501的通孔520可对应于具有直径D1的硅通孔(TSV)。直径D1可小于穿透模制层的模制通孔(TMV)的直径。因此，可增加具有有限尺寸的第一主体510中形成的通孔520的数量。第二桥接管芯505的通孔525也可形成为具有直径D11的TSV。
如图3所示，第二组的芯片焊盘410可密集地设置在第二半导体芯片400的突起435上。第一桥接管芯501的电连接到第二组的芯片焊盘410的柱状凸块530可包括至少两个凸块，如图6所示。在这种情况下，第一桥接管芯501的通孔520可对准以与第二组的芯片焊盘410交叠，使得第一桥接管芯501的柱状凸块530与第二半导体芯片400的第二组的芯片焊盘410交叠。由于使用TSV工艺形成第一桥接管芯501的通孔520，所以例如与TMV的直径相比，通孔520可形成为具有值相对小的直径D1。因此，可使第一桥接管芯501的分别与多个I/O端子、电源端子和接地端子对应的通孔520的数量最大化。即，即使第二组的芯片焊盘410密集地设置，也可形成第一桥接管芯501的通孔520，使得通孔520被设置为具有与第二组的芯片焊盘410相同的间距大小。因此，即使第二组的芯片焊盘410密集地设置，也可将第二组的芯片焊盘410垂直地连接到第一桥接管芯501的相应通孔520，而不在第二半导体芯片400上形成任何再分配线。
如果第一桥接管芯501的通孔520的直径D1减小，则通孔520的垂直长度也可减小。当第一桥接管芯501的通孔520形成为穿透具有厚度T3的第一主体510时，由于由通孔520填充的过孔的纵横比的限制，在减小通孔520的直径D1方面可存在限制。为了减小第一桥接管芯501的通孔520的直径D1，可能有必要减小第一主体510的厚度T3以满足形成通孔520的过孔的纵横比的限制。为了增加第一主体510中形成的通孔520的数量，可能有必要将第一主体510的厚度T3减小为小于第一半导体芯片300的厚度T1。在这种情况下，可减小第一桥接管芯501的通孔520的直径D1。
第一桥接管芯501的第一主体510的厚度T3可小于第二桥接管芯505的第二主体515的厚度T33。第一桥接管芯501的第一通孔522的直径D1可小于第二桥接管芯505的第二通孔527的直径D11。由于第二桥接管芯505的第二主体515比第一桥接管芯501的第一主体510厚，所以在由于纵横比的限制第二通孔527的直径D11大于第一通孔522的直径D1的情况下，第二通孔527可基本上充分地穿透第二主体515。
第二柱状凸块537的直径D22可大于第二通孔527的直径D11。第二通孔焊盘547的直径D33可大于第二通孔527的直径D11。第二柱状凸块537的直径D22也可大于第一柱状凸块532的直径D2。因此，如图6所示，柱状凸块535的间距大小S2可大于柱状凸块530的间距大小S1。
参照图5，为了第一桥接管芯501在结构上支撑第二半导体芯片400，第一桥接管芯501的总厚度T2被设定为等于第一半导体芯片300的厚度T1可能是有效的。例如，小于第一半导体芯片300的厚度T1的第一主体510的厚度T3可由第一桥接管芯501的柱状凸块530的厚度T4和第一桥接管芯501的通孔焊盘540的厚度T5补偿。即，通过适当地调节第一桥接管芯501的柱状凸块530的厚度T4，第一桥接管芯501的总厚度T2可被调节为等于第一半导体芯片300的厚度T1。第一桥接管芯501的总厚度T2可包括第一桥接管芯501的柱状凸块530的厚度T4、第一桥接管芯501的通孔焊盘540的厚度T5和第一主体510的厚度T3。
第一桥接管芯501的柱状凸块530可分别直接接合到第三组的内连接器630。第一柱状凸块532的直径D2可大于第一桥接管芯501的通孔520的直径D1。因此，用作第三组的内连接器630的焊料凸块可分别直接接合到第一桥接管芯501的柱状凸块530。为了第一桥接管芯501的通孔焊盘540直接接合到第二组的内连接器620，通孔焊盘540的直径D3可大于第一桥接管芯501的通孔520的直径D1。
图7是示出图1所示的第一半导体芯片300和第二半导体芯片400之间的连接部分的放大横截面图。
参照图1和图7，第二半导体芯片400可与第一半导体芯片300部分地交叠，并且第二半导体芯片400的突起435可由第一桥接管芯501支撑。第二半导体芯片400的突起435通过第三组的内连接器630接合到第一桥接管芯501，并且虚拟凸块690可用于支撑第二半导体芯片400的与突起435相对的边缘436。由于虚拟凸块690支撑第二半导体芯片400的边缘436，所以可防止第二半导体芯片400倾斜。由于当第二半导体芯片400的突起435接合到第一桥接管芯501时虚拟凸块690设置在第一半导体芯片300与第二半导体芯片400之间，所以第二半导体芯片400可维持水平高度。
虚拟凸块690可以是焊料凸块。虚拟凸块690可附接到第二半导体芯片400的第一表面401。虚拟接合焊盘691可形成在第二半导体芯片400的第一表面401上。在这种情况下，虚拟凸块690可接合到虚拟接合焊盘691。虚拟接合焊盘691可形成在设置在第二半导体芯片400的第一表面401上的钝化层425上。虚拟接合焊盘691可使用金属溅射工艺形成在钝化层425上。钝化层425可形成为覆盖第二半导体芯片400的主体420(由硅材料制成)并将其电绝缘。因此，虚拟凸块690可与第二半导体芯片400的内部电路电绝缘。虚拟凸块690可与第一半导体芯片300的与RDL结构100相对的第二表面302接触。
图8是示出根据另一实施方式的SiP 11的横截面图。
参照图8，SiP 11可被实现为具有层叠封装(PoP)形状。SiP 11可被配置为包括第一子封装SP1’以及安装在第一子封装SP1’上的第二子封装SP2。第一子封装SP1’可被配置为包括RDL结构100、第一半导体芯片300、第二半导体芯片400、第一桥接管芯501、第二桥接管芯505和模制层700。第二半导体芯片400可与第一半导体芯片300部分地交叠，并且第二半导体芯片400的突起435可由第一桥接管芯501在结构上支撑。粘合层690L可设置在第一半导体芯片300与第二半导体芯片400之间。粘合层690L可支撑第二半导体芯片400。当第二半导体芯片400的突起435接合到第一桥接管芯501并由第一桥接管芯501支撑时，粘合层690L可防止第二半导体芯片400倾斜。粘合层690L可帮助第二半导体芯片400维持水平高度。
粘合层690L可附接到第二半导体芯片400的第一表面401和第一半导体芯片300的第二表面302。粘合层690L可将第二半导体芯片400接合到第一半导体芯片300。
图9是示出根据另一实施方式的SiP 12的横截面图。
参照图9，SiP 12可被实现为具有层叠封装(PoP)形状。SiP 12可被配置为包括第一子封装SP1”以及安装在第一子封装SP1”上的第二子封装SP2。第一子封装SP1”可被配置为包括RDL结构100、第一半导体芯片300、第二半导体芯片400、第一桥接管芯501-1、第二桥接管芯505-1和模制层700。
第一半导体芯片300可设置在RDL结构100上。第二半导体芯片400可层叠在第一半导体芯片300上以与第一半导体芯片300交叠。第一组的内连接器610可设置在第一半导体芯片300与RDL结构100之间以将第二半导体芯片400电连接到RDL结构100。第一组的内连接器610中的第五内连接器612可接合到第一RDL图案120的一部分以将第一组的芯片焊盘310中的第一芯片焊盘312电连接到第一RDL图案120。第二半导体芯片400可包括在第二半导体芯片400的突起435上的第二组的芯片焊盘410。
RDL结构100还可包括第三RDL图案110，第三RDL图案110被设置为与第一RDL图案120间隔开。第三RDL图案110可通过第五RDL图案140电连接到外连接器200中的第一外连接器210。RDL结构100可包括设置在第五RDL图案140与第三RDL图案110之间的第一介电层191。第三RDL图案110和第一RDL图案120可设置在第一介电层191上。第五RDL图案140可基本上穿透第一介电层191以连接到第三RDL图案110。
RDL结构100还可包括第二介电层193，第二介电层193设置在第一介电层191的与外连接器200相对的表面上以将第三RDL图案110和第一RDL图案120彼此电隔离。RDL结构100还可包括第三介电层195，第三介电层195设置在第一介电层191的与第一半导体芯片300相对的表面上以将第五RDL图案140与SiP 12的外部空间电隔离。第一外连接器210可基本上穿透第三介电层195以连接到第五RDL图案140。
第一桥接管芯501-1可设置在RDL结构100上以支撑第二半导体芯片400的突起435。当第二半导体芯片400的突起435由第一桥接管芯501-1在结构上支撑时，虚拟凸块690可用于支撑第二半导体芯片400的与突起435相对的边缘436。
第一桥接管芯501-1可被配置为包括第一模制材料基板510-1以及穿透第一模制材料基板510-1的通孔520-1。通孔520-1中的第一通孔522-1可将第二半导体芯片400的第二芯片焊盘412电连接到第一RDL图案120。
第一桥接管芯501-1可通过第三组的内连接器630电连接到第二半导体芯片400。第三组的内连接器630中的第二内连接器632可将第二芯片焊盘412电连接到第一通孔522-1。第二组的内连接器620可将第一桥接管芯501-1电连接到第一RDL图案120。第一内连接器622可接合到第一RDL图案120的一部分以将第一通孔522-1电连接到第一RDL图案120。
第二半导体芯片400可通过第一电路径电连接到第一半导体芯片300。第一电路径可包括第二半导体芯片400的第二芯片焊盘412、第二内连接器632、第一通孔522-1、第一内连接器622、第一RDL图案120、第五内连接器612和第一半导体芯片300的第一芯片焊盘312。
第二半导体芯片400还可包括第三芯片焊盘411，第三芯片焊盘411设置在突起435上以与第二芯片焊盘412间隔开。第一桥接管芯501-1还可包括第三通孔521-1，第三通孔521-1被设置为与第三芯片焊盘411基本上交叠。
第六内连接器621可接合到第三RDL图案110以将第三通孔521-1电连接到第三RDL图案110。第三组的内连接器630中的第七内连接器631可将第三通孔521-1电连接到第三芯片焊盘411。
第一外连接器210、第五RDL图案140、第三RDL图案110、第六内连接器621、第三通孔521-1、第七内连接器631和第三芯片焊盘411可构成第二电路径。第二电路径可以是将第二半导体芯片400电连接到第一外连接器210的路径。第四芯片焊盘313、第三内连接器613、第四RDL图案130、第六RDL图案150和第二外连接器230可构成第三电路径。
RDL结构100还可包括第四RDL图案130，第四RDL图案130被设置为与第一RDL图案120间隔开。第四RDL图案130可通过第六RDL图案150电连接到第二外连接器230。第一半导体芯片300还可包括第四芯片焊盘313，第四芯片焊盘313被设置为与第一芯片焊盘312间隔开。第三内连接器613可将第四芯片焊盘313电连接到第四RDL图案130。
第二桥接管芯505-1可设置在RDL结构100上以与第一半导体芯片300间隔开。第二桥接管芯505-1可将第二子封装SP2电连接到第二RDL图案170。
第二桥接管芯505-1可被配置为包括第二模制材料基板515-1以及穿透第二模制材料基板515-1的通孔525-1。通孔525-1中的第二通孔527-1可被设置为与第二RDL图案170的一部分交叠并且可电连接到第二RDL图案170的该部分。
内连接器625可设置在第二桥接管芯505-1与RDL结构100之间以将第二桥接管芯505-1电连接到RDL结构100。内连接器625中的第八内连接器627可将第二通孔527-1连接到第二RDL图案170的一部分。
第二桥接管芯505-1可被设置为使得第二通孔527-1的顶表面527-1S在模制层700的顶表面700S处露出。第二桥接管芯505-1可被设置为基本上穿透模制层700。第一互连器257可接合到第二通孔527-1的顶表面527-1S。第一互连器257可以是将第二桥接管芯505电连接到第二子封装SP2的互连器250中的任一个。
尽管图中未示出，第二子封装SP2可被设置为包括：半导体管芯，其包括集成电路；内部互连线，其用于半导体管芯中的组件之间的电连接；以及模制层，其保护半导体管芯。
第一互连器257、第二通孔527-1、第八内连接器627、第二RDL图案170、第四内连接器617和第五芯片焊盘317可构成第四电路径。第四电路径可充当将第二子封装SP2电连接到第一半导体芯片300的电路径。
RDL结构100还可包括与第二RDL图案170间隔开的第七RDL图案180。第七RDL图案180可电连接到第八RDL图案190，第八RDL图案190可电连接到第三外连接器270。
第二桥接管芯505-1还可包括第四通孔528-1，第四通孔528-1被设置为与第二通孔527-1间隔开。内连接器625中的第九内连接器628可被设置为将第四通孔焊盘528-1电连接到第七RDL图案180。第二互连器258可将第四通孔528-1电连接到第二子封装SP2。
第二互连器258、第四通孔528-1、第七RDL图案180、第八RDL图案190和第三外连接器270可构成第五电路径。第五电路径可以是将电源电压或接地电压供应给第二子封装SP2的电路径。
再参照图9，第一桥接管芯501-1的第一模制材料基板510-1可由模制材料或包封材料形成。第二桥接管芯505-1的第二模制材料基板515-1可由模制材料或包封材料形成。第一模制材料基板510-1和第二模制材料基板515-1可包括两种不同的材料。第一模制材料基板510-1和第二模制材料基板515-1可由不同于模制层700的材料形成。例如，第一模制材料基板510-1和第二模制材料基板515-1可由组分不同于模制层700的环氧模制料(EMC)材料的组分的EMC材料形成。
第一桥接管芯501-1的第一通孔522-1或第二桥接管芯505-1的第二通孔527-1可形成为包括镀层。例如，第一桥接管芯501-1的第一通孔522-1或第二桥接管芯505-1的第二通孔527-1可形成为包括铜镀层。更具体地，在使用镀覆工艺形成第一桥接管芯501-1的第一通孔522-1或第二桥接管芯505-1的第二通孔527-1之后，可形成覆盖第一通孔522-1的第一模制层或覆盖第二通孔527-1的第二模制层。由于纵横比的限制，在减小第一通孔或第二通孔(图5的522或527)的直径或增加第一通孔或第二通孔(图5的522或527)的长度方面可存在限制。然而，在形成第一模制层或第二模制层之前使用镀覆工艺形成第一通孔522-1或第二通孔527-1的情况下，可形成第一通孔522-1或第二通孔527-1而没有由第一通孔522-1或第二通孔527-1填充的贯通孔的纵横比的任何限制。
如上所述，根据一些实施方式，第二半导体芯片400可层叠在第一半导体芯片300上以减小SiP 10、11或12的宽度或大小。根据SiP 10、11或12，由于第二半导体芯片400使用第一桥接管芯501或501-1电连接到第一半导体芯片300，所以可在第一半导体芯片300上层叠第二半导体芯片400。
对半导体芯片施加热的工艺可使半导体芯片(具体地，存储器芯片)的特性劣化。例如，当热施加到DRAM装置时，DRAM装置的存储器单元的数据保持时间减少，从而减小DRAM装置的刷新循环时间。另外，如果热施加到NAND型闪存装置，则NAND型闪存装置的存储器单元的数据保持时间也可减小。
根据本教导的实施方式的SiP 10、11和12可被实现为包括内连接器，内连接器附接到RDL结构100以用于半导体芯片之间以及外部装置与半导体芯片之间的互连。因此，可省略或减少使用于形成再分配线的聚合物层固化的热工艺(或退火工艺)。结果，SiP 10、11和12的性能可改进。例如，如果在形成RDL结构100之后第一半导体芯片300和第二半导体芯片400层叠在RDL结构100上以形成SiP 10、11或12，则当执行热工艺(或退火工艺)以使用于形成RDL图案的聚合物层固化时，可防止热施加到第一半导体芯片300和第二半导体芯片400。
图10是示出包括采用根据实施方式的***级封装(SiP)中的至少一个的存储卡7800的电子***的框图。存储卡7800包括诸如非易失性存储器装置的存储器7810以及存储控制器7820。存储器7810和存储控制器7820可存储数据以及读出所存储的数据。存储器7810和存储控制器7820中的至少一个可包括根据实施方式的SiP中的至少一个。
存储器7810可包括应用了本公开的实施方式的技术的非易失性存储器装置。存储控制器7820可控制存储器7810，使得响应于来自主机7830的读/写请求，读出所存储的数据或者存储数据。
图11是示出包括根据实施方式的SiP中的至少一个的电子***8710的框图。电子***8710可包括控制器8711、输入/输出单元8712和存储器8713。控制器8711、输入/输出单元8712和存储器8713可通过提供数据移动的路径的总线8715彼此联接。
在实施方式中，控制器8711可包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件。控制器8711或存储器8713可包括根据本公开的实施方式的SiP中的至少一个。输入/输出单元8712可包括选自键区、键盘、显示装置、触摸屏等中的至少一个。存储器8713是用于存储数据的装置。存储器8713可存储要由控制器8711执行的数据和/或命令等。
存储器8713可包括诸如DRAM的易失性存储器装置和/或诸如闪存的非易失性存储器装置。例如，闪存可被安装到诸如移动终端或台式计算机的信息处理***。闪存可构成固态盘(SSD)。在这种情况下，电子***8710可在闪存***中稳定地存储大量数据。
电子***8710还可包括被配置为向通信网络发送数据以及从通信网络接收数据的接口8714。接口8714可为有线或无线型。例如，接口8714可包括天线或者有线或无线收发器。
电子***8710可被实现为移动***、个人计算机、工业计算机或者执行各种功能的逻辑***。例如，移动***可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐***和信息发送/接收***中的任一个。
如果电子***8710是能够执行无线通信的设备，则电子***8710可用在使用CDMA(码分多址)、GSM(全球移动通信***)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信***中。
出于例示性目的公开了本公开的实施方式。本领域技术人员将理解，在不脱离本公开和所附权利要求的范围和精神的情况下，可进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求2019年2月22日提交的韩国申请No.10-2019-0021452的优先权，其整体通过引用并入本文。

Claims (21)

1.一种***级封装，该***级封装包括：
第一子封装；以及
安装在所述第一子封装上的第二子封装，
其中，所述第一子封装包括：
再分配线RDL结构，该RDL结构包括第一RDL图案和第二RDL图案；
第一半导体芯片，该第一半导体芯片设置在所述RDL结构上，使得所述第一半导体芯片的电连接到所述第一RDL图案的第一芯片焊盘面向所述RDL结构；
第二半导体芯片，该第二半导体芯片层叠在所述第一半导体芯片上，使得所述第二半导体芯片突出越过所述第一半导体芯片的侧表面，其中，设置在所述第二半导体芯片的突起上的第二芯片焊盘面向所述RDL结构；
第一桥接管芯，该第一桥接管芯设置在所述RDL结构上以支撑所述第二半导体芯片的所述突起，其中，所述第一桥接管芯包括由第一通孔穿透的第一主体，其中，所述第一通孔将所述第二芯片焊盘电连接到所述第一RDL图案；
第二桥接管芯，该第二桥接管芯设置在所述RDL结构上并且与所述第一半导体芯片间隔开，其中，所述第二桥接管芯包括由第二通孔穿透的第二主体，其中，所述第二通孔将所述第二子封装电连接到所述第二RDL图案；以及
模制层，该模制层设置在所述RDL结构上以覆盖所述第一半导体芯片和所述第一桥接管芯并且围绕所述第二半导体芯片和所述第二桥接管芯。
2.根据权利要求1所述的***级封装，其中，
所述第二半导体芯片包括被配置为存储数据的第一存储器半导体芯片；
所述第一半导体芯片包括***芯片SoC，该SoC被配置为通过第一电路径接收存储在所述第一存储器半导体芯片中的数据，该第一电路径包括所述第二芯片焊盘、所述第一通孔、所述第一RDL图案和所述第一芯片焊盘；并且
所述第二子封装包括电连接到所述SoC的第二存储器半导体芯片。
3.根据权利要求1所述的***级封装，其中，所述第一桥接管芯包括：
第一柱状凸块，该第一柱状凸块设置在所述第一主体的顶表面上并且电连接到所述第一通孔，其中，所述第一柱状凸块的直径大于所述第一通孔的直径；以及
第一通孔焊盘，该第一通孔焊盘设置在所述第一主体的底表面上并且电连接到所述第一通孔，其中，所述第一通孔焊盘的直径大于所述第一通孔的直径。
4.根据权利要求3所述的***级封装，该***级封装还包括：
第一内连接器，该第一内连接器将所述第一通孔焊盘电连接到所述第一RDL图案；以及
第二内连接器，该第二内连接器将所述第一柱状凸块电连接到所述第二芯片焊盘。
5.根据权利要求4所述的***级封装，该***级封装还包括设置在所述第一半导体芯片与所述第二半导体芯片之间并且与所述第二内连接器间隔开的虚拟凸块，其中，该虚拟凸块被配置为支撑所述第二半导体芯片。
6.根据权利要求5所述的***级封装，其中，
所述第二半导体芯片还包括设置在所述第二半导体芯片的面向所述第一半导体芯片的表面上的虚拟接合焊盘；并且
所述虚拟凸块接合到所述虚拟接合焊盘。
7.根据权利要求4所述的***级封装，该***级封装还包括设置在所述第一半导体芯片与所述第二半导体芯片之间并且与所述第二内连接器间隔开的粘合层，其中，该粘合层被配置为支撑所述第二半导体芯片。
8.根据权利要求3所述的***级封装，其中，
所述第二半导体芯片还包括第三芯片焊盘，该第三芯片焊盘设置在所述突起上并且与所述第二芯片焊盘间隔开；
所述RDL结构还包括第三RDL图案，该第三RDL图案与所述第一RDL图案间隔开并且电连接到第一外连接器；并且
所述第一桥接管芯还包括第三通孔和第三柱状凸块，所述第三通孔与所述第一通孔间隔开并且通过所述第三RDL图案将所述第三芯片焊盘电连接到所述第一外连接器，所述第三柱状凸块电连接到所述第三通孔。
9.根据权利要求8所述的***级封装，其中，所述第一外连接器、所述第三RDL图案、所述第三通孔、所述第三柱状凸块和所述第三芯片焊盘构成将电源电压供应给所述第二半导体芯片或者将所述第二半导体芯片接地的第二电路径。
10.根据权利要求3所述的***级封装，其中，所述第二桥接管芯还包括：
第二柱状凸块，该第二柱状凸块设置在所述第二主体的在所述模制层的顶表面处露出的顶表面上，其中，所述第二柱状凸块直接连接到所述第二通孔并且电连接到所述第二子封装，并且其中，所述第二柱状凸块的直径大于所述第二通孔的直径；以及
第二通孔焊盘，该第二通孔焊盘设置在所述第二主体的底表面上并且电连接到所述第二通孔，其中，所述第二通孔焊盘的直径大于所述第二通孔的直径。
11.根据权利要求10所述的***级封装，其中，
所述第一桥接管芯的所述第一主体的厚度小于所述第二桥接管芯的所述第二主体的厚度；并且
所述第一通孔的直径小于所述第二通孔的直径。
12.根据权利要求11所述的***级封装，其中，
所述第一桥接管芯的所述第一主体的厚度小于所述第一半导体芯片的厚度；并且
所述第二桥接管芯的所述第二主体的厚度大于所述第一半导体芯片的厚度。
13.根据权利要求12所述的***级封装，其中，所述第一柱状凸块、所述第一通孔和所述第一通孔焊盘的组合厚度基本上等于所述第一半导体芯片的厚度。
14.根据权利要求10所述的***级封装，该***级封装还包括互连器，该互连器接合到所述第二桥接管芯的所述第二柱状凸块以将所述第二柱状凸块电连接到所述第二子封装。
15.根据权利要求1所述的***级封装，
其中，所述第一桥接管芯的所述第一主体包括硅材料；并且
其中，所述第一桥接管芯的所述第一通孔包括硅通孔TSV。
16.根据权利要求1所述的***级封装，其中，
所述RDL结构还包括第四RDL图案，该第四RDL图案与所述第一RDL图案间隔开并且电连接到第二外连接器；并且
所述第一半导体芯片还包括第四芯片焊盘，该第四芯片焊盘通过第三内连接器电连接到所述第四RDL图案。
17.根据权利要求1所述的***级封装，其中，所述第一半导体芯片还包括第五芯片焊盘，该第五芯片焊盘通过第四内连接器电连接到所述第二RDL图案。
18.一种***级封装，该***级封装包括：
第一子封装；以及
安装在所述第一子封装上的第二子封装，
其中，所述第一子封装包括：
再分配线RDL结构，该RDL结构包括第一RDL图案和第二RDL图案；
第一半导体芯片，该第一半导体芯片设置在所述RDL结构上，使得所述第一半导体芯片的电连接到所述第一RDL图案的第一芯片焊盘面向所述RDL结构；
第二半导体芯片，该第二半导体芯片层叠在所述第一半导体芯片上，使得所述第二半导体芯片突出越过所述第一半导体芯片的侧表面，其中，设置在所述第二半导体芯片的突起上的第二芯片焊盘面向所述RDL结构；
第一桥接管芯，该第一桥接管芯设置在所述RDL结构上以支撑所述第二半导体芯片的所述突起，其中，所述第一桥接管芯包括由第一通孔穿透的第一模制材料基板，其中，所述第一通孔将所述第二芯片焊盘电连接到所述第一RDL图案；
第二桥接管芯，该第二桥接管芯设置在所述RDL结构上并且与所述第一半导体芯片间隔开，其中，所述第二桥接管芯包括由第二通孔穿透的第二模制材料基板，其中，所述第二通孔将所述第二子封装电连接到所述第二RDL图案；以及
模制层，该模制层设置在所述RDL结构上以覆盖所述第一半导体芯片和所述第一桥接管芯并且围绕所述第二半导体芯片和所述第二桥接管芯。
19.根据权利要求18所述的***级封装，其中，
所述第二半导体芯片包括被配置为存储数据的第一存储器半导体芯片；
所述第一半导体芯片包括***芯片SoC，该SoC被配置为通过第一电路径接收存储在所述第一存储器半导体芯片中的数据，该第一电路径包括所述第二芯片焊盘、所述第一通孔、所述第一RDL图案和所述第一芯片焊盘；并且
所述第二子封装包括电连接到所述SoC的第二存储器半导体芯片。
20.根据权利要求18所述的***级封装，其中，所述第一桥接管芯包括：
第一内连接器，该第一内连接器将所述第一通孔电连接到所述第一RDL图案；以及
第二内连接器，该第二内连接器将所述第一通孔电连接到所述第二芯片焊盘。
21.根据权利要求18所述的***级封装，其中，所述第一桥接管芯的所述第一模制材料基板包括与用于所述模制层的材料不同的模制材料。
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