CN111602226A - 具有外延层的半导体晶片 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 230000007717 exclusion Effects 0.000 claims abstract description 9
- 235000012431 wafers Nutrition 0.000 description 52
- 238000000151 deposition Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 9
- 238000005498 polishing Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000000126 substance Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
- C23C16/4585—Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
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Abstract
一种单晶硅半导体晶片,其包括单晶硅衬底晶片和位于所述衬底晶片的正面上的单晶硅层,所述衬底晶片具有晶体取向,其中在所述外延层的表面被分为16个扇区且边缘排除为1mm的情况下,所述半导体晶片的基于正面的平均ZDD为不小于‑30nm/mm2且不大于0nm/mm2,以及在边缘排除为1mm,具有72个扇区,每个扇区长度为30mm的情况下所述半导体晶片的ESFQRmax为最大10nm。
Description
本发明提供一种单晶硅半导体晶片,其包括单晶硅衬底晶片和位于该衬底晶片之上的单晶硅层,其在下文中被称为具有外延层的硅半导体晶片(硅外延晶片)。
具有外延层的这种硅半导体晶片的生产包括借助于气相沉积(化学气相沉积CVD)在衬底晶片上沉积外延层。特别合适的CVD是在单晶片反应器中在标准压力(大气压)下进行的CVD。
US5355831公开了用于这种过程的典型过程参数,其可以被认为是说明性的。
苛刻的应用要求具有外延层的硅半导体晶片具有特别均匀的边缘几何形状。先决条件是外延层的厚度是特别均匀的。
US 2007/0227441 A1指出了在这种硅半导体晶片的边缘区域中外延层的厚度的周期性变化。原因是外延层生长的生长速率不同。不同的生长速率与半导体晶片的晶体取向相关。为了使边缘区域中的外延层的厚度均匀,US 2007/0227441 A1提出了通过厚度变化的周期来改变基座的结构。
该提议可以减轻该问题,但是对于电子元件制造商对未来的期望而言是不足的。
本发明的目的是提出一种更好地满足要求的建议。
该目的通过单晶硅的半导体晶片来实现,所述半导体晶片包括单晶硅的衬底晶片和位于该衬底晶片的正面上的单晶硅层,所述衬底晶片具有晶体取向,其中在将外延层的表面划分为16个扇区且边缘排除为1mm的情况下所述半导体晶片的基于正面的平均ZDD为不小于-30nm/mm2且不大于0nm/mm2,以及在边缘排除为1mm且具有72个扇区,每个扇区长度为30mm的情况下所述半导体晶片的ESFQRmax为最大10nm。
ZDD和ESFQR是表征半导体晶片边缘几何形状的参数,SEMI标准也规定了这些参数(ZDD(SEMI M68-1015),ESFQR(SEMI M67-1015))。基于正面的ZDD描述了表面的平均近边缘曲率。ESFQRmax表示ESFQR处于最大值的那个扇区的ESFQR。
本发明的具有外延层的半导体晶片在外延层的边缘几何形状中基本上没有显示出角度相关性变化,这是因为其生产可以防止这种变化的发生。与常规方法不同,外延层基本上仅覆盖确定衬底晶片的晶体取向的衬底层的正面的主要表面,而基本上不覆盖具有不同的晶体取向的正面区域,因为在衬底层的边缘处提供的氧化物层在很大程度上防止了外延层沉积在这样的区域中。以基于正面的ZDD(垂直于外延层表面的正中面的高度的二阶导数)表示,并表示为确定ZDD的扇区的平均ZDD,在将外延层的表面划分为16个扇区并且遵循边缘排除为1mm的情况下具有外延层的半导体晶片的边缘几何形状为不小于-30nm/mm2且不大于0nm/mm2。背面上的氧化物层另外在外延层沉积在正面上时防止材料沉积在背面上,从而使ESFQR变差。因此,在边缘排除为1mm,并且具有72个扇区,每个扇区长度为30mm的情况下半导体晶片的ESFQRmax为最大10nm。
本发明的半导体晶片的直径优选为不小于300mm,更优选为300mm。
本发明的半导体晶片的生产优选包括以下步骤:
提供单晶硅衬底晶片;
在所述衬底晶片上产生氧化层;
对衬底晶片进行不对称双面抛光,其部分去除了氧化物层并限制其程度在衬底晶片的背面和边缘区域的表面上;
在衬底晶片的正面上进行CMP;
在衬底晶片的正面上沉积单晶硅的外延层;和
从衬底晶片上去除氧化物层。
根据本发明,衬底晶片的边缘区域和背面被氧化层掩盖,并且CMP(化学机械抛光)步骤产生衬底晶片镜面抛光的正面,其构成了具有均匀晶体取向的主表面的大部分。衬底晶片的正面的主表面的晶体取向优选为{100}取向或{110}取向。随后将外延层沉积在正面上。现在,在外延层的厚度上几乎没有出现角度相关性变化。这样的变化源自外延层在具有不同晶体取向的表面上以与其相关的不同沉积速率沉积。氧化物层的存在防止在其上沉积外延层。
这里的不对称双面抛光是指双面抛光,其中在正面上材料的去除快于背面,并且在抛光结束时,氧化物层已经从正面完全抛光掉了,但仍存在于背面上。例如,EP 0 857542 A1描述了如何实现材料的不对称去除。
氧化物层是二氧化硅层,并且优选通过CVD,更优选通过AP-CVD(大气压CVD)来生产。或者,氧化物层也可以借助于LP-CVD(低压CVD)或通过热来制造。氧化物层的厚度优选为不小于5nm且不大于100nm。首先,衬底晶片被氧化物层完全覆盖。随后,对衬底晶片进行不对称DSP抛光,在此过程中,衬底晶片的正面上的氧化物层被去除,但是在背面和边缘区域中保留该氧化物。接下来是对衬底晶片的正面进行单面CMP抛光。该过程的结果是在衬底晶片的CMP抛光区域中不再存在氧化物层。
外延层沉积在不含氧化层的衬底晶片的正面上。可以在沉积外延层之前通过用氢处理正面(H2烘烤)来去除天然氧化物。在沉积外延层时,衬底晶片位于CVD反应器的基座上,使得正面暴露于沉积气体。由于正面的晶体取向基本上是均匀的,并且优选为{100}晶体取向或{110}晶体取向,所以外延层在衬底晶片的正面上以基本均匀的沉积速率生长。因此,外延层的厚度基本上是均匀的。边缘区域中外延层厚度的角度相关性变化基本上是不可检测的,因为氧化物层是导致边缘区域中外延沉积的障碍。
硅外延层的厚度优选为1至15μm,更优选为1至7μm。沉积温度优选为900℃至1250℃。沉积气体包含作为硅源的硅烷,优选三氯硅烷,和氢。
在已经沉积外延层之后,优选通过湿化学途径借助于包含氟化氢和任选存在的氯化氢和/或氟化铵的化学物质去除氧化物层。氟化氢的浓度优选为0.2重量%至49重量%。湿化学步骤可以是清洁顺序的一部分,在该过程中,用另外的化学物例如用臭氧水和/或SC1溶液处理半导体晶片。与此相反,还可以在干燥条件下例如通过等离子体蚀刻或反应离子蚀刻(RIE)去除氧化物层。
实施例:
在CVD反应器中,用氧化物层完全涂覆直径为300mm且具有正面的{100}取向的单晶硅衬底晶片。此后,首先通过DSP(在正面上用硬的(除去更多材料)的抛光布,在背面上用软的(除去较少材料的)抛光布)对衬底晶片进行抛光,然后通过CMP对正面进行抛光,并清洁。
随后,在包含氟化氢的浴中从所得外延涂覆的半导体晶片的边缘和背面去除氧化物层。
清洗并干燥半导体晶片,并进行边缘几何形状的测量。在边缘排除为1mm,外延层分为16个扇区的情况下,用KLA-Tencor Wafersight仪器测得的基于正面的平均ZDD为-27nm/mm2。在边缘排除为1mm,有72个扇区,每个扇区的长度为30mm的情况下,ESFQRmax为8nm。
对比例:
如在实施例中那样,用单晶硅的外延层涂覆具有实施例的特性的另一单晶硅衬底晶片。然而,省略了氧化物层的生产。忽略这一点对所得的半导体晶片的边缘几何形状有明显的不利影响:相应的基于正面的平均ZDD值为-120nm/mm2,相应的ESFQRmax为23nm。
Claims (4)
1.一种单晶硅半导体晶片,其包括单晶硅衬底晶片和位于所述衬底晶片的正面上的单晶硅层,所述衬底晶片具有晶体取向,其中在所述外延层的表面被分为16个扇区且边缘排除为1mm的情况下,所述半导体晶片的基于正面的平均ZDD为不小于-30nm/mm2且不大于0nm/mm2,以及在边缘排除为1mm,具有72个扇区,每个扇区长度为30mm的情况下所述半导体晶片的ESFQRmax为最大10nm。
2.根据权利要求1所述的单晶硅半导体晶片,其中,所述晶体取向是{100}取向。
3.根据权利要求1或2所述的单晶硅半导体晶片,其中,所述晶体取向是{110}取向。
4.根据权利要求1至3中任一项所述的单晶硅半导体晶片,其特征在于,所述半导体晶片的直径为不小于300mm。
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DE102018200415.3A DE102018200415A1 (de) | 2018-01-11 | 2018-01-11 | Halbleiterscheibe mit epitaktischer Schicht |
PCT/EP2018/084620 WO2019137728A1 (de) | 2018-01-11 | 2018-12-12 | Halbleiterscheibe mit epitaktischer schicht |
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JP (1) | JP6996001B2 (zh) |
KR (1) | KR102416913B1 (zh) |
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DE (1) | DE102018200415A1 (zh) |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110039411A1 (en) * | 2009-08-12 | 2011-02-17 | Siltronic Ag | Method For Producing A Polished Semiconductor Wafer |
CN103493184A (zh) * | 2011-04-26 | 2014-01-01 | 信越半导体股份有限公司 | 半导体晶片及其制造方法 |
WO2017102597A1 (de) * | 2015-12-17 | 2017-06-22 | Siltronic Ag | Verfahren zum epitaktischen beschichten von halbleiterscheiben und halbleiterscheibe |
CN107210222A (zh) * | 2015-01-21 | 2017-09-26 | 硅电子股份公司 | 外延涂布的半导体晶圆和生产外延涂布的半导体晶圆的方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4119531A1 (de) | 1991-06-13 | 1992-12-17 | Wacker Chemitronic | Epitaxierte halbleiterscheiben mit sauerstoffarmer zone einstellbarer ausdehnung und verfahren zu ihrer herstellung |
DE19704546A1 (de) | 1997-02-06 | 1998-08-13 | Wacker Siltronic Halbleitermat | Verfahren zur Herstellung einer einseitig beschichteten und mit einem Finish versehenen Halbleiterscheibe |
JP2006190703A (ja) | 2004-12-28 | 2006-07-20 | Shin Etsu Handotai Co Ltd | エピタキシャルウェーハの製造方法及びエピタキシャルウェーハ |
TW200802552A (en) | 2006-03-30 | 2008-01-01 | Sumco Techxiv Corp | Method of manufacturing epitaxial silicon wafer and apparatus thereof |
JP2010021441A (ja) | 2008-07-11 | 2010-01-28 | Sumco Corp | エピタキシャル基板ウェーハ |
KR20100121837A (ko) * | 2009-05-11 | 2010-11-19 | 주식회사 실트론 | 가장자리의 평탄도가 제어된 에피택셜 웨이퍼 및 그 제조 방법 |
JP2013055231A (ja) | 2011-09-05 | 2013-03-21 | Shin Etsu Handotai Co Ltd | エピタキシャルウェーハの製造方法 |
JP6312976B2 (ja) * | 2012-06-12 | 2018-04-18 | Sumco Techxiv株式会社 | 半導体ウェーハの製造方法 |
JP6035982B2 (ja) | 2012-08-09 | 2016-11-30 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法およびエピタキシャルシリコンウェーハ |
DE102013218880A1 (de) * | 2012-11-20 | 2014-05-22 | Siltronic Ag | Verfahren zum Polieren einer Halbleiterscheibe, umfassend das gleichzeitige Polieren einer Vorderseite und einer Rückseite einer Substratscheibe |
KR101810643B1 (ko) * | 2016-02-02 | 2017-12-19 | 에스케이실트론 주식회사 | 에피텍셜 웨이퍼의 평탄도 제어 방법 |
DE102016210203B3 (de) | 2016-06-09 | 2017-08-31 | Siltronic Ag | Suszeptor zum Halten einer Halbleiterscheibe, Verfahren zum Abscheiden einer epitaktischen Schicht auf einer Vorderseite einer Halbleiterscheibe und Halbleiterscheibe mit epitaktischer Schicht |
-
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110039411A1 (en) * | 2009-08-12 | 2011-02-17 | Siltronic Ag | Method For Producing A Polished Semiconductor Wafer |
CN101996863A (zh) * | 2009-08-12 | 2011-03-30 | 硅电子股份公司 | 用于制造抛光的半导体晶片的方法 |
CN103493184A (zh) * | 2011-04-26 | 2014-01-01 | 信越半导体股份有限公司 | 半导体晶片及其制造方法 |
CN107210222A (zh) * | 2015-01-21 | 2017-09-26 | 硅电子股份公司 | 外延涂布的半导体晶圆和生产外延涂布的半导体晶圆的方法 |
WO2017102597A1 (de) * | 2015-12-17 | 2017-06-22 | Siltronic Ag | Verfahren zum epitaktischen beschichten von halbleiterscheiben und halbleiterscheibe |
Also Published As
Publication number | Publication date |
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TWI692557B (zh) | 2020-05-01 |
DE102018200415A1 (de) | 2019-07-11 |
SG11202006496WA (en) | 2020-08-28 |
IL275870A (en) | 2020-10-29 |
US11482597B2 (en) | 2022-10-25 |
EP3738138A1 (de) | 2020-11-18 |
KR20200097348A (ko) | 2020-08-18 |
KR102416913B1 (ko) | 2022-07-05 |
CN111602226B (zh) | 2023-10-24 |
US20210376088A1 (en) | 2021-12-02 |
JP6996001B2 (ja) | 2022-01-17 |
WO2019137728A1 (de) | 2019-07-18 |
TW201938852A (zh) | 2019-10-01 |
JP2021510459A (ja) | 2021-04-22 |
IL275870B1 (en) | 2024-04-01 |
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