CN111599817B - Method for manufacturing three-dimensional memory - Google Patents
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- CN111599817B CN111599817B CN202010478359.5A CN202010478359A CN111599817B CN 111599817 B CN111599817 B CN 111599817B CN 202010478359 A CN202010478359 A CN 202010478359A CN 111599817 B CN111599817 B CN 111599817B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a manufacturing method of a three-dimensional memory. The manufacturing method comprises the following steps: providing a first substrate with a memory array, wherein an insulating medium layer and an etching stop layer positioned in the insulating medium layer are formed on one side of the first substrate with the memory array; forming a first through hole penetrating to the etching stop layer in the insulating medium layer; removing the etching stop layer, and forming a first conductive channel in the first through hole and the area where the etching stop layer is removed; providing a second substrate with CMOS circuits, and bonding the CMOS circuits with the memory array of the first substrate; through contacts are formed through the first substrate from a side remote from the memory array and connected to the first conductive vias. By adopting the manufacturing method, the through contact is not required to be completely wrapped on the end part of the conductive channel by adjusting the size of the through contact in the back winding process, the electric leakage between the conductive channel and the substrate can be effectively prevented, and the process difficulty is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a three-dimensional memory.
Background
As the demand for integration and storage capacity continues to increase, 3D NAND memories have come into play. The 3D NAND memory greatly saves the area of a silicon chip, reduces the manufacturing cost and increases the storage capacity.
In the 3D NAND memory structure, a stacked 3D NAND memory structure is implemented by vertically stacking multiple layers of data storage units, however, other circuits such as a decoder (decoder), a page buffer (page buffer), a latch (latch), and the like are all formed by CMOS devices, and the processes of the CMOS devices cannot be integrated with the 3D NAND devices. In the current process, a wafer with a 3D NAND memory array and a wafer with peripheral circuits are formed separately and then bonded together by a bonding technique, and the wire wrapping of the back side of the silicon wafer is achieved by a TSC technique, which is a vertical electrical connection completely through the silicon wafer by directly forming contact points (commonly referred to as through-silicon contacts) through the silicon wafer to electrically connect with contact points of bonded CMOS devices through conductive vias, thereby providing interconnection of vertically aligned devices through internal wiring that significantly reduces chip complexity and overall size, which can provide higher device interconnection density and shorter device interconnection length than conventional packaging techniques.
In an actual process, the end portion of the through silicon contact needs to completely wrap the end portion of the conductive channel connected with the CMOS device, and an isolation layer with a certain thickness needs to be formed outside the through silicon contact, so as to prevent leakage (leakage) by isolating the through silicon contact from the substrate, which results in that the cross-sectional dimension of the end portion of the through silicon contact needs to be larger than that of the end portion of the conductive channel. However, in order to form the through silicon contact, a through contact hole needs to be formed in the substrate, and a post-etching treatment (PET) process is usually performed after the through contact hole, so as to ensure the loss of the silicon substrate in the etching process of the conductive channel, the selection ratio of the process to silicon is high, which may cause the cross-sectional dimension of the end portion of the conductive channel to be enlarged by 30-50 nm, thereby causing the cross-sectional dimension of the end portion of the through silicon contact to need to be adjusted in the subsequent process of realizing the wire winding on the back surface of the silicon wafer through the TSC technology, and increasing the process difficulty.
Disclosure of Invention
The invention mainly aims to provide a method for manufacturing a three-dimensional memory, which aims to solve the problem that the process difficulty is increased due to the fact that the size of a cross section penetrating through the end part of a silicon contact needs to be adjusted in the process of winding the back of a silicon wafer in the prior art.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for fabricating a three-dimensional memory, including the steps of: providing a first substrate with a memory array, wherein an insulating medium layer and an etching stop layer positioned in the insulating medium layer are formed on one side of the first substrate with the memory array; forming a first through hole penetrating to the etching stop layer in the insulating medium layer; removing the etching stop layer, and forming a first conductive channel in the first through hole and the area where the etching stop layer is removed; providing a second substrate with CMOS circuits, and bonding the CMOS circuits with the memory array of the first substrate; through contacts are formed through the first substrate from a side remote from the memory array and connected to the first conductive vias.
Further, an insulating material is deposited on the first substrate to form an insulating medium layer, and an etching stop layer is formed in the process of depositing the insulating material.
Further, the memory array comprises a core storage area and a step area, the step area is provided with a step structure connected with the core storage area, and an etching stop layer is formed on one side of the step structure far away from the core storage area.
Further, the step of forming the insulating dielectric layer and the etching stop layer includes: forming a stacking structure on the first substrate, wherein the stacking structure comprises a grid structure and inter-grid dielectric layers, and the grid structure and the inter-grid dielectric layers are alternately stacked along the direction far away from the first substrate; etching the grid structure and the dielectric layer between the grids to form a step structure at one end of the stacked structure; and depositing an insulating material on the first substrate to form an insulating dielectric layer, and forming an etching stop layer in the process of depositing the insulating material.
Further, the projection area of the first through hole on the etching stop layer is smaller than the cross-sectional area of the etching stop layer.
Further, the step of forming the first via hole includes: forming a first contact layer covering the insulating medium layer on the first substrate; and sequentially etching the first contact layer and the insulating medium layer to form a first contact hole in the first contact layer and form a first through hole penetrating to the etching stop layer in the insulating medium layer, wherein the first through hole is communicated with the first contact hole.
Further, after the step of removing the etch stop layer, a first conductive channel is formed in the first via hole and the region where the etch stop layer is removed, and a first contact point connected to the first conductive channel is formed in the first contact hole.
Further, in the step of etching the first contact layer and the insulating medium layer, a second contact hole is formed in the first contact layer, and a second through hole penetrating to the step structure is formed in the insulating medium layer so as to communicate the second through hole with the second contact hole, and before the step of bonding the CMOS circuit with the memory array, the manufacturing method further includes: a second conductive via is formed in the second via hole, and a second contact point connected to the second conductive via is formed in the second contact hole.
Further, the step of bonding the CMOS circuitry to the memory array comprises: forming a second contact layer covering the CMOS circuit on the second substrate; forming an interconnection contact hole penetrating to the CMOS circuit in the second contact layer; forming an interconnection contact point in the interconnection contact hole to connect the interconnection contact point with the CMOS circuit; the interconnect contacts are bonded to the first and second contacts, respectively.
Further, the step of forming the through contact includes: forming a third contact hole penetrating through the first substrate and connected to the first conductive via; forming an isolation layer covering the side wall of the third contact hole; and forming a through contact in the third contact hole so that the isolation layer wraps the through contact.
Further, the first conductive channel has a conductive surface in contact with the through contact, and a projected area of the through contact on the conductive surface is smaller than an area of the conductive surface.
Further, the material of the etching stop layer comprises silicon nitride.
The technical scheme of the invention is applied, and provides a manufacturing method of a three-dimensional memory, which comprises the steps of simultaneously forming an etching stop layer in the process of forming a memory array, then covering an insulating medium layer on the etching stop layer, forming a first through hole penetrating to the etching stop layer in the insulating medium layer, forming a first conductive channel in the area of the first through hole and the etching stop layer after removing the etching stop layer, forming a penetrating contact connected with the first conductive channel after bonding a CMOS circuit and the memory array, so that the end part of the conductive channel can be isolated through a part of the insulating medium layer by forming the etching stop layer first, then removing the etching stop layer and forming the end part of the conductive channel in the etching stop layer, further realizing the complete wrapping of the end part of the conductive channel by the penetrating contact without adjusting the size of the penetrating contact in the back winding process, the electric leakage between the conductive channel and the substrate can be effectively prevented, and the process difficulty is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram of a substrate after an insulating dielectric layer is covered on a surface of a first substrate having a step region and a core storage region in a method for manufacturing a three-dimensional memory provided in an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of the substrate after forming a first via through the insulating dielectric layer shown in FIG. 1 to an etch stop layer;
FIG. 3 is a schematic cross-sectional view of the substrate after removing the etch stop layer shown in FIG. 2;
FIG. 4 is a schematic cross-sectional view of the substrate after forming a first conductive via in the first via and etch stop layer removal region shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view of the base shown in FIG. 4 after the base has been inverted;
FIG. 6 is a schematic cross-sectional view of the body after forming a third contact hole through the first substrate shown in FIG. 5 and connected to the first conductive via;
fig. 7 is a schematic cross-sectional view of the substrate after forming a through contact in the first contact hole shown in fig. 6.
Wherein the figures include the following reference numerals:
10. a first substrate; 20. etching the stop layer; 30. an insulating dielectric layer; 40. a first through hole; 50. a first conductive path; 60. a third contact hole; 70. a through contact; 80. an isolation layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background section, in the actual manufacturing process of the TSC technology, the end of the through silicon contact needs to completely wrap the end of the conductive channel connected to the CMOS device, and an isolation layer needs to be formed to a certain thickness outside the through silicon contact, which results in the cross-sectional dimension of the end of the through silicon contact needing to be larger than the cross-sectional dimension of the end of the conductive channel by isolating the through silicon contact from the substrate to prevent leakage. However, in order to form the through silicon contact, a through contact hole needs to be formed in the substrate, and a post-etching treatment process is usually performed after the through contact hole, which may cause the cross-sectional size of the end portion of the conductive channel to be enlarged by 30-50 nm, so that the cross-sectional size of the end portion of the through silicon contact needs to be adjusted in a subsequent process of realizing wire winding on the back surface of a silicon wafer by the TSC technology, and the process difficulty is increased.
The inventor of the present invention has made a study in view of the above problems, and proposes a method for manufacturing a three-dimensional memory, including the steps of: providing a first substrate 10 with a memory array, wherein an insulating medium layer 30 and an etching stop layer 20 positioned in the insulating medium layer 30 are formed on one side of the first substrate 10 with the memory array; forming a first through hole 40 penetrating to the etch stop layer 20 in the insulating dielectric layer 30; removing the etch stop layer 20 and forming a first conductive via 50 in the first via 40 and the region where the etch stop layer 20 is removed; providing a second substrate having CMOS circuitry, bonding the CMOS circuitry to the memory array of the first substrate 10; through contacts are formed through the first substrate 10 from a side remote from the memory array and connected to the first conductive vias 50.
According to the manufacturing method, an etching stop layer is formed simultaneously in the process of forming the memory array, then a first through hole penetrating to the etching stop layer is formed, a first conductive channel is formed in the first through hole and the area where the etching stop layer is removed after the etching stop layer is removed, a penetrating contact connected with the first conductive channel is formed after the CMOS circuit and the memory array are bonded, and therefore the etching stop layer is formed firstly, then the etching stop layer is removed, and the end part of the conductive channel is formed in the etching stop layer, the end part of the conductive channel and the substrate can be isolated through a part of insulating medium layer 30, further the penetrating contact is completely wrapped on the end part of the conductive channel in the back winding process without adjusting the size of the penetrating contact, electric leakage between the conductive channel and the substrate can be effectively prevented, and the process difficulty is reduced.
An exemplary embodiment of a method for fabricating a three-dimensional memory according to the present invention will be described in more detail with reference to fig. 1 to 7. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a first substrate 10 with a memory array is provided, and an insulating dielectric layer and an etching stop layer 20 located in the insulating dielectric layer 30 are formed on one side of the first substrate 10 with the memory array, as shown in fig. 1.
In a preferred embodiment, an insulating material is deposited on the first substrate 10 to form the insulating dielectric layer 30, and the etch stop layer 20 is formed during the deposition of the insulating material.
The memory array may include a core storage region and a step region having a step structure connected to the core storage region, the step region having the etch stop layer 20 on a side of the step structure remote from the core storage region. At this time, a stacked structure is formed on the first substrate 10, the stacked structure includes a gate structure and inter-gate dielectric layers, and the gate structure and the inter-gate dielectric layers are alternately stacked along a direction away from the first substrate 10; etching the grid structure and the dielectric layer between the grids to form a step structure at one end of the stacked structure; an insulating material is deposited on the first substrate 10 to form an insulating dielectric layer 30, and an etch stop layer 20 is formed during the deposition of the insulating material.
The material of the substrate may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
The gate material forming the gate structure is usually metal, and may be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni; the material for forming the inter-gate dielectric layer can be SiO2But not limited to the above categories, those skilled in the art can also reasonably select the categories of the gate structure and the inter-gate dielectric layer according to the prior art.
The etching stop layer 20 is formed during the process of depositing the insulating material, specifically, a portion of the insulating material may be deposited on the first substrate 10 to a position where the etching stop layer 20 is to be formed, and then the insulating material may be deposited to cover the etching stop layer 20 after the etching stop layer 20 is formed, the insulating material deposited twice forms the insulating dielectric layer 30, and the etching stop layer 20 is located in the insulating dielectric layer 30, as shown in fig. 1.
The material of the etch stop layer 20 may be chosen appropriately by those skilled in the art, and the material of the etch stop layer 20 may be silicon nitride.
After the step of forming the etch stop layer 20, an insulating dielectric layer 30 is covered on the surface of the first substrate 10 having the stepped region and the core storage region, and a first via hole 40 penetrating to the etch stop layer 20 is formed in the insulating dielectric layer 30, as shown in fig. 2.
The first via 40 formed in the insulating dielectric layer 30 does not need to have a large cross-sectional size as long as it can ensure a proper contact area with the etch stop layer 20, and preferably, the projected area of the first via 40 on the etch stop layer 20 is smaller than the cross-sectional area of the etch stop layer 20, as shown in fig. 2.
In order to achieve good bonding with CMOS circuitry in subsequent processes, in a preferred embodiment, the step of forming the first via 40 includes: forming a first contact layer covering the insulating dielectric layer 30 on the first substrate 10; the first contact layer and the insulating dielectric layer 30 are sequentially etched to form a first contact hole in the first contact layer, and a first via hole 40 penetrating to the etch stop layer 20 is formed in the insulating dielectric layer 30, the first via hole 40 communicating with the first contact hole.
After the step of removing the above-described etch stop layer 20, it is also possible to form a first conductive via 50 in the first via hole 40 and the region where the etch stop layer 20 is removed, and to form a first contact point connected to the first conductive via 50 in the first contact hole. The first contact point is used for subsequent bonding with the CMOS circuit.
After the step of forming the first via hole 40 penetrating to the etch stop layer 20 as described above, the etch stop layer 20 is removed, and a first conductive path 50 is formed in the first via hole 40 and the region where the etch stop layer 20 is removed, as shown in fig. 3 and 4.
The etch stop layer 20 may be removed by an etch process conventional in the art, such as a hot phosphoric acid process, by one skilled in the art. Also, the first conductive via 50 may be formed by a deposition process that is conventional in the art, and the material of the first conductive via 50 includes, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, or any combination thereof.
In the step of etching the first contact layer and the insulating medium layer 30, a second contact hole is formed in the first contact layer, and a second through hole penetrating to the step structure is formed in the insulating medium layer 30, so that the second through hole is communicated with the second contact hole, and preferably, before the CMOS circuit is bonded to the memory array of the first substrate 10, the manufacturing method of the present invention further includes: a second conductive via is formed in the second via hole, and a second contact point connected to the second conductive via is formed in the second contact hole. The second contact point and the first contact point are jointly used for subsequent bonding with the CMOS circuit.
After the step of forming the first conductive vias 50 described above, a second substrate having CMOS circuitry is provided and the CMOS circuitry is bonded to the memory array of the first substrate 10.
In a preferred embodiment, the bonding step includes: forming a second contact layer covering the CMOS circuit on the second substrate; forming an interconnection contact hole penetrating to the CMOS circuit in the second contact layer; forming an interconnection contact point in the interconnection contact hole to connect the interconnection contact point with the CMOS circuit; the interconnect contacts are bonded to the first contact and the second contact, respectively, and the CMOS circuit is connected to the first conductive via 50 and the step structure of the memory array through the interconnect contacts, the first contact, and the second contact, respectively.
The first substrate 10 may be back thinned prior to bonding the CMOS circuitry of the second substrate to the memory array of the first substrate 10. The first substrate 10 may be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other process, or any combination thereof.
After the step of bonding the CMOS circuitry to the memory array, through contacts 70 are formed through the first substrate 10 and connected to the first conductive vias 50 from a side remote from the memory array, as shown in fig. 5-7.
In a preferred embodiment, the step of forming the through contact 70 includes: forming a third contact hole 60 penetrating the first substrate 10 and connected to the first conductive via 50, as shown in fig. 6; forming an isolation layer 80 covering sidewalls of the third contact hole 60; the through contact 70 is formed in the third contact hole 60 such that the isolation layer 80 wraps around the through contact 70, as shown in fig. 7.
In the above preferred embodiment, it is preferable that the first conductive path 50 has a conductive surface contacting the through contact 70, and a projected area of the through contact 70 on the conductive surface is smaller than an area of the conductive surface.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
according to the manufacturing method, the etching stop layer is formed firstly, then the etching stop layer is removed, and the end part of the conductive channel is formed in the etching stop layer, so that the end part of the conductive channel can be isolated from the substrate through a part of insulating medium layer, the end part of the conductive channel is completely wrapped by the through contact without adjusting the size of the through contact in the back winding process, the electric leakage between the conductive channel and the substrate can be effectively prevented, and the process difficulty is reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
providing a first substrate with a memory array, wherein an insulating medium layer and an etching stop layer positioned in the insulating medium layer are formed on one side of the first substrate with the memory array;
forming a first through hole penetrating to the etching stop layer in the insulating medium layer;
removing the etching stop layer, and forming a first conductive channel in the first through hole and the area where the etching stop layer is removed;
providing a second substrate having CMOS circuitry, bonding the CMOS circuitry to the memory array of the first substrate;
through contacts are formed through the first substrate from a side remote from the memory array and connected with the first conductive vias.
2. The method of claim 1, wherein an insulating material is deposited on the first substrate to form the insulating dielectric layer, and wherein the etch stop layer is formed during the deposition of the insulating material.
3. A method according to claim 1 or 2, wherein the memory array comprises a core storage region and a step region, the step region has a step structure connected to the core storage region, and the etching stop layer is formed on a side of the step structure away from the core storage region.
4. The method of claim 3, wherein the step of forming the insulating dielectric layer and the etch stop layer comprises:
forming a stacked structure on the first substrate, wherein the stacked structure comprises a grid structure and inter-grid dielectric layers, and the grid structure and the inter-grid dielectric layers are alternately stacked along the direction far away from the first substrate;
etching the grid structure and the dielectric layer between the grids to form the step structure at one end of the stacked structure;
and depositing an insulating material on the first substrate to form the insulating medium layer, and forming the etching stop layer in the process of depositing the insulating material.
5. The method according to claim 1, wherein a projected area of the first via hole on the etch stop layer is smaller than a cross-sectional area of the etch stop layer.
6. The method of manufacturing according to claim 3, wherein the step of forming the first via hole includes:
forming a first contact layer covering the insulating medium layer on the first substrate;
and sequentially etching the first contact layer and the insulating medium layer to form a first contact hole in the first contact layer and form a first through hole penetrating to the etching stop layer in the insulating medium layer, wherein the first through hole is communicated with the first contact hole.
7. The method of manufacturing according to claim 6, wherein after the step of removing the etch stop layer, the first conductive channel is formed in the first via hole and a region where the etch stop layer is removed, and a first contact point connected to the first conductive channel is formed in the first contact hole.
8. The method of claim 7, wherein in the step of etching the first contact layer and the insulating dielectric layer, forming a second contact hole in the first contact layer and forming a second via hole in the insulating dielectric layer penetrating to the step structure to communicate the second via hole with the second contact hole, the method further comprising, prior to the step of bonding the CMOS circuitry to the memory array:
forming a second conductive via in the second via hole, and forming a second contact point connected to the second conductive via in the second contact hole.
9. The method of claim 8, wherein the step of bonding the CMOS circuitry to the memory array comprises:
forming a second contact layer covering the CMOS circuit on the second substrate;
forming an interconnection contact hole penetrating to the CMOS circuit in the second contact layer;
forming an interconnection contact point in the interconnection contact hole to connect the interconnection contact point with the CMOS circuit;
bonding the interconnect contacts to the first and second contact points, respectively.
10. The method of manufacturing according to claim 1, wherein the step of forming the through contact includes:
forming a third contact hole penetrating through the first substrate and connected with the first conductive channel;
forming an isolation layer covering the side wall of the third contact hole;
forming the through contact in the third contact hole such that the isolation layer wraps the through contact.
11. The method of manufacturing according to claim 10, wherein the first conductive via has a conductive surface in contact with the through contact, the conductive surface is an entire plane of the first conductive via, and a projected area of the through contact on the conductive surface is smaller than an area of the conductive surface.
12. A method according to claim 1 or 2, wherein the material of the etch stop layer comprises silicon nitride.
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