CN111584637A - FDSOI (fully-drawn silicon on insulator) -based PIN (personal identification number) structure and manufacturing method thereof - Google Patents

FDSOI (fully-drawn silicon on insulator) -based PIN (personal identification number) structure and manufacturing method thereof Download PDF

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CN111584637A
CN111584637A CN202010466299.5A CN202010466299A CN111584637A CN 111584637 A CN111584637 A CN 111584637A CN 202010466299 A CN202010466299 A CN 202010466299A CN 111584637 A CN111584637 A CN 111584637A
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sti
forming
type substrate
gate structure
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CN111584637B (en
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徐翠芹
田明
汪雪娇
刘巍
景旭斌
廖端泉
王昌锋
张瑜
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention provides a PIN structure based on FDSOI and a manufacturing method thereof, wherein the PIN structure is positioned on a buried oxide layer of a shallow region of a P-type substrate; the region of the P-type substrate above the buried oxide layer is a channel region; a gate structure located over the channel region; the first P + region and the N + region are respectively positioned at two sides of the grid structure; the first STI region and the second STI region pass through the edge of the buried oxide layer from the surface of the channel region and extend to the depth of the P-type substrate, and the first STI region is positioned at the edge of one side of the first P + region, which is far away from the grid electrode; the second STI region is positioned at the edge of one side of the N + far away from the grid electrode. According to the invention, the N + region on one side of the grid electrode in the traditional PIN structure is replaced by the P + region, so that the interface state and energy state distribution between the channel region and the grid electrode are effectively extracted, and the defect that the interface state, i.e. energy state distribution cannot be extracted by the conventional PIN is overcome; meanwhile, the P + region and the N + region on two sides of the grid are manufactured by using a photomask, and the boundary of the P + region and the N + region is arranged above the grid, so that a photoetching process window can be enlarged.

Description

FDSOI (fully-drawn silicon on insulator) -based PIN (personal identification number) structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a PIN structure based on FDSOI and a manufacturing method thereof.
Background
Charge pumps (Charge pumping) are commonly used in bulk silicon processes to extract interface states and can extract the energy level distribution of the interface. But for FDSOI devices the channel is undoped and is separated from the substrate by a buried oxide layer (BOX). Therefore, carriers in channel inversion can only be from the source and drain, and an accumulation region cannot be formed. Therefore, conventional NFET/PFET structures cannot extract and evaluate interface states and their energy state distributions by charge pumping.
Therefore, a new PIN structure and a method for fabricating the same are needed to solve the above problems.
Disclosure of Invention
In view of the above-described shortcomings of the prior art, it is an object of the present invention to provide an FDSOI-based PIN structure for solving the problem of the prior art in that the interface states and their energy state distributions cannot be extracted and evaluated by a charge pump due to the conventional NFET/PFET.
In order to achieve the above objects and other related objects, the present invention provides a PIN structure based on FDSOI, which at least includes a P-type substrate, a buried oxide layer located in a shallow region of the P-type substrate; the region of the P-type substrate above the buried oxide layer is a channel region; a gate structure located over the channel region; the first P + region and the N + region are respectively positioned at two sides of the grid structure; the first STI region and the second STI region pass through the edge of the buried oxide layer from the surface of the channel region and extend to the depth of the P-type substrate, and the first STI region is positioned at the edge of one side of the first P + region, which is far away from the grid electrode; the second STI region is positioned at the edge of one side of the N + far away from the grid electrode.
Preferably, the gate structure comprises an oxide layer located on the channel region; a polysilicon structure located on the oxide layer; and side walls cover the oxide layer, the side walls of the polycrystalline silicon structure and the top of the polycrystalline silicon structure.
Preferably, the PIN structure further comprises: and the third STI region extends from the surface of the P-type substrate to the deep part of the P-type substrate and is mutually spaced from the first STI region, the third STI region is positioned on one side of the first STI region, which is far away from the second STI region, and a second P + region is arranged on the surface region of the P-type substrate between the first STI region and the third STI region.
The invention also provides a manufacturing method of the FDSOI-based PIN structure, which at least comprises the following steps:
providing a P-type substrate, and forming a first STI region and a second STI region on the P-type substrate;
step two, forming a buried oxide layer in a shallow region of the P-type substrate between the first STI region and the second STI region; the region of the P-type substrate above the buried oxide layer is a channel region;
step three, forming a grid structure on the channel region;
fourthly, forming a first P + region and an N + region on the channel regions on two sides of the grid structure respectively; the first P + region is located on the channel region between the first STI region and the gate structure and the first P + region is away from an edge of the gate structure along an edge of the first STI region; the N + region is located on the channel region between the second STI region and the gate structure and the N + region is along an edge of the second STI region away from an edge of the gate structure.
Preferably, in the first step, while the first and second STI regions are formed on the P-type substrate, a third STI region is formed on the P-type substrate on a side of the first STI region away from the second STI region, where the third STI region is spaced apart from the first STI region.
Preferably, in the fourth step, while forming the first P + region and the N + region on the channel regions on both sides of the gate structure, a second P + region is formed in the P-type substrate surface region between the third STI region and the first STI region.
Preferably, the method for forming the first P + region and the N + region in the fourth step at least comprises: (1) suspending and coating photoresist; (2) exposing by using a photomask for forming the first P + region and the N + region, and orthographically projecting the boundary of a mask pattern for forming the first P + region and the N + region on the photomask on the gate structure during exposure; (3) developing after exposure to form a first photoresist pattern between the first STI region and the gate structure and a second photoresist pattern between the second STI region and the gate structure; (4) carrying out P-type heavy doping according to the first photoresist pattern to form a first P + region; and carrying out N-type heavy doping according to the second photoresist pattern to form the N + region.
Preferably, the method for forming the first P + region and the N + region in the fourth step at least comprises: (a) suspending and coating photoresist; (b) exposing by using a photomask for forming the first P + region, the second P + region and the N + region, and orthographically projecting the boundary of a mask pattern for forming the first P + region and the N + region on the photomask on the gate structure during exposure; orthographically projecting a mask pattern for forming the second P + region to a region between the first and third STI regions; (c) developing after exposure to form a first photoresist pattern between the first STI region and the gate structure; forming a second photoresist pattern between the second STI region and the gate structure, and forming a third photoresist pattern between the first and third STI regions; (d) carrying out P-type heavy doping according to the first photoresist pattern to form a first P + region; carrying out N-type heavy doping according to the second photoresist pattern to form the N + region; and carrying out P-type heavy doping according to the third photoresist pattern to form the second P + region.
Preferably, the boundary between the mask patterns for forming the first P + region and the N + region in step (2) is orthographically projected to a central position on the gate structure.
Preferably, the boundary between the mask patterns for forming the first P + region and the N + region in step (b) is orthographically projected to a central position on the gate structure.
Preferably, the method for forming the gate structure in step three comprises: (01) forming an oxide layer on the channel region; (02) forming a layer of polysilicon on the oxide layer; (03) etching the polycrystalline silicon and the oxide layer to form a grid; (04) and covering a layer of side wall on the top and the side wall of the grid to form the grid structure.
As described above, the FDSOI-based PIN structure and the method for manufacturing the same according to the present invention have the following advantageous effects: according to the invention, the N + region on one side of the grid electrode in the traditional PIN structure is replaced by the P + region, so that the interface state and energy band distribution between the channel region and the grid electrode can be effectively extracted, and the defect that the interface state and energy band distribution cannot be extracted by a conventional NFET or PFET through a charge pump is overcome; meanwhile, a photomask for manufacturing the P + region and the N + region on two sides of the grid is used, the junction of the P + region and the N + region is arranged above the grid, and grid polycrystalline silicon or a side wall of the grid polycrystalline silicon is used as a blocking layer for injecting N-type heavy doping and P-type heavy doping, so that a photoetching process window can be enlarged.
Drawings
FIG. 1 is a schematic cross-sectional view of a PIN structure according to the present invention;
FIG. 2 is a schematic diagram illustrating a top view of a PIN structure according to the present invention;
figure 3 shows a schematic cross-sectional view of a four port structure for a PIN structure of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The present invention provides a PIN structure based on FDSOI, as shown in fig. 1, fig. 1 is a schematic cross-sectional structure of the PIN structure of the present invention. The PIN structure of the present invention at least includes: a P-type Substrate (P-Substrate), a buried oxide layer (BOX) located in a shallow region of the P-type Substrate, namely the buried oxide layer is formed at a shallow surface of the P-type Substrate, and the P-type Substrate is also present in the shallow region of the P-type Substrate; the region of the P-type substrate above the buried oxide layer is a channel region 04; a gate structure 02 located on the channel region 04; further, the gate structure 02 includes an oxide layer on the channel region; a polysilicon structure located on the oxide layer; and side walls cover the oxide layer, the side walls of the polycrystalline silicon structure and the top of the polycrystalline silicon structure.
The PIN structure further comprises a first P + region 01 and an N + region 03 which are respectively positioned on two sides of the gate structure 02; a first STI region 001 and a second STI region 002 which pass through the edge of the buried oxide layer from the surface of the channel region 04 and extend to the depth of the P-type substrate, wherein the first STI region 001 is positioned at the edge of the first P + region 01 far away from the gate; the second STI region 002 is located at the edge of the N +03 side away from the gate.
The present embodiment further provides a method for manufacturing the FDSOI-based PIN structure, which at least includes the following steps:
providing a P-type substrate, and forming a first STI region 001 and a second STI region 002 on the P-type substrate, wherein the two STI regions are used for isolating active region devices;
step two, forming a buried oxide layer (BOX) in a shallow region of the P-type substrate between the first STI region and the second STI region; the region of the P-type substrate above the buried oxide layer is a channel region 04;
step three, forming a gate structure 02 on the channel region; further, in this embodiment, the method for forming the gate structure 02 in step three includes: (01) forming an oxide layer on the channel region; (02) forming a layer of polysilicon on the oxide layer; (03) etching the polycrystalline silicon and the oxide layer to form a grid; (04) and covering a layer of side wall on the top and the side wall of the grid to form the grid structure.
Step four, forming a first P + region 01 and an N + region 03 on the channel regions on two sides of the gate structure 02 respectively; the first P + region 01 is located on the channel region between the first STI region and the gate structure and the first P + region 01 is away from the edge of the gate structure along the edge of the first STI region 001; the N + region 03 is located on the channel region 04 between the second STI region 002 and the gate structure 02 and the N + region 03 is located along the edge of the second STI region 002 away from the edge of the gate structure 02.
Further, the method for forming the first P + region 01 and the N + region 03 in the fourth step at least includes: (1) suspending and coating photoresist; (2) exposing by using a photomask for forming the first P + region and the N + region, and orthographically projecting the boundary of a mask pattern for forming the first P + region and the N + region on the photomask on the gate structure during exposure; as shown in fig. 2, fig. 2 is a schematic top view of the PIN structure of the present invention. Further, in the step (2), the boundary between the mask patterns for forming the first P + region 01 and the N + region 03 is orthographically projected to the central position on the gate structure.
(3) After exposure, developing to form a first photoresist pattern A between the first STI region 001 and the gate structure 02 and a second photoresist pattern B between the second STI region 002 and the gate structure; (4) carrying out P-type heavy doping according to the first photoresist pattern to form a first P + region 01; and carrying out N-type heavy doping according to the second photoresist pattern to form the N + region 03.
In the embodiment, the N + region on one side of the gate in the conventional PIN structure is replaced by the P + region, so that the interface state and the energy band distribution between the channel region and the gate can be effectively extracted, and the defect that the interface state and the energy band distribution cannot be extracted by a conventional NFET or PFET through a charge pump is overcome; meanwhile, a photomask for manufacturing the P + region and the N + region on two sides of the grid is used, the junction of the P + region and the N + region is arranged above the grid, and grid polycrystalline silicon or a side wall of the grid polycrystalline silicon is used as a blocking layer for injecting N-type heavy doping and P-type heavy doping, so that a photoetching process window can be enlarged.
Example two
Another FDSOI-based PIN structure is provided in the present invention as shown in fig. 3, where fig. 3 is a cross-sectional schematic diagram of a four-port structure of the PIN structure of the present invention. The PIN structure of the present invention at least includes: a P-type Substrate (P-Substrate), a buried oxide layer (BOX) located in a shallow region of the P-type Substrate, namely the buried oxide layer is formed at a shallow surface of the P-type Substrate, and the P-type Substrate is also present in the shallow region of the P-type Substrate; the region of the P-type substrate above the buried oxide layer is a channel region 04; a gate structure 02 located on the channel region 04; further, the gate structure 02 includes an oxide layer on the channel region; a polysilicon structure located on the oxide layer; and side walls cover the oxide layer, the side walls of the polycrystalline silicon structure and the top of the polycrystalline silicon structure.
The PIN structure further comprises a first P + region 01 and an N + region 03 which are respectively positioned on two sides of the gate structure 02; a first STI region 001 and a second STI region 002 which pass through the edge of the buried oxide layer from the surface of the channel region 04 and extend to the depth of the P-type substrate, wherein the first STI region 001 is positioned at the edge of the first P + region 01 far away from the gate; the second STI region 002 is located at the edge of the N +03 side away from the gate.
As shown in fig. 3, the PIN structure further includes: and a third STI region 003 which extends from the surface of the P-type substrate to the deep part of the P-type substrate and is spaced from the first STI region 001, wherein the third STI region 003 is positioned on one side of the first STI region 001 away from the second STI region 002, and a second P + region 05 is arranged on the surface area of the P-type substrate between the first STI region 001 and the third STI region 003. In the four ports of the PIN structure, the P-type substrate can be realized by a non-SOI region, i.e., the P-type substrate is led out by the second P + region 05.
The present embodiment further provides a method for manufacturing the FDSOI-based PIN structure, which at least includes the following steps:
providing a P-type substrate, and forming a first STI region 001 and a second STI region 002 on the P-type substrate, wherein the two STI regions are used for isolating active region devices; further, in the first step, while the first and second STI regions are formed on the P-type substrate, a third STI region 003 is formed on the P-type substrate on a side of the first STI region away from the second STI region, where the third STI region 003 is spaced apart from the first STI region 001.
Step two, forming a buried oxide layer (BOX) in a shallow region of the P-type substrate between the first STI region and the second STI region; the region of the P-type substrate above the buried oxide layer is a channel region 04;
step three, forming a gate structure 02 on the channel region; further, in this embodiment, the method for forming the gate structure 02 in step three includes: (01) forming an oxide layer on the channel region; (02) forming a layer of polysilicon on the oxide layer; (03) etching the polycrystalline silicon and the oxide layer to form a grid; (04) and covering a layer of side wall on the top and the side wall of the grid to form the grid structure.
Step four, forming a first P + region 01 and an N + region 03 on the channel regions on two sides of the gate structure 02 respectively; the first P + region 01 is located on the channel region 04 between the first STI region 001 and the gate structure 02 and the first P + region 01 is away from the edge of the gate structure along the edge of the first STI region 001; the N + region 03 is located on the channel region 04 between the second STI region 002 and the gate structure 02 and the N + region 03 is located along the edge of the second STI region 002 away from the edge of the gate structure 02. Further, in the fourth step, while forming the first P + region 01 and the N + region 03 on the channel regions on both sides of the gate structure, the second P + region 05 is formed in the P-type substrate surface region between the third STI region 003 and the first STI region 001.
In the fourth step of the present embodiment, the method for forming the first P + region 01 and the N + region 03 at least includes: (a) suspending and coating photoresist; (b) exposing by using a photomask for forming the first P + region 01, the second P + region 05 and the N + region 03, and orthographically projecting the boundary of a mask pattern for forming the first P + region 01 and the N + region 03 on the gate structure during exposure; orthographically projecting a mask pattern for forming the second P + region 05 to a region between the first and third STI regions; further, as shown in fig. 2, the boundary between the mask pattern for forming the first P + region and the mask pattern for forming the N + region in the step (b) is orthographically projected to the central position on the gate structure. (c) Developing after exposure to form a first photoresist pattern A between the first STI region and the gate structure; forming a second photoresist pattern B between the second STI region and the gate structure, and forming a third photoresist pattern between the first and third STI regions (third photoresist pattern not shown in fig. 2); (d) carrying out P-type heavy doping according to the first photoresist pattern A to form a first P + region 01; carrying out N-type heavy doping according to the second photoresist pattern B to form the N + region 03; and carrying out P-type heavy doping according to the third photoresist pattern to form the second P + region 05.
In summary, the N + region on one side of the gate in the conventional PIN structure is replaced by the P + region, so that the interface state and the energy band distribution between the channel region and the gate can be effectively extracted, and the defect that the interface state, i.e. the energy band distribution cannot be extracted by a conventional NFET or PFET through a charge pump is overcome; meanwhile, a photomask for manufacturing the P + region and the N + region on two sides of the grid is used, the junction of the P + region and the N + region is arranged above the grid, and grid polycrystalline silicon or a side wall of the grid polycrystalline silicon is used as a blocking layer for injecting N-type heavy doping and P-type heavy doping, so that a photoetching process window can be enlarged. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. An FDSOI-based PIN structure comprising at least:
the P-type substrate and the buried oxide layer are positioned in the shallow region of the P-type substrate; the region of the P-type substrate above the buried oxide layer is a channel region; a gate structure located over the channel region; the first P + region and the N + region are respectively positioned at two sides of the grid structure; the first STI region and the second STI region pass through the edge of the buried oxide layer from the surface of the channel region and extend to the depth of the P-type substrate, and the first STI region is positioned at the edge of one side of the first P + region, which is far away from the grid electrode; the second STI region is positioned at the edge of one side of the N + far away from the grid electrode.
2. The FDSOI-based PIN structure as defined in claim 1 wherein: the gate structure comprises an oxide layer located on the channel region; a polysilicon structure located on the oxide layer; and side walls cover the oxide layer, the side walls of the polycrystalline silicon structure and the top of the polycrystalline silicon structure.
3. The FDSOI-based PIN structure as defined in claim 2 wherein: the PIN structure further comprises: and the third STI region extends from the surface of the P-type substrate to the deep part of the P-type substrate and is mutually spaced from the first STI region, the third STI region is positioned on one side of the first STI region, which is far away from the second STI region, and a second P + region is arranged on the surface region of the P-type substrate between the first STI region and the third STI region.
4. Method for fabricating an FDSOI-based PIN structure according to any of the claims 1 to 3 comprising at least the following steps:
providing a P-type substrate, and forming a first STI region and a second STI region on the P-type substrate;
step two, forming a buried oxide layer in a shallow region of the P-type substrate between the first STI region and the second STI region; the region of the P-type substrate above the buried oxide layer is a channel region;
step three, forming a grid structure on the channel region;
fourthly, forming a first P + region and an N + region on the channel regions on two sides of the grid structure respectively; the first P + region is located on the channel region between the first STI region and the gate structure and the first P + region is away from an edge of the gate structure along an edge of the first STI region; the N + region is located on the channel region between the second STI region and the gate structure and the N + region is along an edge of the second STI region away from an edge of the gate structure.
5. The method of fabricating an FDSOI-based PIN structure according to claim 4, wherein: in the first step, while the first and second STI regions are formed on the P-type substrate, a third STI region is formed on the P-type substrate on the side of the first STI region far away from the second STI region, and the third STI region is spaced from the first STI region.
6. The method of fabricating an FDSOI-based PIN structure as defined in claim 5 wherein: and step four, forming a first P + region and the N + region on the channel regions on two sides of the gate structure respectively, and forming a second P + region in the surface region of the P-type substrate between the third STI region and the first STI region.
7. The method of fabricating an FDSOI-based PIN structure according to claim 4, wherein: the method for forming the first P + region and the N + region in step four at least comprises: (1) suspending and coating photoresist; (2) exposing by using a photomask for forming the first P + region and the N + region, and orthographically projecting the boundary of a mask pattern for forming the first P + region and the N + region on the photomask on the gate structure during exposure; (3) developing after exposure to form a first photoresist pattern between the first STI region and the gate structure and a second photoresist pattern between the second STI region and the gate structure; (4) carrying out P-type heavy doping according to the first photoresist pattern to form a first P + region; and carrying out N-type heavy doping according to the second photoresist pattern to form the N + region.
8. The method of fabricating an FDSOI-based PIN structure as defined in claim 6 wherein: the method for forming the first P + region and the N + region in step four at least comprises: (a) suspending and coating photoresist; (b) exposing by using a photomask for forming the first P + region, the second P + region and the N + region, and orthographically projecting the boundary of a mask pattern for forming the first P + region and the N + region on the photomask on the gate structure during exposure; orthographically projecting a mask pattern for forming the second P + region to a region between the first and third STI regions; (c) developing after exposure to form a first photoresist pattern between the first STI region and the gate structure; forming a second photoresist pattern between the second STI region and the gate structure, and forming a third photoresist pattern between the first and third STI regions; (d) carrying out P-type heavy doping according to the first photoresist pattern to form a first P + region; carrying out N-type heavy doping according to the second photoresist pattern to form the N + region; and carrying out P-type heavy doping according to the third photoresist pattern to form the second P + region.
9. The method of fabricating an FDSOI-based PIN structure as defined in claim 7 wherein: and (3) orthographically projecting the boundary of the mask pattern used for forming the first P + region and the mask pattern used for forming the N + region in the step (2) to the central position on the gate structure.
10. The method of fabricating an FDSOI-based PIN structure as defined in claim 8 wherein: and (c) orthographically projecting the boundary of the mask pattern for forming the first P + region and the N + region in the step (b) to the central position on the gate structure.
11. The method of fabricating an FDSOI-based PIN structure according to claim 4, wherein: the method for forming the gate structure in the third step comprises the following steps: (01) forming an oxide layer on the channel region; (02) forming a layer of polysilicon on the oxide layer; (03) etching the polycrystalline silicon and the oxide layer to form a grid; (04) and covering a layer of side wall on the top and the side wall of the grid to form the grid structure.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040201063A1 (en) * 2003-04-10 2004-10-14 Koichi Fukuda Semiconductor device and method of fabricating same
CN101047193A (en) * 2006-03-31 2007-10-03 冲电气工业株式会社 Semiconductor storage device and method of fabrication thereof
CN101136347A (en) * 2007-09-29 2008-03-05 上海集成电路研发中心有限公司 MOS pipe interface state testing method
CN102446958A (en) * 2011-11-08 2012-05-09 上海华力微电子有限公司 Carbon silicon-germanium silicon heterojunction 1T-DRAM (Single Transistor Dynamic Random Access Memory) structure on insulator and forming method thereof
CN102709296A (en) * 2012-06-11 2012-10-03 中国电子科技集团公司第五十八研究所 Silicon-on-insulator (SOI)/metal oxide semiconductor (MOS) device structure for connecting negative voltage on backgate through negative charge pump and manufacturing method
US20140017856A1 (en) * 2012-07-13 2014-01-16 Stmicroelectronics Sa On-SOI integrated circuit comprising a subjacent protection transistor
CN106298564A (en) * 2015-05-19 2017-01-04 中芯国际集成电路制造(上海)有限公司 The measurement structure of a kind of FinFET interfacial state and measuring method, electronic installation
CN111145810A (en) * 2019-12-19 2020-05-12 华东师范大学 Static random access memory based on FDSOI device back gate structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040201063A1 (en) * 2003-04-10 2004-10-14 Koichi Fukuda Semiconductor device and method of fabricating same
CN101047193A (en) * 2006-03-31 2007-10-03 冲电气工业株式会社 Semiconductor storage device and method of fabrication thereof
CN101136347A (en) * 2007-09-29 2008-03-05 上海集成电路研发中心有限公司 MOS pipe interface state testing method
CN102446958A (en) * 2011-11-08 2012-05-09 上海华力微电子有限公司 Carbon silicon-germanium silicon heterojunction 1T-DRAM (Single Transistor Dynamic Random Access Memory) structure on insulator and forming method thereof
CN102709296A (en) * 2012-06-11 2012-10-03 中国电子科技集团公司第五十八研究所 Silicon-on-insulator (SOI)/metal oxide semiconductor (MOS) device structure for connecting negative voltage on backgate through negative charge pump and manufacturing method
US20140017856A1 (en) * 2012-07-13 2014-01-16 Stmicroelectronics Sa On-SOI integrated circuit comprising a subjacent protection transistor
CN106298564A (en) * 2015-05-19 2017-01-04 中芯国际集成电路制造(上海)有限公司 The measurement structure of a kind of FinFET interfacial state and measuring method, electronic installation
CN111145810A (en) * 2019-12-19 2020-05-12 华东师范大学 Static random access memory based on FDSOI device back gate structure

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