CN115064593A - Method for saving chip area - Google Patents
Method for saving chip area Download PDFInfo
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- CN115064593A CN115064593A CN202210745901.8A CN202210745901A CN115064593A CN 115064593 A CN115064593 A CN 115064593A CN 202210745901 A CN202210745901 A CN 202210745901A CN 115064593 A CN115064593 A CN 115064593A
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for saving chip area.A substrate is provided with different types of device areas, wherein the different types of device areas comprise a core NFET area, a core PFET area, an IO NFET area and an IO PFET area; grid electrodes are respectively formed on the substrates of the device areas of different types; covering the core NFET region, the core PFET region, the IO NFET region and the IO PFET region on the substrate with photoresist; providing a photomask, and exposing and developing the substrate by using the photomask to enable a core PFET region and an IO PFET region to be displayed; etching the substrate of the developed core PFET region and IO PFET region to form a trench for growing SiGe; SiGe is deposited in the trench to form an epitaxial region. According to the invention, the SiGe process is adopted in the IOPMOS region, so that the width of the active region of the IO PMOS is reduced on the basis of improving the performance of the IO PMOS, and the area of a chip in the IO region is saved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for saving chip area.
Background
It is well known that the performance of CMOS circuits is strongly limited by PMOS, and therefore any technology is considered advantageous if it can improve the performance of PMOS to NMOS level. Strain is introduced in the active region by a process, known as process-induced strain (S-D), i.e., source/drain (S/D) deposition-induced strain technique. SiGe is embedded in a source-drain region, so that compression deformation is generated at a channel, the carrier mobility of the PMOS transistor is improved, and the improvement of the carrier mobility can lead to high driving current and improve the performance of the transistor. The stress provided by the SiGe epitaxy can greatly improve the mobility of carriers and improve the electrical performance of the PMOS device. At the 28nm technology node, SiGe epitaxy is widely used to improve the electrical performance of core PMOS devices, while for IO PMOS devices there are few applications.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for saving chip area, which is used to solve the problems of low carrier mobility of PMOS and large usage area of IO PMOS in the prior art.
To achieve the above and other related objects, the present invention provides a method for saving chip area, which at least comprises:
providing a substrate, wherein different types of device regions are arranged on the substrate, and the different types of device regions comprise: a core NFET region, a core PFET region, an IO NFET region, an IO PFET region; grid electrodes are respectively formed on the substrate of the device areas of different types;
covering the core NFET region, the core PFET region, the IO NFET region and the IO PFET region on the substrate by photoresist; providing a photomask, and exposing and developing the substrate by using the photomask to enable the core PFET area and the IO PFET area to be displayed;
etching the substrate of the developed core PFET region and IO PFET region to form a groove for growing SiGe;
and fourthly, depositing SiGe in the groove to form an epitaxial region.
Preferably, the core NFET, core PFET, IO NFET, and IO PFET regions of step one are isolated from each other by STI regions.
Preferably, the core NFET region, the core PFET region, the IO NFET region and the IO PFET region in the first step are sequentially arranged on the substrate.
Preferably, a gate oxide layer is formed on the substrate of the different types of device regions in the first step, and the gate electrode is formed on the gate oxide layer.
Preferably, the side wall of the gate in the first step is provided with a side wall.
Preferably, in step two, the core PFET region and the IO PFET region are opened including the gates of the core PFET region and the IO PFET region and the gate oxide layer are opened.
Preferably, the trenches for growing SiGe in step three are respectively located on the substrate on both sides of the gate; when the groove is formed through etching, the gate oxide layer on the core PFET area and the IO PFET area is also removed.
Preferably, the shape of the trenches in step three is sigma-shaped.
Preferably, the epitaxial region formed in the IO PFET region in step four reduces the active region width of the IO PMOS, saving the area of the IO region.
Preferably, the epitaxial region formed in the IO PFET region in step four reduces the active area width of the IO PMOS by 10%.
As described above, the method for saving chip area of the present invention has the following beneficial effects: according to the invention, the SiGe process is adopted in the IO PMOS region, the width of the active region of the IO PMOS is reduced on the basis of improving the performance of the IO PMOS, and the area of a chip in the IO region is saved.
Drawings
FIGS. 1 to 4 are schematic views showing the structure of processes for forming SiGe epitaxial regions in different device regions according to the present invention;
FIG. 5 is a graph showing the relationship between IDSAT and POL in the present invention when the width of the active region is 9 μm;
FIG. 6 is a graph showing the relationship between IDSAT and POL in the present invention when the width of the active region is 0.243 μm.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for saving chip area, which at least comprises the following steps:
providing a substrate, wherein different types of device regions are arranged on the substrate, and the different types of device regions comprise: a core NFET region, a core PFET region, an IO NFET region, an IO PFET region; grid electrodes are respectively formed on the substrate of the device areas of different types;
further, the core NFET region, the core PFET region, the IO NFET region and the IO PFET region in the first step of this embodiment are isolated from each other by STI regions.
Further, the core NFET region, the core PFET region, the IO NFET region, and the IO PFET region in the first step of this embodiment are sequentially arranged on the substrate.
Further, in the present invention, in the first step of this embodiment, a gate oxide layer is formed on the substrate of the device region of different type, and the gate is formed on the gate oxide layer.
Further, in the present invention, a sidewall is disposed on the sidewall of the gate in the first step of this embodiment.
As shown in fig. 1, in the first step of this embodiment, a substrate is provided, on which different types of device regions are disposed, where the different types of device regions include: a core NFET region (core NFET), a core PFET region (core PFET), an IO NFET region (IO NFET), an IO PFET region (IO PFET); grid electrodes 02 are respectively formed on the substrate of the device areas of different types; the core NFET, PFET, IO NFET, and IO PFET regions are isolated from each other by STI region 01. The core NFET region, core PFET region, IO NFET region, and IO PFET region of FIG. 1 are arranged in sequence on the substrate. A gate oxide layer (GOX) is formed on the substrate of the different types of device regions, and the gate electrode is formed on the GOX layer.
Covering the core NFET region, the core PFET region, the IO NFET region and the IO PFET region on the substrate by photoresist; providing a photomask, and exposing and developing the substrate by using the photomask to enable the core PFET area and the IO PFET area to be displayed;
further, the gate and gate oxide layers of the core PFET region and the IO PFET region are exposed in step two of this embodiment, including the core PFET region and the IO PFET region.
As shown in fig. 2, this step two of this embodiment covers the core NFET region, core PFET region, IO NFET region, IO PFET region on the substrate with photoresist 03; providing a mask with which the substrate is exposed and developed to expose the core PFET region (core PFET) and the IO PFET region (IO PFET); as shown in FIG. 2, the core PFET region and the IO PFET region are exposed including the gates of the core PFET region and the IO PFET region and the gate oxide layer. That is, the gates and gate oxide layers of the core and IO PFET regions are exposed through development.
Etching the substrate of the developed core PFET region and IO PFET region to form a groove for growing SiGe;
furthermore, in the third step of this embodiment, the trenches for growing SiGe are respectively located on the substrate at two sides of the gate; when the groove is formed through etching, the gate oxide layer on the core PFET area and the IO PFET area is also removed.
Further, the shape of the trench in step three of the present embodiment is Σ -shaped.
As shown in fig. 3, step three of this embodiment is to etch the substrate of the core PFET region and the IO PFET region that are exposed, forming a trench 04 for growing SiGe; the grooves 04 for growing SiGe are respectively positioned on the substrate at two sides of the grid; when the trench 04 is formed by etching, the gate oxide layer GOX on the core PFET region and the IO PFET region is also removed. The shape of the trenches in fig. 3 is sigma-shaped.
And fourthly, depositing SiGe in the groove to form an epitaxial region. This step four deposits SiGe in the trench to form an epitaxial region 05, as shown in fig. 4.
Further, the width of the active area of the IO PMOS is reduced by the epitaxial area formed in the IO PFET area in step four of this embodiment, and the area of the IO area is saved.
Further, the epitaxial region formed in the IO PFET region in step four of this embodiment reduces the active area width of the IO PMOS by 10%.
FIG. 5 is a graph showing the relationship between IDSAT and POL in the present invention when the width of the active region is 9 μm, as shown in FIGS. 5 and 6; FIG. 6 is a graph showing the relationship between IDSAT and POL in the present invention when the width of the active region is 0.243 μm. Therefore, the IO P SiGe is basically in linear inverse proportion to the effect of IDSAT lifting on POL, and when the POL is lower than 0.72um IDSAT lifting by more than 30%, the Width (AA Width) of an active region can be correspondingly reduced by 10%.
In summary, the invention proposes to adopt the SiGe process in the IO PMOS region, reduce the width of the IO PMOS active region on the basis of improving the performance of the IO PMOS, and save the chip area in the IO region. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for saving chip area, comprising:
providing a substrate, wherein different types of device regions are arranged on the substrate, and the different types of device regions comprise: a core NFET region, a core PFET region, an IO NFET region, an IO PFET region; grid electrodes are respectively formed on the substrate of the device areas of different types;
covering the core NFET region, the core PFET region, the IO NFET region and the IO PFET region on the substrate by photoresist; providing a photomask, and exposing and developing the substrate by using the photomask to enable the core PFET area and the IO PFET area to be displayed;
etching the substrate of the developed core PFET region and IO PFET region to form a groove for growing SiGe;
and fourthly, depositing SiGe in the groove to form an epitaxial region.
2. The method of claim 1, wherein: and the core NFET region, the core PFET region, the IO NFET region and the IO PFET region in the step one are isolated from each other by STI regions.
3. The method of claim 1, wherein: and the core NFET region, the core PFET region, the IO NFET region and the IO PFET region in the step one are sequentially arranged on the substrate.
4. The method of claim 3, wherein: and in the first step, a gate oxide layer is formed on the substrate of the device region of different types, and the gate is formed on the gate oxide layer.
5. The method of claim 1, wherein: and a side wall is arranged on the side wall of the grid in the first step.
6. The method of claim 4, wherein: in step two, the core PFET region and the IO PFET region are exposed including the gates of the core PFET region and the IO PFET region and the gate oxide layer.
7. The method of claim 1, wherein: in the third step, the trenches for growing SiGe are respectively positioned on the substrate at two sides of the grid; the gate oxide layer over the core PFET region and the IO PFET region is also removed when the trench is etched.
8. The method of claim 7, wherein: the shape of the trenches in step three is sigma-shaped.
9. The method of claim 1, wherein: and in the fourth step, the width of the active area of the IO PMOS is reduced by the epitaxial area formed in the IO PFET area, so that the area of the IO area is saved.
10. The method of claim 1, wherein: the epitaxial region formed in the IO PFET region in step four reduces the active area width of the IO PMOS by 10%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210745901.8A CN115064593A (en) | 2022-06-28 | 2022-06-28 | Method for saving chip area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210745901.8A CN115064593A (en) | 2022-06-28 | 2022-06-28 | Method for saving chip area |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115064593A true CN115064593A (en) | 2022-09-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210745901.8A Pending CN115064593A (en) | 2022-06-28 | 2022-06-28 | Method for saving chip area |
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| Country | Link |
|---|---|
| CN (1) | CN115064593A (en) |
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- 2022-06-28 CN CN202210745901.8A patent/CN115064593A/en active Pending
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