CN111564556A - Pyramid-shaped resistive random access memory and preparation method thereof - Google Patents
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
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Abstract
The invention discloses a pyramid-shaped resistive random access memory and a preparation method thereof, and belongs to the field of oxygen vacancy type resistive random access memories. The invention accelerates the migration of oxygen vacancy in the resistive random access medium by adopting the electric field enhancement effect of the pyramid-shaped tip bottom electrode, controls the growth position and shape of the conductive filament, and compared with the existing planar resistive random access memory, the resistive random access memory with the structure has lower power consumption and better reliability. In addition, the pyramid structure is prepared into the source drain through hole of the CMOS, so that good integration with the CMOS circuit can be realized.
Description
Technical Field
The invention belongs to the technical field of resistive random access memories, and particularly relates to a resistive random access memory which enables a device to have the advantages of low power consumption and high consistency by improving a bottom electrode structure.
Background
The explosive data volume in the big data era has raised new requirements on the storage capacity and storage density of the memory, and the oxygen vacancy type resistive memory is more and more favored because of its non-volatility, simple structure, high integration density and good CMOS compatibility. However, the existing oxygen vacancy type resistive memory has the challenges of poor consistency, high power consumption and the like, and the work of solving the problems by adopting the improved special-shaped electrode is reported, but the problems that the position of the special-shaped electrode is difficult to locate and the like still exist.
Specifically, the resistance change mechanism of the oxygen vacancy type resistance change memory is based on the growth and the breakage of a conductive filament formed by oxygen vacancies, and certain randomness exists in the growth and the breakage processes of the conductive filament, so that the growth position of the conductive filament in each operation and the shape of the filament are inconsistent, the fluctuation of the device in each operation is large, and the reliability is poor. Due to the fact that defect distribution in the resistance change layer is inconsistent between devices, randomness of growth of the conductive filaments between different devices is caused, and uniformity between the devices is poor.
On the other hand, the operating voltage of the conventional oxygen vacancy type resistive memory is relatively high, and the current is large and the power consumption is high in the process of switching from high resistance to low resistance at the time of Reset (Reset).
In conclusion, the development of oxygen vacancy type resistive memory with low power consumption and high consistency is urgently needed.
Disclosure of Invention
The conventional resistive random access memory has poor consistency due to randomness existing in a resistive mechanism and randomness of defect distribution in a resistive layer prepared by the process, and has large power consumption in a resistive process, particularly in a process of converting from a high resistance state to a low resistance state, namely a Reset process. In order to solve the problems, the invention provides a preparation method of a pyramid resistive random access memory with low power consumption and high consistency.
The resistive random access memory provided by the invention is an oxygen vacancy type resistive random access memory and comprises a semiconductor substrate, a pyramid base, a bottom electrode, a resistive layer, a top electrode and an isolation layer, wherein the pyramid base is positioned on the semiconductor substrate; covering a bottom electrode, a resistance change layer and a top electrode on the pyramid-shaped silicon base in sequence; the bottom electrode is made of oxygen-absorbing metal, and the top electrode is made of inert metal; the isolation layer covers the surface of the device, and through holes are formed downwards from the isolation layer and filled with metal to achieve metal extraction of the bottom electrode and the top electrode.
Furthermore, the pyramid-shaped base is preferably a silicon base and can be prepared by utilizing a silicon film on the surface of the SOI substrate. The base may also be other materials such as germanium and iii-v compound semiconductor materials. Preferably, the bottom surface of the pyramid-shaped base is a square with the side length of 80 nm-200 nm, and the height from the bottom surface to the tip of the pyramid is 80 nm-200 nm.
Preferably, the bottom electrode has a thickness of 20nm to 40nm and may be selected from the following oxygen-absorbing metal materials: ti, Hf, Zr, La, etc.; the thickness of the top electrode is 20 nm-40 nm, and the top electrode can be selected from the following inert metals: pt, Ta, and W, and the like.
Preferably, the resistance change layer is an oxide resistance change layer, the thickness of the oxide resistance change layer is 5 nm-10 nm, and the material is selected from HfO2、Al2O3And Ta2O3And the like.
The invention also provides a preparation method of the oxygen vacancy type resistance change memory, which comprises the following steps:
1) forming a pyramid-shaped base on a semiconductor substrate;
2) preparing a bottom electrode covering the pyramid-shaped base;
3) depositing a resistance change layer on the bottom electrode to cover the whole bottom electrode;
4) preparing a top electrode on the resistance change layer, wherein the top electrode is covered with a pyramid structure;
5) depositing an isolating layer and flattening the surface, and then manufacturing metal extraction of the bottom electrode and the top electrode.
Preferably, an SOI substrate is selected in the step 1), a square hard mask is formed on a surface silicon film of the SOI substrate through photoetching and patterning, and then the silicon film is dry-etched to obtain a silicon column; and then, etching the silicon column by using an etching solution under the condition that the hard mask is kept until a pyramid-shaped structure is formed. Or a bulk silicon substrate can be adopted, silicon oxide and a silicon film are sequentially deposited on the bulk silicon substrate to form an SOI substrate, and then the preparation of the pyramid-shaped silicon base is carried out.
In the step 1), preferably, the hard mask of the silicon pillar is defined by electron beam lithography, an inorganic negative photoresist, such as hsq (hydrogen silsesquioxane) electron beam photoresist containing hydrosilicate, may be spin-coated on the substrate, and then patterned by electron beam lithography, taking into account that the size of the hard mask directly determines the size of the bottom surface of the subsequently formed pyramid silicon base. The silicon film is then dry etched to form silicon pillars, the depth of the etch, i.e., the thickness of the silicon film, determining the height of the subsequently formed pyramidal structures. The dry Etching may use Reactive Ion Etching (RIE) technology, and the Etching of the silicon pillar needs to use an Etching scheme with high steepness, for example, the Etching scheme with good steepness may be obtained by adjusting and controlling Etching gas ratio and Etching power in the Reactive Ion Etching.
In the step 1), a tetramethylammonium hydroxide (TMAH) solution may be used as the etching solution, and in the embodiment of the present invention, a TMAH solution with a concentration of 25% is used to etch the silicon column at 35 ℃. The concentration of the etching solution, the etching temperature and the etching time are noted to precisely control the size of the pyramid-shaped base formed after etching.
And 2) depositing a bottom electrode metal material, defining a bottom electrode area (an area to contain the pyramid-shaped base) by using a photoetching technology, forming the bottom electrode by using an etching or stripping mode, wherein a metal etching technology is required for preparing a small-size resistive random access memory unit, and a metal stripping technology is required for preparing a large-size resistive random access memory unit. The bottom electrode metal is selected from oxygen-absorbing metal such as Ti, Hf, Zr and La, and is selected from Deposition methods with good conformality such as Atomic Layer Deposition (ALD) and Magnetron Sputtering (Magnetron Sputtering).
Further, the step 3) above deposits an oxide resistance change layer, preferably made of HfO2、Al2O3And Ta2O3And the like, and the Deposition modes such as Atomic Layer Deposition (ALD) and Magnetron Sputtering (Magnetron Sputtering) can be selected。
And 4) depositing top electrode metal, defining a top electrode area (an area to contain a pyramid structure) by using a photoetching technology, forming the top electrode by using an etching or stripping mode, wherein a metal etching technology is required for preparing a small-size resistive random access memory unit, and a metal stripping technology is required for preparing a large-size resistive random access memory unit. The top electrode metal is selected from inert metals such as Pt, Ta and W. The reason why the bottom electrode is made of active metal and the top electrode is made of inert metal is that the conductive filament grows from the top end of the bottom end of the top electrode under the positive voltage, and on the other hand, the bottom electrode is made of oxygen-absorbing metal, so that a large number of oxygen vacancies exist near the top end of the bottom electrode, the conductive filament grows from the top end of the bottom electrode, the power consumption is reduced, and the consistency of the device is improved.
The isolation layer in step 5) is preferably a silicon oxide isolation layer, the thickness of the isolation layer is higher than the tip of the pyramid structure, and the isolation layer can be deposited by using methods such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.
In the step 5), after depositing an isolation layer and flattening the surface, defining through holes above the bottom electrode and the top electrode by using a photoetching technology, and etching to the bottom electrode and the top electrode by using a dry method and then a wet method by using a photoresist as a mask; removing the photoresist, depositing metal to fill the through hole and form a metal layer, and flattening the surface; and then defining the metal lead-out wire by utilizing a photoetching technology, and etching the metal layer to the isolation layer by using the photoresist as a mask in a dry method to finish the metal lead-out. The filling metal for depositing the through hole needs to be selected from metals with high filling rate and high conductivity, such as W, TiN, Cu, Al, Pt and the like.
The invention has the following advantages and positive effects:
1) the oxygen vacancy type resistance variable memory provided by the invention can accelerate the migration of oxygen vacancies due to the enhancement of the electric field at the top end of the bottom, thereby accelerating the formation and the breakage of the conductive filaments, namely reducing the operating voltage and realizing low power consumption;
2) due to the enhancement effect of the electric field at the tip, the conductive filament at the tip theoretically grows faster, and the conductive filament at other positions of the bottom electrode has an inhibiting effect, so that the probability of the conductive filament growing at the tip is enhanced, the randomness of the growing position and shape of the conductive filament is reduced, the fluctuation of a device is reduced, and the reliability of the device is improved;
3) the resistive random access memory is expected to be prepared into a through hole of a Complementary Metal Oxide Semiconductor (CMOS) circuit, so that the resistive random access memory and the CMOS circuit are well integrated.
Drawings
Fig. 1-10 are schematic diagrams of key process steps of a low-power-consumption high-consistency pyramid-shaped resistive random access memory. In the drawings, (a) is a top view of the device, (B) is a cross-sectional view of the device taken along the A-A 'direction, and (c) is a cross-sectional view of the device taken along the B-B' direction.
Wherein:
FIG. 1 shows a step of spin coating HSQ electron beam resist on an SOI substrate;
FIG. 2 is a step of patterning HSQ electron beam resist to form a square hard mask for subsequent etching of silicon pillars by electron beam lithography, and etching to form silicon pillars to a silicon oxide BOX layer;
FIG. 3 is a step of etching the silicon pillar with TMAH solution, wherein the etching process is performed from the periphery to the middle of the silicon pillar to form a stable silicon surface;
FIG. 4 shows a step of forming a pyramid structure by lifting the top mask and the inverted triangular top of the silicon pillar with TMAH etchant as time increases;
FIG. 5 is a step of depositing a bottom electrode metal, and defining the size of the bottom electrode by photolithography, wherein the bottom electrode is to cover the pyramid structure;
FIG. 6 is a step of depositing a resistance change layer;
FIG. 7 is a step of depositing a top electrode metal, defining the size of the top electrode by photolithography, the top electrode covering the pyramid structure;
FIG. 8 is a step of depositing an isolation layer and planarizing the surface;
FIG. 9 is a step of defining via holes by photolithography, filling metal after etching the via holes, and planarizing;
fig. 10 is a step of patterning a metal layer by a photolithography technique to form metal lead-out lines;
fig. 11 is a schematic representation of all of the materials in fig. 1-10.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples.
As shown in fig. 1 to 10, a low-power consumption high-consistency pyramid-shaped resistive random access memory is prepared according to the following steps:
1) the silicon film of the SOI substrate is thinned, and the specific operation mode is to oxidize the surface silicon film into silicon oxide by a dry oxygen oxidation or hydrogen-oxygen synthetic oxidation mode, then rinse the surface silicon oxide by hydrofluoric acid solution, and further spin-coat HSQ electron beam glue, as shown in figure 1. Or a bulk silicon substrate can be adopted, and an SOI substrate is formed by depositing a silicon oxide layer on the bulk silicon substrate and then depositing a thin silicon film;
2) defining the hard mask size (100nm × 100nm) of the silicon pillar by electron beam lithography, and then Etching the silicon film to the silicon oxide layer by Reactive Ion Etching (RIE), as shown in fig. 2;
3) placing the substrate into a TMAH solution with a concentration of 25%, and etching at 35 deg.C for a proper time to form pyramid-shaped tips, wherein the specific etching time can be calculated according to the height and width of the silicon pillars and the etching rate of the TMAH solution on each surface, as shown in FIGS. 3 and 4;
4) depositing a bottom electrode metal Ti by a Deposition mode with good conformality, such as Atomic Layer Deposition (ALD) or Magnetron Sputtering, and defining a bottom electrode of the resistive random access memory by a photolithography technique, wherein the bottom electrode is to cover a pyramid structure, as shown in FIG. 5;
5) deposition of 5nm thick HfO by ALD or magnetron sputtering2A resistance change layer, as shown in FIG. 6;
6) depositing top electrode metal Pt through magnetron sputtering, and defining a top electrode of the resistive random access memory through a photoetching technology, wherein the top electrode is covered with a pyramid structure, as shown in FIG. 7;
7) a 300nm thick silicon oxide spacer layer was deposited by Low Pressure Chemical Vapor Deposition (LPCVD) and planarized with Chemical Mechanical Polishing (CMP), as shown in fig. 8;
8) defining through holes above the bottom electrode and the top electrode by using a photoetching technology, etching a 250nm silicon oxide isolation layer by using a photoresist as a mask through a dry method, then corroding the residual silicon oxide and the resistance change layer in the through holes to a bottom electrode layer and a top electrode layer through a wet method, depositing Metal to fill the through holes and form a Metal layer (namely Metal 0), and carrying out surface planarization by using CMP (chemical mechanical polishing), wherein the Metal layer is shown in FIG. 9;
9) the metal lead-out lines are defined by photolithography, the metal layer is etched to the silicon oxide isolation layer by an Inductively Coupled Plasma (ICP) technique with the photoresist as a mask, and appropriate over-etching is required to prevent short circuits between the interconnection lines, as shown in fig. 10.
The embodiments of the present invention are not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. The resistive random access memory is an oxygen vacancy type resistive random access memory and is characterized by comprising a semiconductor substrate, a pyramid-shaped base, a bottom electrode, a resistive layer, a top electrode and an isolation layer, wherein: the pyramid-shaped base is positioned on the semiconductor substrate; covering a bottom electrode, a resistance change layer and a top electrode on the pyramid-shaped silicon base in sequence; the bottom electrode is made of oxygen-absorbing metal, and the top electrode is made of inert metal; the isolation layer covers the surface of the device, and through holes are formed downwards from the isolation layer and filled with metal to achieve metal extraction of the bottom electrode and the top electrode.
2. The resistive-switching memory according to claim 1, wherein the material of the pyramidal base is silicon, germanium or a group iii-v compound semiconductor material.
3. The resistive random access memory according to claim 1, wherein the bottom surface of the pyramidal base is square with a side length of 80nm to 200nm, and the height from the bottom surface to the tip of the pyramid is 80nm to 200 nm.
4. The resistive random access memory according to claim 1, wherein the bottom electrode has a thickness of 20 to 40nm and is made of an oxygen-absorbing metal selected from the group consisting of: ti, Zr, Hf and La; the thickness of the top electrode is 20-40 nm, and the material is selected from the following inert metals: pt, Ta and W; the resistance-change layer is an oxide resistance-change layer, the thickness of the resistance-change layer is 5-10 nm, and the material is selected from HfO2,Al2O3And Ta2O3。
5. The preparation method of the resistive random access memory according to claim 1, comprising the steps of:
1) forming a pyramid-shaped base on a semiconductor substrate;
2) preparing a bottom electrode covering the pyramid-shaped base;
3) depositing a resistance change layer on the bottom electrode to cover the whole bottom electrode;
4) preparing a top electrode on the resistance change layer, wherein the top electrode is covered with a pyramid structure;
5) depositing an isolating layer and flattening the surface, and then manufacturing metal extraction of the bottom electrode and the top electrode.
6. The production method according to claim 5, wherein in step 1) an SOI substrate is used, a square hard mask is formed on a surface silicon film of the SOI substrate by photolithography patterning, then the silicon film is dry-etched to obtain silicon pillars, and then the silicon pillars are etched with an etching solution with the hard mask being left until a pyramidal silicon base is formed; or a bulk silicon substrate is adopted, silicon oxide and a silicon film are sequentially deposited on the bulk silicon substrate to form an SOI substrate, and then the preparation of the pyramid-shaped silicon base is carried out.
7. The method of claim 6, wherein in step 1), the hard mask of the silicon pillar is defined by electron beam lithography, and then the silicon film is dry etched to form the silicon pillar, and then the silicon pillar is etched using a tetramethylammonium hydroxide solution as an etching solution.
8. The method according to claim 5, wherein in step 2), a bottom electrode metal material is deposited, a bottom electrode area is defined through a photoetching technology, and a bottom electrode is formed in an etching or stripping mode; and 4) depositing top electrode metal, defining a top electrode area through a photoetching technology, and forming a top electrode in an etching or stripping mode.
9. The method of claim 5, wherein the oxide resistance change layer is deposited in step 3) by atomic layer deposition or magnetron sputtering.
10. The method of claim 5, wherein in step 5), the isolation layer is deposited by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition and the surface is planarized; then, defining through holes above the bottom electrode and the top electrode by utilizing a photoetching technology, and etching the through holes to the bottom electrode and the top electrode by a dry method and then etching the through holes to the bottom electrode and the top electrode by a wet method by taking photoresist as a mask; removing the photoresist, depositing metal to fill the through hole and form a metal layer, and flattening the surface; and defining the metal lead-out wire by utilizing a photoetching technology, and etching the metal layer to the isolation layer by using the photoresist as a mask in a dry method to finish metal lead-out.
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| CN103515534A (en) * | 2013-10-10 | 2014-01-15 | 北京大学 | Resistive random access memory with high uniformity and manufacturing method thereof |
| CN107221598A (en) * | 2017-04-25 | 2017-09-29 | 中国科学院微电子研究所 | A kind of method and RRAM device of raising RRAM homogeneity |
| CN107275482A (en) * | 2017-07-07 | 2017-10-20 | 中国科学院微电子研究所 | The manufacture method and resistance-variable storing device of a kind of resistance-variable storing device |
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Application publication date: 20200821 |