CN111548683B

CN111548683B - Polystyrene-porphyrin derivative nano vertical array film and preparation method and application thereof

Info

Publication number: CN111548683B
Application number: CN202010400448.8A
Authority: CN
Inventors: 石乃恩; 顾大庆; 仪明东; 丁震; 黄维; 余洋
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2020-05-13
Filing date: 2020-05-13
Publication date: 2021-09-28
Anticipated expiration: 2040-05-13
Also published as: CN111548683A

Abstract

The invention discloses a polystyrene-porphyrin derivative nanometer vertical array film and a preparation method and application thereof, the nanometer vertical array film functional film is formed by mixing polystyrene and porphyrin derivative in a proper proportion, has uniform appearance, low roughness and simple process, and can be used for preparing a nonvolatile floating gate type transistor memory with high on-off ratio, high stability and high tolerance.

Description

Polystyrene-porphyrin derivative nano vertical array film and preparation method and application thereof

Technical Field

The invention belongs to the technical field of functional thin film devices, and is applied to the field of memories in the electronic industry, in particular to a polystyrene-porphyrin derivative nano vertical array thin film which is used as a charge storage layer of an organic field effect transistor memory, and realizes the preparation of a high-performance organic field effect transistor memory.

Background

With the rapid development of the science and technology in the world and the increasing living standard of people, intelligent electronic products are ubiquitous in our lives, including computers, chips, communication, storage and the like. Small organic molecules as new materials have the following advantages: firstly, special electrical properties can be realized through molecular structure design and regulation; manufacturing electronic devices based on organic materials can effectively reduce production cost; the flexible electronic product has the characteristics of good flexibility, light weight and the like, and can realize the functional application of large-area flexible and stretchable flexible electronic products. The memory can record and obtain digital information, realizes information storage and retrieval through coding of '0' and '1', and is a core component of a computer and an electronic system. The storage medium used for the memory includes a semiconductor device, a magnetic material, an optical disk, and the like. When the memory chip is connected with the CPU chip, the address wire, the data wire and the control signal wire of the memory can be respectively connected to the address bus, the data bus and the control bus of the CPU, thereby realizing the design of the integrated circuit of the device. The memory device of the organic field effect transistor generally adopts a device structure with bottom gate top contact, the device with the structure has high charge injection efficiency, and the contact condition of the organic semiconductor layer and the source and drain electrodes is better, so that the device has lower contact resistance. The storage device integrating organic field effect transistors has the characteristics of small area, low power consumption, reliability, stability, large-capacity storage and the like, but the challenges for realizing the characteristics are many, so that the search for excellent storage materials is urgently required to meet the increasingly advanced technological requirements.

Porphyrins are a class of macromolecular heterocyclic compounds formed by the interconnection of the α -carbon atoms of four pyrrolyl subunits via methine bridges (═ CH-). The parent compound is porphin (porphin, C20H14N4), and the porphin with substituent is called porphyrin. The porphyrin ring has 26 pi electrons and is a highly conjugated system. The applications of porphyrin and its derivatives are diverse, such as porphyrin molecular switches, solar cells, organic electroluminescence, photoconductive materials, optical storage devices, etc. The application of the porphyrin compound in the aspect of storage is not related, and a novel optical storage device is designed mainly by utilizing the special photoelectric characteristics of the porphyrin derivative. The earlier research structure shows that porphyrin has potential electric storage and photoelectric response functions and has important potential application prospect in the field effect transistor memory.

The topography of the floating gate layer in an organic field effect transistor memory is critical to the performance of the device. Generally, increasing the contact area with charges and increasing the active sites for trapping charges are important considerations for the morphological design of the floating gate layer material. However, the mixture of Polystyrene (PS) and small organic molecules is often evaporated to form a uniform and smooth thin film, resulting in limited charge trapping sites. (relevant reports can be seen in Phys. chem. Phys.,2016,18, 9412; adv. Sci.2018, 1800747; Organ. Electron.2017,44,247e 252). in the invention, through the composition of porphyrin derivatives and PS, a uniform and regular nano vertical array film can be obtained with the assistance of a simple spin-coating annealing process, so that more charge trapping sites are brought, and the charge trapping density of the material is improved. PS can improve the stability and durability of the device, promoting the practicality and commerciality of the material. In addition, the nanometer vertical array is regular and uniform in appearance, transmission and transfer of current carriers on the surface are facilitated, and the overall device performance is greatly improved.

Disclosure of Invention

The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides a polystyrene-porphyrin derivative nano vertical array film and a preparation method thereof, so as to realize an organic field effect transistor memory with a high storage window, high stability and high tolerance.

The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:

a polystyrene-porphyrin derivative nanometer vertical array film is characterized in that: the film is prepared from Polystyrene (PS) and porphyrin Derivative (DAH)₂P), the structure of which is a nano vertical array, the nano array is composed of a plurality of one-dimensional structures which are formed by upward growth vertical to the substrate.

The polystyrene-porphyrin derivative nanometer vertical array film is characterized in that: the structural formula of the porphyrin derivative is shown as,

further, in the polystyrene-porphyrin derivative nano vertical array film, by mass, DAH₂P:PS＝1:0.6–1:6。

Furthermore, the thickness of the polystyrene-porphyrin derivative nano vertical array film is 25-35 nm, and the one-dimensional structure of the formed film is regularly and tightly arranged.

The preparation method of the polystyrene-porphyrin derivative nano vertical array film is characterized by comprising the following steps:

step 1, reacting DAH at room temperature₂Dissolving P in chlorobenzene solution by ultrasonic wave to prepare 1 mg/mL^-1DAH of (2)₂The P solution and PS solution were dissolved in a chlorobenzene solution to prepare 3 mg/mL^-1The PS solution of (1). Then, DAH is added₂And mixing the P solution and the PS solution, and dissolving by ultrasonic to obtain a transparent mixed solution.

And 2, cleaning, drying and pretreating the silicon wafer plated with the silicon dioxide layer gate insulating layer with the thickness of 300 nm.

And 3, immediately spin-coating the mixed solution on the gate insulating layer subjected to cleaning and drying pretreatment. After spin coating, the substrate is immediately placed into an oven with the temperature of 110-120 ℃ for annealing for 30 minutes, and the polystyrene-porphyrin derivative nano vertical array film can be obtained on the surface of the gate insulating layer.

Further, the preparation method of the polystyrene-porphyrin derivative nano vertical array film is characterized by comprising the following steps: DAH₂And mixing the P solution and the PS solution according to the volume ratio of 1:0.2-1:2, immediately ultrasonically dissolving, and immediately performing spin coating treatment on the mixed solution.

Further, the preparation method of the polystyrene-porphyrin derivative nano vertical array film is characterized by comprising the following steps: the silicon wafer plated with a silicon dioxide layer gate insulating layer with the thickness of 300nm is cleaned and dried by sequentially carrying out ultrasonic treatment on the silicon wafer by using ethanol, deionized water, acetone and ethanol, and then using N₂After flow blow drying, the films were dried at 120 ℃ for half an hour and then stored in a vacuum desiccator for immediate use after 15 minutes of irradiation with an ultraviolet lamp before film deposition.

Further, the preparation method of the polystyrene-porphyrin derivative nano vertical array film is characterized by comprising the following steps: in step 3, spin coating speed: 3000r/min, spin coating time: 30s, spin-coating acceleration:600r/s²amount of spin coating solution: 100 μ L.

The application of the polystyrene-porphyrin derivative composite nano vertical array film in a transistor memory is to prepare the composite nano vertical array film into the transistor memory as a charge trapping layer.

Furthermore, the prepared organic field effect transistor memory is characterized in that: the device structure is as follows from top to bottom: the transistor comprises a source electrode, a drain electrode, a semiconductor layer, a charge trapping layer, a gate insulating layer and a substrate, wherein the functional film serves as the charge trapping layer, and the overall device structure is designed to be a transistor structure with bottom gate top contact.

Further, the substrate can be a highly doped silicon wafer, a glass sheet or plastic PET, and the like; the gate insulating layer can be a silicon dioxide layer with different thicknesses of 50nm,100nm and 300 nm; the semiconductor layer may be one of P-type semiconductors such as pentacene, tetracene, titanium bronze, or the like; the source and drain electrode material can be metal or organic conductor material, such as gold, silver, copper, etc.; but preferably an n-doped Si-type substrate, 300nm silicon dioxide, pentacene, gold, or the like.

Further, the device fabrication is characterized by: pentacene and source/drain electrodes are formed by thermal vacuum evaporation, and the vacuum degree of the pentacene and the source/drain electrodes is controlled at 5 × 10^-4pa or less, and the evaporation rate of pentacene is controlled to be about

Controlling the evaporation rate of the source and drain electrodes to be about

The pentacene thickness is controlled to be about 50nm after about 30 minutes of vapor deposition, and the source and drain electrode thickness is preferably controlled to be 60-70nm after about 60 minutes of vapor deposition.

The invention adopts a simple spin-coating annealing method to obtain a regular polystyrene-porphyrin derivative composite nano vertical array film, namely the array growth direction is vertical to the substrate and arranged upwards, and the invention can directly grow the nano array on SiO₂On the/Si substrate, the preparation and the collection of a memory are facilitatedAnd (4) obtaining. In addition, the regularly arranged nano vertical array thin film material has a larger contact angle and lower surface roughness, so that a conductive channel is more regular and flat, and the field effect of the transistor is improved. The nano vertical array film as a charge trapping layer has higher specific surface area, forms higher-density storage sites, is beneficial to the effective transmission of current carriers, and greatly improves the overall performance of the transistor memory.

Has the advantages that: compared with the prior art, the preparation method of the polystyrene-porphyrin derivative nano vertical array film provided by the invention has the following advantages:

1. the polystyrene-porphyrin derivative composite nano vertical array film is different from a common spin-coating film and has higher specific surface area, thereby having higher charge trapping sites and improving the storage performance;

2. the nano vertical array film prepared by the simple spin-coating annealing method has simpler process, is convenient for large-scale integration and is beneficial to large-scale commercial popularization;

3. with DAH₂The functional film prepared from the P-based porphyrin derivative expands the potential application of the porphyrin derivative in the aspect of electricity, in particular to the field of transistor memories;

4.DAH₂when the mass ratio of P to PS is 1:3, the memory has excellent storage capacity, stability and tolerance.

Drawings

FIG. 1 is a SEM thickness view of a cross-section of a thin film of a polystyrene-porphyrin derivative composite nano-array prepared in example 1;

FIG. 2 is an AFM interface view of a polystyrene-porphyrin derivative composite nano-array film prepared in example 1;

FIG. 3 is a schematic structural diagram of an organic field effect transistor memory according to

embodiments

1, 2 and 3;

FIG. 4 is an AFM image of the thin film of polystyrene/porphyrin derivative composite nano-array of example 1 after evaporation of pentacene;

FIG. 5 is a graph showing the contact angle of the surface of the thin film of polystyrene/porphyrin derivative composite nano-array of example 1;

FIG. 6 is a transfer curve of an organic field effect transistor memory of example 1;

FIG. 7 is an output curve of an organic field effect transistor memory of example 1;

FIG. 8 shows the read speed of the organic field effect transistor memory of example 1;

FIG. 9 is a memory window of an organic field effect transistor memory according to example 1;

FIG. 10 is a memory window of an organic field effect transistor memory according to example 2;

FIG. 11 is a memory window of an organic field effect transistor memory according to example 3;

FIG. 12 is a read-write cycle chart of the organic field effect transistor memory of example 1;

fig. 13 shows the retention time of the organic field effect transistor memory of example 1.

Detailed Description

The invention provides a preparation method of a polystyrene-porphyrin derivative nano vertical array film, and is applied to the field of electronic devices. The nano vertical array film functional film is formed by mixing polystyrene and porphyrin derivatives in a proper proportion, has regular and ordered appearance, low roughness and simple process, and can be used for preparing a nonvolatile floating gate type transistor memory with high on-off ratio, high stability and high tolerance.

In order to make the content, technical scheme and beneficial effects of the invention more clear and clearer, the invention is further described in detail in the following with the accompanying drawings.

Example 1

(1) The invention uses the following medicines:

①DAH₂p is a small molecule material of porphyrin derivative, purchased from Aldrich chemical agents;

the molecular formula structure is as follows:

(PS) from Aldrich Chemicals; the molecular formula structure is as follows:

③ PENTACENE (pentacene) was purchased from Aldrich chemical agents; the molecular formula structure is as follows:

(2) the preparation process of the polystyrene and porphyrin derivative composite nano vertical array film comprises the following steps:

firstly, weighing a certain amount of DAH under room temperature environment₂Dissolving the P-type compound in chlorobenzene solution to prepare 1 mg/mL^-1DAH of (2)₂A solution P;

② weighing a certain amount of PS to be dissolved in chlorobenzene to prepare 3 mg.mL^-1(ii) a PS solution of (a);

taking appropriate amount of the first and the second to mix, wherein the volume ratio of the mixed solution is DAH₂Solution P: PS solution 1: 1; immediately carrying out ultrasonic treatment after mixing to ensure complete dissolution, and immediately carrying out spin coating treatment;

and fourthly, selecting a silicon dioxide wafer with the thickness of 300nm as a gate insulating layer, performing ultrasonic treatment on the silicon dioxide wafer for 15 minutes by using ethanol, deionized water, acetone and ethanol respectively before use, blow-drying water stains by using a nitrogen bottle, drying the silicon dioxide wafer in a heat preservation box at the temperature of 120 ℃ for half an hour, and then performing vacuum preservation. The product is irradiated by ultraviolet for 15 minutes before use and can be used as soon as possible;

and (c) immediately spin-coating the solution on a substrate (c), wherein the spin-coating rotation speed is as follows: 3000 r/min; spin coating time: 30 s; spin-coating acceleration: 600r/s²Spin coating solvent amount: 100 mu L of the solution;

sixthly, immediately placing the spun film into a 115 ℃ oven for annealing for 30 minutes, finishing the preparation of the nano array morphology film, and placing the film in vacuum for later use. (all the above operations were carried out in a dust-free environment).

Description of the drawings:

1. in the step (sixthly), the surface morphology of the prepared film is tested by SEM, and as shown in figure 1, the cross-section SEM thickness of the prepared polystyrene-porphyrin derivative composite nano array is about 30 nm.

2. According to the thin film AFM picture, the root mean square roughness of the nano vertical array thin film is 0.244nm (FIG. 2). The nano array film is smooth and uniform, the carrier mobility is favorably improved, the charge trapping sites are increased due to the dense and regular array shape, and the charge trapping density is further improved.

(3) The preparation process of the organic field effect transistor memory comprises the following steps:

putting the silicon chip which is coated with the thin film material by the spin coating and annealed into a vacuum evaporation chamber, and extracting the silicon chip with the thickness less than 5 multiplied by 10^-4Pa degree of vacuum, and controlling the evaporation rate of pentacene to be about

Continuously evaporating for about 30 minutes to obtain a pentacene semiconductor layer with the thickness of about 50 nm;

secondly, after the pentacene layer is evaporated, a mask is added for patterning treatment to evaporate the source and drain electrodes, and the vacuum environment is controlled to be 5 multiplied by 10^-4The width of a channel of the mask is 1500 mu m and the length is 100 mu m below Pa; the evaporation electrode material can be selected from heavy metals, but is preferably pure gold, and the evaporation rate is about

And continuously evaporating for about one hour to obtain a gold electrode layer with the thickness of about 60-70nm, completing the manufacturing of the transistor memory, and then storing in vacuum to be tested.

(all the above operations were carried out in a dust-free environment)

Description of the drawings:

1. in the above steps, the device structure diagram adopted by the invention is as shown in fig. 3, and the device structure diagram sequentially comprises a source drain electrode, a semiconductor layer, a charge trapping layer, a gate insulating layer and an n-type doped Si-type substrate from top to bottom. The charge trapping layer is a polystyrene/porphyrin derivative composite nano vertical array film material;

2. the source and drain electrodes are gold and have a thickness of about 60-70 nm; the semiconductor layer is pentacene and has a thickness of about 50 nm. As shown in fig. 4, the AFM image shows that the evaporated pentacene layer also presents a regular and continuous array shape, which indicates that the pentacene layer has better crystallinity and is more favorable for the transmission of carriers;

3. through the contact angle test of the nano vertical array film, as shown in fig. 5, the nano vertical array film material doped with the PS has increased hydrophobicity, and charges are more favorable for entering the film structure. PS is used as a wide-band-gap insulating material and uniformly distributed in the gap of the film to serve as a blocking layer in a device structure, so that the loss of charges is prevented, and the doped film has better charge trapping capacity.

(4) The performance test of the organic field effect transistor memory in the invention is as follows:

after the device is prepared, the storage performance is analyzed and characterized by a semiconductor tester Jishili 4200 and Agilent B1500, and the specific steps are that SiO is used₂Grinding a small angle of the/Si sheet until the substrate Si leaks out, respectively connecting three probes of a semiconductor tester with the source-drain electrode and the grid electrode, and respectively testing a series of electrical or storage performances such as transfer and output curves of the semiconductor tester.

Description of the drawings:

1. as shown in FIG. 6, the transistor memory mobility reaches 0.12cm²Vs, on-off ratio of 10⁴The threshold voltage is also within 5V. The resulting transistor memory has a reliable field effect, as shown by the transistor device output curve of fig. 7.

2. The memory device performance is mainly characterized in the following four aspects,

firstly, storing speed: as shown in the negative storage characteristic transfer curve of the device in fig. 8, the test time is respectively selected from four times of 0.02,0.2,1 and 5s, and under the condition of adding the same negative gate voltage, the source-drain current range and the gate voltage variation range of the transfer curve are not obviously changed, which indicates that the device has good read-write speed in four test states, reaches the reaction time of commercial application of 0.02s, and indicates that the device has a fast response characteristic and good charge capturing capability.

Storing a window: as shown in fig. 9, the ratio of the ultra-large negative window under the p-type semiconductor layer is 82%, and when writing is performed at-140V gate voltage, the negative storage window reaches 110V, which shows that the p-type semiconductor layer has excellent hole trapping capability, ultra-large storage capacity and extremely high reading accuracy. The device also had an electron capture window of 15V, with a total window of approximately 125V. The results show that the composite nano vertical array film as a storage window of a charge trapping layer reaches the level of the front level in the technical field.

③ the cycle of reading and writing: as shown in fig. 12, the device can endure 100 consecutive read/write erase cycles, and the value is substantially stable, indicating good endurance of the memory.

Maintaining time: as shown in FIG. 13, the on-off ratio of the trapped charge retention capability of the device is still greater than 10 at a retention time of more than 10000s⁴And basically has no attenuation, and embodies the excellent stability of the device.

Example 2

The preparation method is the same as example 1, except that the volume ratio of the two solutions is changed to DAH₂Solution P: PS solution 1: 0.2. As shown in fig. 10, under the same gate voltage writing of-140V as in example 1, the total window is 80V, the positive window almost disappears, the electron trapping ability is poor, and the storage window is mainly a storage window for trapping holes negatively. As can be seen, DAH at low PS ratios₂P-functional films also have appreciable memory window performance.

Example 3

The preparation method is the same as example 1, except that the volume ratio of the two solutions is changed to DAH₂Solution P: PS solution 1: 2; as shown in fig. 11, under the same gate voltage writing of-140V as in example 1, the total window is 100V, the negative window is about 90V, and the positive window is about 10V, the hole trapping capability is still excellent, but the electron trapping capability is still reduced, but there is still a considerable positive window, which indicates that DAH as a whole₂The composition of P and PS has good charge storage performance to a certain extent and in a proper proportion.

In summary, the implementation is the preferred implementation of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims

1. A polystyrene-porphyrin derivative nanometer vertical array film is characterized in that: the film is prepared from polystyrene PS and porphyrin derivative DAH₂P, the structure of which is a nano vertical array, wherein the nano vertical array is composed of a plurality of one-dimensional structures which are formed by upward growth vertical to the substrate;

the porphyrin derivative DAH₂P has a structural formula of

The preparation method of the nano vertical array film comprises the following steps:

step 1, reacting DAH at room temperature₂Dissolving P in chlorobenzene solution by ultrasonic wave to prepare 1 mg/mL^-1DAH of (2)₂The P solution and PS solution were dissolved in a chlorobenzene solution to prepare 3 mg/mL^-1(ii) a PS solution of (a); then, DAH is added₂Mixing the P solution and the PS solution, and dissolving by ultrasonic to obtain a transparent mixed solution;

step 2, cleaning, drying and pretreating the silicon wafer plated with the silicon dioxide gate insulating layer with the thickness of 300 nm;

and 3, immediately spin-coating the mixed solution on the gate insulating layer subjected to cleaning and drying pretreatment, immediately putting the gate insulating layer into a 110-plus-one 120-DEG C drying oven for annealing for 30 minutes after spin-coating, and obtaining the polystyrene-porphyrin derivative nano vertical array film on the surface of the gate insulating layer.

2. The polystyrene-porphyrin derivative nano vertical array film of claim 1, wherein: by mass, DAH₂P:PS＝1:0.6–1:6。

3. The polystyrene-porphyrin derivative nano vertical array film of claim 1, wherein: the thickness of the film is 25-35 nm, and the one-dimensional structure of the film is regularly and tightly arranged.

4. The polystyrene-porphyrin derivative nano vertical array film of claim 1, wherein: DAH₂And mixing the P solution and the PS solution according to the volume ratio of 1:0.2-1:2, immediately ultrasonically dissolving, and immediately performing spin coating treatment on the mixed solution.

5. The polystyrene-porphyrin derivative nano vertical array film of claim 1, wherein: the silicon wafer plated with a silicon dioxide gate insulating layer with the thickness of 300nm is cleaned and dried by sequentially carrying out ultrasonic treatment on the silicon wafer by using ethanol, deionized water, acetone and ethanol, and then using N₂After flow drying, the films were dried at 120 ℃ for half an hour and then stored in a vacuum desiccator for immediate use after 15 minutes of irradiation with an ultraviolet lamp before deposition of the films.

6. The polystyrene-porphyrin derivative nano vertical array film of claim 1, wherein: in step 3, spin coating speed: 3000r/min, spin coating time: 30s, spin-coating acceleration: 600r/s²Amount of spin coating solution: 100 μ L.

7. The use of a polystyrene-porphyrin derivative nano vertical array film as claimed in any one of claims 1 to 6, wherein: the organic field effect transistor memory is applied to an organic field effect transistor memory, and the device structures in the transistor memory are sequentially from top to bottom: the transistor comprises a source electrode, a drain electrode, a semiconductor layer, a charge trapping layer, a gate insulating layer and a substrate, wherein the overall device structure is designed into a transistor structure with bottom gate top contact; the polystyrene-porphyrin derivative nanometer vertical array film is used as a charge trapping layer, the substrate is a highly doped silicon wafer, the gate insulating layer is a 300nm silicon dioxide layer, the semiconductor layer is one of P-type semiconductors, the P-type semiconductors are pentacene, tetracene and titanium bronze, and the source and drain electrode material is gold or copper.

8. According to claim 7The application is characterized in that: the device consists of an n-type doped Si-type substrate, 300nm silicon dioxide, a polystyrene-porphyrin derivative nano vertical array film, pentacene and a gold electrode, wherein the pentacene and the source and drain electrode gold are formed into films by adopting a thermal vacuum evaporation film-forming method, and the evaporation vacuum degrees of the pentacene and the source and drain electrode gold are both lower than 5 multiplied by 10^-4Pa, pentacene evaporation rate of

The gold electrode has a vapor deposition rate of