CN111508835A - Pattern structure and forming method thereof - Google Patents

Pattern structure and forming method thereof Download PDF

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Publication number
CN111508835A
CN111508835A CN202010338501.6A CN202010338501A CN111508835A CN 111508835 A CN111508835 A CN 111508835A CN 202010338501 A CN202010338501 A CN 202010338501A CN 111508835 A CN111508835 A CN 111508835A
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Prior art keywords
material layer
doped
doping
doped material
layer
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CN202010338501.6A
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Chinese (zh)
Inventor
马万里
马云骁
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Shenzhen Zhaosi Microelectronics Technology Co ltd
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Shenzhen Zhaosi Microelectronics Technology Co ltd
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Priority to CN202010338501.6A priority Critical patent/CN111508835A/en
Publication of CN111508835A publication Critical patent/CN111508835A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a pattern structure and a forming method thereof, wherein the forming method of the pattern structure comprises the following steps: providing a material layer; forming a doped material layer on the upper surface of the material layer, wherein the doping concentration of the doped material layer is gradually changed from bottom to top; and forming an opening in the doped material layer by adopting a wet etching process to form a pattern structure, wherein the opening exposes the material layer. In the method for forming the graphic structure, the doping concentration of the doping material layer is gradually changed from bottom to top; the wet etching process is adopted to form the opening in the doped material layer, so that high production efficiency can be ensured, the problem that etching is in a horn mouth shape can be solved, and a certain integration level is ensured.

Description

Pattern structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a pattern structure and a method for forming the same.
Background
The integrated circuit is made by using semiconductor manufacturing process, and many transistors, resistors, capacitors and other components are manufactured on a small single crystal silicon chip, and the components are combined into a complete electronic circuit by multilayer wiring or tunnel wiring. In the manufacturing process of the semiconductor device, various contact holes are often required to be formed, a dry etching process or a wet etching process can be adopted for forming the contact holes, but the dry etching process has low efficiency and high cost, and the contact holes formed by the wet etching process can be in a serious horn mouth shape, so that the integration level of the device is influenced.
Disclosure of Invention
In view of the above, the present invention provides a pattern structure and a method for forming the same.
The invention provides a method for forming a pattern structure, which comprises the following steps: providing a material layer; forming a doped material layer on the material layer, wherein the doping concentration of the doped material layer is gradually changed from bottom to top, so that the etching removal rate of the doped material layer under the same etching condition is gradually reduced from bottom to top; and forming an opening in the doped material layer by adopting a wet etching process, wherein the opening exposes the material layer.
In the method for forming the pattern structure, the doping concentration of the doping material layer is gradually changed from bottom to top; and a wet etching process is adopted to form an opening in the doped material layer, so that high production efficiency can be ensured, the problem that etching is in a horn mouth shape can be solved, and a certain integration level is ensured.
In one embodiment, before forming the doped material layer on the upper surface of the material layer, the method further includes: and forming an undoped material layer on the upper surface of the material layer, wherein the undoped material layer is positioned below the doped material layer.
In one embodiment, the doping concentration of the doping material layer is gradually reduced from bottom to top.
In one embodiment, the doped material layer comprises doped silicon dioxide, and the doped impurities comprise one or more of boron and phosphorus.
In one embodiment, the doping concentration of the doping material layer gradually changes in a gradient manner or continuously and gradually changes from bottom to top.
In one embodiment, the doping concentration of the doping material layer is between 0% and 10%.
In one embodiment, the concentration of impurity doping is gradually reduced during the formation of the doped material layer.
The present invention also provides a graphic structure comprising: a layer of material; the doping material layer is formed on the material layer, and the doping concentration of the doping material layer is gradually changed from bottom to top so that the etching removal rate of the doping material layer under the same etching condition is gradually reduced from bottom to top; and the opening is formed in the doped material layer, and the material layer is exposed through the opening.
In the graph structure, the doping concentration of the doping material layer is gradually changed from bottom to top, so that high production efficiency can be guaranteed, the problem that etching is in a horn mouth shape can be solved, and a certain integration level is guaranteed.
In one embodiment, the method further comprises the following steps: a layer of undoped material located between the layer of material and the layer of doped material.
In one embodiment, the doping concentration of the doping material layer is gradually reduced from bottom to top.
Drawings
FIG. 1 is a flow chart of a method of forming a pattern structure according to the present invention.
FIGS. 2 to 9 are schematic structural views of steps in a method for forming a pattern structure according to the present invention; fig. 9 is a schematic structural diagram of the graphic structure of the present invention.
101. A layer of material; 102. a layer of undoped material; 103. a layer of doped material; 104. an opening; 105. and (7) photoresist.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
One embodiment, as shown in fig. 1, provides a method for forming a pattern structure, comprising: providing a material layer 101; forming a doped material layer 103 on the material layer 101, wherein the doping concentration of the doped material layer 103 gradually changes from bottom to top, so that the etching removal rate of the doped material layer 103 under the same etching condition gradually decreases from bottom to top; an opening 104 is formed in the doped material layer 103 by a wet etching process to form a pattern structure, wherein the opening 104 exposes the material layer 101.
In the present embodiment, in the method for forming the pattern structure, the doping concentration of the doped material layer 103 gradually changes from bottom to top; the opening 104 is formed in the doped material layer 103 by using a wet etching process, so that high production efficiency can be ensured, the problem that etching is in a horn mouth shape can be solved, and a certain integration level is ensured.
S10: as shown in fig. 2, a layer of material 101 is provided.
In one embodiment, the material layer 101 comprises a silicon substrate or a metal layer.
In one embodiment, after step S10, the method further includes:
s11: as shown in fig. 3, an undoped material layer 102 is formed on the upper surface of the material layer 101, and the undoped material layer 102 is located below the doped material layer 103.
In one embodiment, the undoped material layer 102 comprises a silicon dioxide layer.
The undoped material layer 102 can prevent impurities in the doped material layer 103 from diffusing into the material layer 101, and avoid affecting parameters of the chip.
S20: as shown in fig. 4 to 5, a doped material layer 103 is formed on the material layer 101, and the doping concentration of the doped material layer 103 gradually changes from bottom to top.
In one embodiment, the doping concentration of the doping material layer 103 is gradually decreased from bottom to top.
In one embodiment, the layer of doped material 103 comprises a dielectric layer.
In one embodiment, the doped material layer 103 is formed on the top surface of the undoped material layer 102.
In one embodiment, the doped material layer 103 comprises doped silicon dioxide, and the doped impurities comprise one or more of boron and phosphorus.
In one embodiment, the doping concentration of the doping material layer 103 gradually changes in a gradient manner or continuously and gradually changes from bottom to top.
In one embodiment, as shown in fig. 5, the doping concentration of the doping material layer 103 is gradually changed from bottom to top in a continuous manner.
In one embodiment, the doping concentration of the doped material layer 103 gradually changes in a gradient manner from bottom to top, as shown in fig. 4.
In one embodiment, the doped material layer 103 includes a plurality of sub material layers, and the doping concentration of the doped material layer 103 varies from bottom to top.
In one embodiment, the doped material layer 103 includes at least 2 sub-material layers, for example, the number of sub-material layers included in the doped material layer 103 may be 2, 3, 4, 5, 6, 7, or 8.
In one embodiment, the doping concentration of the several sub-material layers is uniform.
In one embodiment, the doping concentration of the plurality of sub-material layers is graded.
In one embodiment, the doping concentration of the doped material layer 103 is between 0% and 10%, for example, the maximum doping concentration may be 5%, 8%, 9%, 10%.
In one embodiment, the method of forming the doped material layer 103 includes: physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes.
In one embodiment, the concentration of impurity doping is gradually reduced during the formation of the doped material layer 103.
In one embodiment, the ratio of silane, phosphane and borane in the reaction gas is gradually adjusted during the growth of the doping material layer 103, so that the doping concentration of the doping material layer 103 gradually changes from bottom to top.
S30: an opening 104 is formed in the doped material layer 103 by a wet etching process to form a pattern structure, wherein the opening 104 exposes the material layer 101.
The wet etching process is convenient to process, a large amount of processing can be carried out in a liquid corrosion tank in one step during processing operation, the yield is high, and the production efficiency is high. The doping concentration of the doping material layer 103 is larger, the etching efficiency is higher, so that although the etching time of the upper part of the doping material layer 103 is long, the doping concentration is lower than that of the lower part, so that the upper and lower etching amounts of the doping material layer 103 are almost the same, the phenomenon that the etching is in a horn mouth shape can be avoided, and the integration level of the device is ensured.
In one embodiment, step S30 includes:
s301: as shown in fig. 6, a photoresist 105 is formed on the upper surface of the doped material layer 103;
s302: as shown in fig. 7, the photoresist 105 is subjected to a developing process to form a patterned photoresist 105;
s303: as shown in fig. 8, the patterned photoresist 105 is used as a mask, the doped material layer 103 is etched by a wet etching process, an opening 104 is formed in the doped material layer 103 to form a pattern structure, and the opening 104 exposes the material layer 101;
s304: as shown in fig. 9, the patterned photoresist 105 is removed.
In one embodiment, a wet etching process is used to form openings 104 in the doped material layer 103 and the undoped material layer 102 to form a pattern structure, and the openings 104 expose the material layer 101.
In one embodiment, opening 104 comprises a contact hole.
One embodiment, as shown in FIG. 9, provides a graphic structure comprising: a material layer 101; the doped material layer 103 is formed on the material layer 101, and the doping concentration of the doped material layer 103 is gradually changed from bottom to top, so that the etching removal rate of the doped material layer 103 under the same etching condition is gradually reduced from bottom to top; an opening 104 is formed in the doped material layer 103, wherein the opening 104 exposes the material layer 101.
In this embodiment, in the above graph structure, the doping concentration of the doped material layer 103 gradually changes from bottom to top, which not only ensures high production efficiency, but also solves the problem that the etching is in a bell mouth shape, and ensures a certain integration level.
In one embodiment, further comprising: a layer of undoped material 102 located between the material layer 101 and the layer of doped material 103.
In one embodiment, the doping concentration of the doping material layer 103 is gradually decreased from bottom to top.
In one embodiment, an opening 104 is formed in the doped material layer 103 and the undoped material layer 102, the opening 104 exposing the material layer 101.
In one embodiment, the material layer 101 comprises a silicon or metal layer.
In one embodiment, the undoped material layer 102 comprises a silicon dioxide layer.
The undoped material layer 102 can prevent impurities in the doped material layer 103 from diffusing into the material layer 101, and avoid affecting parameters of the chip.
In one embodiment, the layer of doped material 103 comprises a dielectric layer.
In one embodiment, the doped material layer 103 comprises doped silicon dioxide, and the doped impurities comprise one or more of boron and phosphorus.
In one embodiment, the doping concentration of the doping material layer 103 gradually changes in a gradient manner or continuously and gradually changes from bottom to top.
In one embodiment, the doping concentration of the doped material layer 103 is between 0% and 10%, for example, the maximum doping concentration may be 5%, 8%, 9%, 10%.
In one embodiment, opening 104 comprises a contact hole.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method for forming a pattern structure, comprising:
providing a material layer;
forming a doped material layer on the material layer, wherein the doping concentration of the doped material layer is gradually changed from bottom to top, so that the etching removal rate of the doped material layer under the same etching condition is gradually reduced from bottom to top;
and forming an opening in the doped material layer by adopting a wet etching process, wherein the opening exposes the material layer.
2. The method as claimed in claim 1, further comprising, before forming the doped material layer on the upper surface of the material layer: and forming an undoped material layer on the upper surface of the material layer, wherein the undoped material layer is positioned below the doped material layer.
3. The method as claimed in claim 1, wherein the doping concentration of the doped material layer is gradually decreased from bottom to top.
4. The method as claimed in claim 1, wherein the doped material layer comprises doped silicon dioxide, and the doped impurities comprise one or more of boron and phosphorus.
5. The method as claimed in claim 1, wherein the doping concentration of the doped material layer is gradually changed in a gradient manner or continuously from bottom to top.
6. The method as claimed in claim 1, wherein the doping concentration of the doped material layer is between 0% and 10%.
7. The method as claimed in claim 1, wherein a concentration of impurity doping is gradually reduced during the forming of the doped material layer.
8. A graphic structure, comprising:
a layer of material;
the doping material layer is formed on the material layer, and the doping concentration of the doping material layer is gradually changed from bottom to top so that the etching removal rate of the doping material layer under the same etching condition is gradually reduced from bottom to top;
and the opening is formed in the doped material layer, and the material layer is exposed through the opening.
9. The graphic structure of claim 8, further comprising: a layer of undoped material located between the layer of material and the layer of doped material.
10. The pattern structure of claim 8, wherein the doping concentration of the doping material layer is gradually decreased from bottom to top.
CN202010338501.6A 2020-04-26 2020-04-26 Pattern structure and forming method thereof Pending CN111508835A (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595339A (en) * 1979-01-12 1980-07-19 Mitsubishi Electric Corp Preparation of semiconductor device
US4814041A (en) * 1986-10-08 1989-03-21 International Business Machines Corporation Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer
JPH06124944A (en) * 1992-10-14 1994-05-06 Seiko Epson Corp Semiconductor device
JPH07106537A (en) * 1993-09-30 1995-04-21 Olympus Optical Co Ltd Manufacture of solid-state image sensing device
JPH07335640A (en) * 1994-06-03 1995-12-22 Sony Corp Psg film and its forming method
US5679590A (en) * 1987-03-04 1997-10-21 Kabushiki Kaisha Toshiba Method for manufacturing contact hole for a nonvolatile semiconductor device
KR20020018119A (en) * 2000-08-29 2002-03-07 윤종용 Method of manufacturing semiconductor device employing insulating layer to confer three dimensional shape on conductive layer
CN101308787A (en) * 2007-05-15 2008-11-19 中芯国际集成电路制造(上海)有限公司 Etching method of polycrystalline silicon
US20130062683A1 (en) * 2011-09-09 2013-03-14 Yoshiaki Fukuzumi Semiconductor memory device and method of manufacturing the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595339A (en) * 1979-01-12 1980-07-19 Mitsubishi Electric Corp Preparation of semiconductor device
US4814041A (en) * 1986-10-08 1989-03-21 International Business Machines Corporation Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer
US5679590A (en) * 1987-03-04 1997-10-21 Kabushiki Kaisha Toshiba Method for manufacturing contact hole for a nonvolatile semiconductor device
JPH06124944A (en) * 1992-10-14 1994-05-06 Seiko Epson Corp Semiconductor device
JPH07106537A (en) * 1993-09-30 1995-04-21 Olympus Optical Co Ltd Manufacture of solid-state image sensing device
JPH07335640A (en) * 1994-06-03 1995-12-22 Sony Corp Psg film and its forming method
KR20020018119A (en) * 2000-08-29 2002-03-07 윤종용 Method of manufacturing semiconductor device employing insulating layer to confer three dimensional shape on conductive layer
CN101308787A (en) * 2007-05-15 2008-11-19 中芯国际集成电路制造(上海)有限公司 Etching method of polycrystalline silicon
US20130062683A1 (en) * 2011-09-09 2013-03-14 Yoshiaki Fukuzumi Semiconductor memory device and method of manufacturing the same

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