CN111506529A - High-speed SPI instruction response circuit applied to F L ASH - Google Patents
High-speed SPI instruction response circuit applied to F L ASH Download PDFInfo
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Abstract
The invention discloses a high-speed SPI instruction response circuit applied to F L ASH, which can adopt higher speed to communicate with external data by improving an address generating circuit and an instruction generating circuit in F L ASH, and can independently and comprehensively analyze specific operation instructions with longer paths, poorer time sequences and more combinational logics to improve the speed on the premise of not influencing other instruction speeds and not increasing idle clock cycles, on the other hand, when the F L ASH data is read, the address is sent to a storage unit in a segmentation mode, the storage unit determines information such as high-order/secondary high-order/low-order addresses in batches in advance, the data is output faster than a mode that the address is sent to a storage module only after the address is completely received, and meanwhile, the frequent address change generated in the SPI address receiving stage due to displacement is reduced, the reading speed is reduced due to influence on simulation judgment, the F L ASH market operation speed can be effectively improved, and the operation requirement of 5G internet on fast flash F L ASH is met.
Description
Technical Field
The invention relates to the field of information storage circuits, in particular to a high-speed SPI instruction response circuit applied to F L ASH.
Background
The F L ASH generally adopts the command of SPI protocol, it is simple and efficient, but with the development of 5G internet in recent years, there is a higher requirement for the speed of reading and writing of F L ASH, especially reading command, the traditional mode circuit can not realize the requirement of high speed.
The disadvantage of the above scheme is that the external clock has an upper limit problem due to the existence of the internal high-speed clock, and generally when the frequency of the external clock is greater than one fourth of the internal high-speed clock, the internal clock signal or the control signal will not be generated stably, resulting in that data cannot be transmitted; the power consumption is also large due to the presence of an internal high-speed clock; multi-pin multiplexing can lead to problems of unavailability under certain conditions.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a high-speed SPI instruction response circuit applied to F L ASH, and aims to solve the problem that the data transmission rate of a flash memory with serial output is low.
The technical scheme of the invention is that the high-speed SPI instruction response circuit applied to F L ASH comprises:
the SPI interface module receives command data and address data transmitted from the outside and outputs data read from a storage unit in the F L ASH;
the address generating circuit receives address data input by the SPI interface module, and carries out packet transmission on the address data to provide the address data to a storage unit in the F L ASH;
and the instruction generating circuit receives instruction data input by the SPI interface module, converts the instruction data from serial input into parallel transmission, performs combinational logic on specific operation instructions, registers the specific operation instructions, then sends the specific operation instructions to the storage unit and the address generating circuit in the F L ASH, performs combinational logic on unspecified operation instructions, and then sends the unspecified operation instructions to the storage unit and the address generating circuit in the F L ASH.
The technical scheme is optimized aiming at the problem of influencing the transmission speed, so that a high-speed SPI instruction response circuit which is higher than the common ASH speed of F L is designed, and specific operation instructions which are longer in path, poorer in time sequence and more in combinational logic are independently analyzed and comprehensively analyzed, so that the speed is improved on the premise of not influencing the speed of other instructions and not increasing the idle clock period, on the other hand, when the F L ASH data is read, the address is sent to a storage unit in the F L ASH in a segmented mode, the storage unit in the F L ASH determines information such as ARRAY/vector/W L in batches in advance, the data is output faster than a mode which only receives the address at last and is sent to a storage module, meanwhile, the frequent address change caused by shifting in an SPI address receiving stage is reduced, the reading speed is reduced by influencing analog judgment, and the reading speed is improved because the number of the address change is reduced and the high-bit data of the address is given in advance, and the reading speed of the F L ASH can meet the requirement of the ASH read operation of the current Internet market for fast flash F L ASH.
The high-speed SPI command response circuit applied to the F L ASH, wherein the SPI interface module includes an SPI output interface that receives an SPI input interface that receives externally transmitted command data and address data and outputs data read from a memory cell within the F L ASH.
The high-speed SPI command response circuit applied to the F L ASH, wherein the externally transmitted data received by the SPI interface module includes an external transmission clock signal SCK and an input data signal.
The high-speed SPI command response circuit applied to the F L ASH, wherein the external transmission clock signal SCK received by the SPI interface module includes first bit data input at a rising edge of the external transmission clock signal SCK and other bit data sequentially input at a following rising edge of the external transmission clock signal SCK after the shift processing.
The high-speed SPI instruction response circuit applied to the F L ASH is characterized in that the address generating circuit receives and analyzes address data transmitted through an SPI interface module from the outside, samples input signals at the rising edge of an external transmission clock signal SCK, shifts the input signals to obtain a first group of results, and sends the results to a storage unit in the F L ASH, samples the input signals at the rising edge of the external transmission clock signal SCK, shifts the results to obtain a second group of results, and sends the results to a storage unit in the F L ASH, samples the input signals at the rising edge of the external transmission clock signal SCK, shifts the results to obtain a third group of results, and sends the results to a storage unit in the F L ASH.
The high-speed SPI command response circuit applied to the F L ASH, wherein the address generation circuit comprises a first group of address generation circuits, a second group of address generation circuits, and a third group of address generation circuits connected in parallel:
the first group of address generating circuits are used for sampling input data signals on the rising edge of an external transmission clock signal SCK to obtain a first group of address data input results;
the second group of address generating circuits are used for sampling the input data signals at the rising edge of an external transmission clock signal SCK to obtain a second group of address data input results;
and the third group of address generating circuits are used for sampling the input data signals at the rising edge of the external transmission clock signal SCK to obtain a third group of address data input results.
The high-speed SPI instruction response circuit applied to F L ASH is characterized in that the first group of address generating circuits comprise a first D flip-flop, a second D flip-flop, a third D flip-flop, a first selector, a second selector and a third selector, a C L K end of each D flip-flop is directly connected with the external transmission clock signal SCK, a D end of each first D flip-flop is connected with a Y end of the first selector, a D end of each second D flip-flop is connected with a Y end of the second selector, a D end of each third D flip-flop is connected with a Y end of the third selector, a Q end of each first D flip-flop is connected with an A end of the first selector and a B end of the second selector, a Q end of each second D flip-flop is connected with the A ends of the second selector and the third selector, a Q end of each third D flip-flop is connected with the A ends of the third selectors, a Q end of each third D flip-flop is used as an address in ASH L, a storage unit of the ASH is used as a storage unit, a storage unit of the ASH is connected with a data unit, and a storage unit is connected with a storage unit, and a storage unit is connected with a storage unit, wherein the storage unit, and a storage unit, the storage unit is connected with a storage unit, the storage.
The address generation circuit can flexibly segment the received address data according to the scale of the F L ASH chip and the characteristics of the analog circuit.
The high-speed SPI command response circuit applied to the F L ASH, wherein the command generation circuit comprises a shift module, a normal command module and an optimized command module:
the shift module synchronizes input data by using the rising edge of the external transmission clock signal SCK and transmits a shift result to a common instruction module and an optimized instruction module;
the ordinary instruction module uses the result combination generated by the shift module to provide the instruction to the storage unit and the address generating circuit in the F L ASH;
the optimized instruction block latches the combination of the results of the shift block with the rising edge of the external transfer clock signal SCK and provides the instruction result to the memory cell and address generation circuit within F L ASH.
The high-speed SPI instruction response circuit applied to F L ASH is characterized in that the shift module comprises a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, a fourth selector, a fifth selector, a sixth selector and a seventh selector, wherein the C L K end of each D flip-flop is directly connected with the external transmission clock signal SCK, the D end of the fourth D flip-flop is connected with the Y end of the fourth selector, the D end of the fifth D flip-flop is connected with the Y end of the fifth selector, the D end of the sixth D flip-flop is connected with the Y end of the sixth selector, the D end of the seventh D flip-flop is connected with the Y end of the seventh selector, the Q end of the fourth D flip-flop is connected with the A end of the fourth selector and the B end of the fifth selector, the Q end of the fifth D flip-flop is connected with the A end of the fifth selector and the B end of the sixth selector, the Q end of the sixth D flip-flop is connected with the A end of the sixth selector, the Q end of the sixth selector is connected with the B end of the seventh selector, and the Q end of the fifth D flip-flop is connected with the data signal input control module;
the normal instruction block is composed of a first combinational logic unit, and the result of the first combinational logic unit is provided to a storage unit and an address generation circuit in the F L ASH;
the optimization instruction module is composed of a second combination logic unit and an eighth D trigger, wherein the input end of the second combination logic unit is connected with Y ends of all selectors of the shift module, the result of the second combination unit is connected with the eighth D trigger, and the Q end of the eighth D trigger is provided for a storage unit and an address generating circuit in the F L ASH.
In the technical scheme, specific operation instructions with longer paths, poorer time sequences and more combinational logics are analyzed independently and comprehensively through an optimized instruction module, registers are added on the paths of the instructions, the combinational logics among the registers are optimized, the combined paths from instruction input to instruction output are reduced, although the possibility of area increase is seen from the front end, because the time sequence is more optimized than before, the speed is improved after DC (design compiler) and PT (PrimeTime), the idle clock area is not increased or even reduced, the optimized instructions can be separated from the combined logic range of common instructions, new instructions can be provided for an address generation circuit and a storage module after the rising edge of a clock comes, the common instructions need to identify the instructions through the combined logic and are slow relatively, the optimized instructions can be used for the instructions with lower speed requirements, and the optimized circuits can be used for high-speed instructions, so that the balance processing of the speed and the area can be realized, and the read-write operation of the F L ASH can be improved.
The high-speed SPI instruction response circuit applied to the F L ASH is characterized in that two optimized instruction modules are arranged, and the two optimized instruction modules are consistent in structure.
The invention has the advantages that the high-speed SPI instruction response circuit applied to the F L ASH is improved through the address generation circuit and the instruction generation circuit inside the F L ASH, so that higher-speed data communication can be adopted.
Drawings
Fig. 1 is a schematic diagram showing the connection of the high-speed SPI command response circuit applied to the F L ASH in the present invention.
FIG. 2 is a schematic diagram of the connection of the address generating circuit of the present invention.
FIG. 3 is a schematic diagram of the connection of the instruction generating circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1 to 3, a high-speed SPI command response circuit applied to F L ASH includes:
an SPI interface module 1 that receives command data and address data transmitted from the outside and outputs data read from a memory cell in F L ASH;
an address generation circuit 3 for receiving address data input from the SPI interface module 1, and performing packet transmission of the address data to supply the address data to a storage unit in the F L ASH;
the command generating circuit 2 receives command data input by the SPI interface module 1, converts the command data from serial input to parallel transmission, performs combinational logic on specific operation commands, registers the specific operation commands, and then sends the specific operation commands to the storage unit and the address generating circuit 3 in the F L ASH, and performs combinational logic on unspecified command data, and then sends the unspecified operation commands, which are registered first and then sent to the storage unit and the address generating circuit 3 in the F L ASH.
In some embodiments, the externally transmitted data received by the SPI interface module 1 includes an externally transmitted clock signal SCK and an input data signal.
In some embodiments, the SPI interface module 1 includes an SPI output interface that receives an SPI input interface of externally transmitted command data and address data and outputs data read from a memory cell in the F L ASH.
In some embodiments, the external transmission clock signal SCK received by the SPI interface module 1 includes first bit data input at a rising edge of the external transmission clock signal SCK, and other bit data sequentially input at a following rising edge of the external transmission clock signal SCK after the shift processing.
In the present technical solution, the address generating circuit 3 receives and analyzes address data transmitted from the outside through the SPI interface module 1, samples an input signal at a rising edge of an external transmission clock signal SCK, shifts the input signal to obtain a first set of results (higher address/ARRAY address), and sends the results to a memory cell in F L ASH, so that the memory cell in F L ASH can lock a region to be operated in advance when the address is not completely received, samples the input signal at a subsequent rising edge of the external transmission clock signal SCK, shifts the input signal to obtain a second set of results (middle address/vector address), and sends the results to a memory cell in F L ASH, so that the memory cell in F L ASH can further lock a portion to be operated when the address is not completely received, samples the input signal at a subsequent rising edge of the external transmission clock signal SCK, shifts the input signal to obtain a third set of results (lower address/W L address), and sends the results to a memory cell in F L ASH, so that the memory cell in F L determines the region to be operated quickly.
Specifically, as shown in fig. 2 (CK is not shown in fig. 2, and all clocks clk to SPI are connected), the address generation circuit 3 includes a first group of address generation circuits, a second group of address generation circuits, and a third group of address generation circuits connected in parallel:
a first group of address generating circuits for sampling the input data signal at the rising edge of the external transmission clock signal SCK to obtain a first group of address data input results (high address/ARRAY address);
a second group of address generating circuits, configured to sample the input data signal at a rising edge of the external transmission clock signal SCK to obtain a second group of address data input results (a median address/a vector address);
and a third group of address generation circuits for sampling the input data signal at the rising edge of the external transfer clock signal SCK to obtain a third group of address data input results (low order address/W L address).
In this embodiment, as shown in fig. 2, the first group of address generating circuits is composed of 3D flip-flops (including a first D flip-flop, a second D flip-flop and a third D flip-flop) and 3 two-out-of-one selectors (including a first selector, a second selector and a third selector), the C L K terminal of each D flip-flop is directly connected to the external transmission clock signal SCK (i.e., the C L K terminals of the first D flip-flop, the second D flip-flop and the third D flip-flop are directly connected to the external transmission clock signal SCK), the D terminal of each D flip-flop is correspondingly connected to the Y terminal of one two-out-of-one selector (the D terminal of the first D flip-flop is connected to the Y terminal of the first selector, the D terminal of the second D flip-flop is connected to the Y terminal of the second selector, the D terminal of the third D flip-flop is connected to the Y terminal of the third selector, the Q terminal of the first D flip-flop is connected to the Y terminal of the first selector, the second selector, the Q terminal of the second selector is connected to the second selector, the third selector is connected to the third selector, the third selector is connected to the third selector, the third selector is connected, the.
Therefore, the storage units in the F L ASH can obtain three groups of 3-bit addresses in batches, the area to be operated can be quickly determined, the number of times of address change to the storage units in the F L ASH is reduced, the operation speed of the storage units in the F L ASH is favorably improved, address segmentation supply is realized through the first group of address generating circuits, the second group of address generating circuits and the third group of address generating circuits, the read-write speed of the whole circuit is improved, particularly the read speed is improved, and the 9-bit addresses are taken as an example to divide the addresses into three sections and supply the three sections to the storage units in the F L ASH.
In some embodiments, as shown in fig. 3 (CK is not shown in fig. 3, and all of the clocks clk are connected to SPI), the command generating circuit 2 includes a shift module, a normal command module, and an optimized command module:
the shift module synchronizes input data by using the rising edge of the external transmission clock signal SCK and transmits a shift result to a common instruction module and an optimized instruction module;
the normal instruction block provides the instruction to the storage unit and address generation circuit 3 in the F L ASH by the result combination generated by the shift block;
the optimized instruction block latches the combination of the results of the shift block with the rising edge of the external transfer clock signal SCK and supplies the instruction result to the memory cell and address generation circuit 3 in F L ASH.
In this embodiment, as shown in fig. 3, the shift module is composed of 4D flip-flops (including a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop and a seventh D flip-flop) and 4 one-out-of-two selectors (including a fourth selector, a fifth selector, a sixth selector and a seventh selector), wherein a C L K terminal of each D flip-flop is directly connected to the external transmission clock signal SCK, a D terminal of each D flip-flop is correspondingly connected to a Y terminal of one-out-of-two selector (a D terminal of the fourth D flip-flop is connected to a Y terminal of the fourth selector, a D terminal of the fifth D flip-flop is connected to a Y terminal of the fifth selector, a D terminal of the sixth D flip-flop is connected to a Y terminal of the sixth selector, a D terminal of the seventh D flip-flop is connected to a Y terminal of the seventh selector), a Q terminal of the fourth D flip-flop is connected to a terminal of the fourth selector and a terminal of the fifth selector, a terminal of the same fifth D flip-flop, a terminal of the fifth D flip-flop is connected to a terminal of the fifth selector, a counter, and a terminal of the seventh flip-flop is connected to a data selection module, and a terminal of the fifth flip-flop, and a data selection module is connected to a, and a data selection unit, wherein the fifth flip-selection unit is connected to the fifth flip-flop, and the fifth flip-flop;
the normal instruction block is composed of a first combinational logic unit, and the result of the first combinational logic unit is provided to the memory location and the address generation circuit 3 in the F L ASH;
the optimization instruction module is composed of a second combination logic unit and an eighth D trigger, the input end of the second combination logic unit is connected with Y ends of all selectors of the shift module, the result of the second combination unit is connected with the eighth D trigger, and the Q end of the eighth D trigger is provided for a storage unit and an address generating circuit 3 in the F L ASH.
Specifically, the optimization instruction module may set one or more of the optimization instruction modules according to actual needs. In this embodiment, two optimization instruction modules are provided, and the two optimization instruction modules have the same structure.
The embodiment mainly improves the address generating circuit 3 and the command generating circuit 2 in the F L ASH, so that the communication with external data can be realized at a higher speed, and other components, transmission among the components and control implementation schemes of the high-speed SPI command response circuit applied to the F L ASH, and connection schemes (such as high-level Vcc, ground GND, chip selection signals CS #, W # and HO L D #) with the outside can be the same as the prior art.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A high speed SPI command response circuit for use in an F L ASH, comprising:
an SPI interface module (1) for receiving command data and address data transmitted from outside and outputting data read from a memory cell in F L ASH;
an address generation circuit (3) which receives address data input by the SPI interface module (1), and performs packet transmission on the address data to provide the address data to a storage unit in an F L ASH;
and the instruction generating circuit (2) receives instruction data input by the SPI interface module (1), converts the instruction data from serial input into parallel transmission, performs combinational logic on specific operation instructions, registers the specific operation instructions and then sends the specific operation instructions to the storage unit and the address generating circuit (3) in the F L ASH, and performs combinational logic on non-specific operation instructions and then sends the non-specific operation instructions and the non-specific operation instructions to the storage unit and the address generating circuit (3) in the F L ASH.
2. The high-speed SPI command response circuit according to claim 1 applied to F L ASH, characterized in that the SPI interface module (1) comprises an SPI output interface that receives an SPI input interface of externally transmitted command data and address data and outputs data read from a memory cell within F L ASH.
3. The high-speed SPI command response circuit according to claim 1, applied to F L ASH, characterized in that the externally transmitted data received by the SPI interface module (1) comprises an external transmission clock signal SCK and an input data signal.
4. The high-speed SPI instruction response circuit according to claim 3, applied to F L ASH, characterized in that the external transmission clock signal SCK received by the SPI interface module (1) includes first bit data input at a rising edge of the external transmission clock signal SCK and other bit data sequentially input at a following rising edge of the external transmission clock signal SCK after the shift processing.
5. The high-speed SPI instruction response circuit of claim 1 for F L ASH is characterized in that said address generating circuit (3) receives and resolves the address data externally transmitted through SPI interface module (1), samples the input signal on the rising edge of external transmission clock signal SCK and shifts it to get the first set of results and sends it to the storage unit in F L ASH, samples the input signal on the rising edge of external transmission clock signal SCK and shifts it to get the second set of results and sends it to the storage unit in F L ASH, samples the input signal on the rising edge of external transmission clock signal SCK and shifts it to get the third set of results and sends it to the storage unit in F L ASH.
6. The high-speed SPI instruction acknowledge circuit according to claim 5 applied to F L ASH, characterized in that said address generating circuit (3) comprises a first group of address generating circuits, a second group of address generating circuits and a third group of address generating circuits connected in parallel:
the first group of address generating circuits are used for sampling input data signals on the rising edge of an external transmission clock signal SCK to obtain a first group of address data input results;
the second group of address generating circuits are used for sampling the input data signals at the rising edge of an external transmission clock signal SCK to obtain a second group of address data input results;
and the third group of address generating circuits are used for sampling the input data signals at the rising edge of the external transmission clock signal SCK to obtain a third group of address data input results.
7. The high-speed SPI instruction response circuit for F L ASH according to claim 6 wherein said first group of address generating circuits includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a first selector, a second selector and a third selector, each D flip-flop having its C L K terminal directly connected to said external transmission clock signal SCK, the D terminal of the first D flip-flop being connected to the Y terminal of the first selector, the D terminal of the second D flip-flop being connected to the Y terminal of the second selector, the D terminal of the third D flip-flop being connected to the Y terminal of the third selector, and the Q terminal of the first D flip-flop being connected to the A terminal of the first selector and the B terminal of the second selector, the Q terminal of the second D flip-flop being connected to the A terminal of the second selector and the B terminal of the third selector, the Q terminal of the third D flip-flop being connected to the A terminal of the third selector, the Q terminal of the third D flip-flop being used as the F terminal of the address, the Q terminal of the second selector being connected to the second selector, the second D flip-flop being connected to the second selector, the Q terminal of the ASH flip-flop being connected to the second selector, and the second D flip-flop being connected to the second selector, the second selector being connected to the second selector, the ASH data unit being connected to the highest address generating unit L, and the ASH being connected to the second selector, the third selector being connected to the ASH data unit being connected to the ASH being connected to the third selector, the ASH being connected to the ASH, the third selector, and the third selector, the AS.
8. The high-speed SPI instruction response circuit according to claim 1, applied to F L ASH, characterized in that said instruction generation circuit (2) comprises a shift module, a normal instruction module and an optimized instruction module:
the shift module synchronizes input data by using the rising edge of the external transmission clock signal SCK and transmits a shift result to a common instruction module and an optimized instruction module;
the general instruction module uses the result combination generated by the shift module to provide the instruction to a storage unit and an address generating circuit (3) in the F L ASH;
the optimized instruction block latches the combination of the results of the shift block with the rising edge of the external transfer clock signal SCK and supplies the instruction result to the memory cell and address generation circuit (3) within F L ASH.
9. The high-speed SPI instruction response circuit of claim 8 for F L ASH wherein said shift module comprises a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, a fourth selector, a fifth selector, a sixth selector, and a seventh selector, wherein terminal C L K of each D flip-flop is directly connected to said external transmission clock signal SCK, terminal D of the fourth D flip-flop is connected to terminal Y of the fourth selector, terminal D of the fifth D flip-flop is connected to terminal Y of the fifth selector, terminal D of the sixth D flip-flop is connected to terminal Y of the sixth selector, terminal D of the seventh D flip-flop is connected to terminal Y of the seventh selector, terminal Q of the fourth D flip-flop is connected to terminals A of the fourth selector and B of the fifth selector, terminal Q of the fifth D flip-flop is connected to terminals A of the fifth selector and B of the sixth selector, terminal Q of the sixth D flip-flop is connected to terminal Q of the sixth selector, and the terminal Q of the sixth flip-flop is connected to terminal of the seventh selector, and the selection module is connected to the output of the logic data selection unit;
the ordinary instruction block is composed of a first combinational logic unit, and the result of the first combinational logic unit is provided to a storage unit and an address generating circuit (3) in the F L ASH;
the optimization instruction module is composed of a second combination logic unit and an eighth D trigger, the input end of the second combination logic unit is connected with Y ends of all selectors of the shift module, the result of the second combination unit is connected with the eighth D trigger, and the Q end of the eighth D trigger is provided for a storage unit and an address generating circuit (3) in the F L ASH.
10. The high-speed SPI command response circuit according to any one of claims 8 and 9 for F L ASH, wherein two of said optimization command modules are provided, and the structures of the two optimization command modules are identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010613528.1A CN111506529B (en) | 2020-06-30 | 2020-06-30 | High-speed SPI instruction response circuit applied to FLASH |
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| CN202010613528.1A CN111506529B (en) | 2020-06-30 | 2020-06-30 | High-speed SPI instruction response circuit applied to FLASH |
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| CN111506529A true CN111506529A (en) | 2020-08-07 |
| CN111506529B CN111506529B (en) | 2020-10-16 |
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| CN202010613528.1A Active CN111506529B (en) | 2020-06-30 | 2020-06-30 | High-speed SPI instruction response circuit applied to FLASH |
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| CN111506529B (en) | 2020-10-16 |
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